JPS626357A - Priority control system for channel - Google Patents

Abstract

PURPOSE:To shorten the maximum waiting time by providing a counter which counts up at every reception of a data transfer request from a channel and changing the priority for the reception of the channel data transfer request signals in response to the count value of the counter. CONSTITUTION:The channel data transfer request signals 5-7 of the 1st-3rd channels 1-3 are supplied to input selectors 14a-14c forming a selector circuit 14. The outputs 15-17 of selectors 14a-14c are supplied to a priority encoder 18. The data transfer request signal sent from the encoder 18 is supplied to a main memory device 4. While a channel address 22 is sent to the memory device 4 via an address converting circuit 24. A counter 21 counts up at every time the data transfer requests are received from channels 1-3. Then the order of inputs given to the encoder 18 from the circuit 14 is changed in response to the count value of the counter 21.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a channel priority control method in a data processing device equipped with a plurality of channels.

[Prior Art] In a data processing device equipped with a plurality of channels, when data transfer requests are simultaneously issued to the main storage device from the plurality of channels, which channel's transfer request should be accepted with the highest priority? It is necessary to determine the

FIG. 4 is a block diagram of a data processing device using a conventional priority control system. In the figure, (1) is the first channel, (2) is the second channel, (3) is the third channel, (4) is the main memory, (5) to (7) are channel data transfer request signals output from the first channel (1) to the third channel (3), respectively, and (8) is the channel data transfer request signal output from the first channel (1) to the third channel (3), respectively. A priority encoder that receives Zenel data transfer request signals @ (5) to (7) as input, (9) is a data transfer request signal to the main storage device (4) output from the priority encoder (8), (10) is the channel address output from the priority encoder (8) and sent to the main memory (4), and (11) to (13) are the first channels (1) to 1 from the main memory (4). Third channel (3)
This is a data transfer acceptance signal sent to each.

In addition, although the number of channels is set to "3" in FIG. 4, it does not matter how many channels there are. Furthermore, the priority encoder (8) may be located in the main memory (4) or in a channel control device (not shown).

Next, the operation will be explained. 1st channel (1) to 3rd
Channel (3) generates respective channel data transfer request signals (5) to (7) when data transfer is required between main storage device (4). The priority encoder (8) outputs a data transfer request signal (9) when no data transfer request signal is generated from any channel.
does not occur. Also, at this time, the channel address (1
0) has no meaning. Next, when a channel data transfer request signal is generated from any one channel, the priority encoder (8) generates a data transfer request signal (9) and sets the address of that channel to the channel address (10). ). On the other hand, if the main storage device (4) can accept the data transfer request, it determines which channel to transfer data to based on the channel address (10) and transfers the data to that channel. A data transfer acceptance signal is sent only at the same time as the data transfer is performed.

Once the data transfer request has been accepted, the channel stops sending the channel data transfer request signal once the transfer of the required data is completed.

If channel data transfer request signals are generated from multiple channels at the same time, the priority encoder (8) selects the channel with the highest priority from among those channels and assigns the address of the channel with the highest priority. is output as the channel address (10).

By the way, since the priority encoder (8) has a fixed priority determined by the physical connection order of its input signals, the physical connection order of the channel data transfer request signals (5) to (7) from each channel Priority among channels is fixedly determined by the connection order. In this example, the first channel has the highest priority, and the third channel has the lowest priority.

FIG. 5 is a timing chart showing the order in which data transfer requests are received under such a priority relationship.

In FIG. 5, when the main storage device (4) is able to accept a data transfer request, it takes time T from the time the main storage device (4) accepts the request until the data transfer is completed.

Further, it is assumed that the first channel (1) to the third channel (3) require data transfer for every four devices. Note that ↑ in the figure indicates that data transfer is necessary for each channel, and ↓ indicates that data transfer has been performed.
a) At time t1, all channels simultaneously
This shows a case where a data transfer request signal is issued.

First, when a data transfer request of the first channel (1) is accepted at time t1 according to the priority order and data transfer is performed, the first channel (1) stops generating the channel data transfer request signal (5).

Next, at time t2, the second channel (2), and at time t3, the third channel (2)
Channel (3) is connected. At time t4, there is no request from any channel, so it becomes an idle cycle. Here, from time t5 to time t7, the main memory (4
) becomes unable to accept data transfer requests, the channel data transfer request signal (5) of the first channel (1,) output at time t5 is accepted at time t8, but at the same time the next data Since the need for transfer has arisen, the channel data transfer request signal (5) remains generated, so that a request for the first channel (1) is subsequently accepted at time t9.

In this way, the original state returns at time t17, but during this period, the waiting time until the channel data transfer request signal (7) of the third channel (3), which has the lowest priority, is accepted is It will be longer than . The figure shows the maximum and average waiting times from when the need for data transfer arises until it is accepted in each channel from time t5 to time tlB. The maximum value is 8-ton, and the average value is 6.3-ton. Also, the fifth
Figure (b) is a timing chart when the channel data transfer request signals (5) to (7) of the first channel (1) to the third channel (3) are generated at times tl, t3, and t2, respectively. However, in this case as well, the third channel (
The maximum value and average value of the waiting time in 3) are 7 and 5, respectively.

[Problems to be Solved by the Invention] As described above, in the conventional channel priority control system, the priorities are fixed, so the waiting time until a data transfer request is accepted is shorter for channels with lower priority. There was a problem in that the transfer time became long, the transfer performance deteriorated, and only low-speed input/output devices could be connected.

On the other hand, in order to achieve the same performance as the upper channel, it is necessary to increase the amount of data buffer to account for the latency time, which leads to an increase in the amount of hardware. Therefore, there is a problem in that more data buffers than necessary are prepared even for the upper channel where the waiting time is short, resulting in an extremely uneconomical configuration.

This invention was made to solve the above-mentioned problems, and it reduces the maximum waiting time until a data transfer request is accepted with only a slight increase in the amount of hardware.
It is an object of the present invention to provide a channel priority control method that can connect high-speed input/output devices and suppress variations in transfer performance of each channel.

[Means for Solving the Problems] The channel priority control method according to the present invention includes a counter that increments each time a data transfer request is received from a channel, and the data transfer request from each channel input to the priority circuit is The priority order for receiving channel data transfer request signals is changed according to the count value of the counter. In another invention, the channels are divided into groups, and the priority order of the channels within the group is changed based on the count value of the counter.

[Operation] The acceptance order of channel data transfer request signals from each channel input to the priority circuit is changed according to the count value of the counter. Therefore, the above counter is set to N
In the case of a forward counter, the priority order goes around every time N data transfer requests are accepted, and the waiting time is averaged.

Furthermore, in another invention, the priority order changes among channels within a group.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, and in the figure, (1) to (7) and (11) to (13) are the same as the conventional configuration shown in FIG. 4. Further, (14) is a selector circuit consisting of three human-powered selectors (14a) to (14c), and the channel data transfer request signal (5) of the first channel (1) is transmitted to each selector (14a) to (14c). U O
Ot+ input.

The "01" input and the "'10" input are input in this order.

Similarly, the channel data transfer request signal (6) of the second channel (2) is input to the ``01'' and ``''oo'' inputs of each selector (14a) to (14c).

“10” input, and also the third channel (3)
The data transfer request signal (7) is transmitted to each selector (14a) to (
u 10 te input'(('
) outputs (15) to (17) are input to a priority encoder (18).

(1) is a data transfer request signal output from the priority encoder (18) and sent to the host device (4), and (20) is a data transfer acceptance signal (11) to be sent to each channel. An OR gate with (13) as input,
(21) uses the output of the OR gate (20) as a clock input, and each time the clock input occurs, the count value is “
The counter (22) increments as "oo" → "01" → "10" → "o o", and its output becomes the selection signal of the selector (14), from the priority encoder (1゛8) The output channel address (23) is determined by the output of the counter (21).
2) into a real channel address (24) and sends it to the main memory (4).

In FIG. 1, the number of channels is set to "3" for comparison with FIG. 4, but any number may be used. In that case, it goes without saying that the number of selectors in the selector circuit (14) and the number of bits in the counter (21) will change.

Furthermore, the function of the priority encoder (18) itself is exactly the same as that of the conventional one. Further, in this embodiment, when the output of the counter (21) is 'oo', the address conversion circuit (23) converts the input channel address <2
2> without converting it as is, the actual channel address (24
), but the counter (21) output is “'01”.
”, the first channel is converted to the second channel, the second channel is converted to the third channel, and the third channel is converted to the first channel,
Also, when the output of the counter (21) is 10'', the first channel becomes the third channel, the second channel becomes the first channel, and the third channel becomes the third channel.
It has the function of converting a channel into a second channel. This is a priority encoder (18) as described later.
This is because the channel address supplied to the main memory device (4) is returned to the original real channel address since the input order to the main memory device (4) is changed.

Now, when the output of the counter (21) is "o o", the channel data transfer request signals (5) to (
7) is input as is to the priority encoder (18) in the order of signals (15) to (17). Therefore, the first channel (1) has the highest priority, and the second channel (1) has the highest priority.
Channel (2) and third channel (3). Next, when a data transfer request for any channel is accepted and one of the data transfer acceptance signals (11) to (13) is generated, the counter <21> is sent via the OR gate (20).
A clock signal is input to the counter (21), and the output of the counter (21) is “01”.
It becomes Pa. Then, each selector (14a) ~(
14G>, the input signals (15) to (17) of the priority encoder (18) are the second channel (2), the third channel (3), and the first channel. Channel data transfer request signals (6), (7), and (5) of channel (1) are respectively input, and the priorities are the second channel, the third channel, and the first channel. When a channel data transfer request signal is generated from any channel in this state, the priority encoder (18) assumes that the data transfer request signal is connected to the first channel, second channel, and third channel in that order. generates a channel address (22), which is then sent to the address conversion circuit (22).
3) converts it into a real channel address (24) based on the information output from the counter (21) and sends it to the main memory (4). In response, when a data transfer acceptance signal is output from the main storage device (4), a clock signal is input to the counter (21), and the output of the counter (21) becomes "10". Then, each selector (14a) to (14c
) 4$ 10 IT large input In order to be selected, input signals (15) to (18) of the priority encoder (18)
17), the third channel (3), the first channel (
1), channel data transfer request signals (7), (5), and (6) of the second channel (2) are respectively input, and the priority is given to the third channel, the first channel, and the second channel. Become.

Next, when a new data transfer acceptance signal is generated, the counter (21) returns to "00", so the priority is set again to the first channel and the second channel.

This will be the third channel. In this way, in this embodiment, the priority order is cyclically changed each time a data transfer request is received from each channel.

FIG. 2 shows a timing chart in this embodiment when a data transfer request is generated from the channel under the same conditions as shown in FIG. 5 above. Figure 2(a)
In this case, the maximum waiting time from time t5 to t16 is 6 on the 3rd channel, and the maximum average value is 5 on the 3rd channel.
He is the king. On the other hand, the maximum holding time in FIG. 2(b) is 57. The maximum average value is still the 4th one in the third channel. The reason why the waiting time of the third channel is large in both FIGS. 2(a) and (b) is that when the main storage device (4) is not ready to receive data and all data transfer requests are made to wait, it happens that the waiting time of the third channel is large. This is because the priority of the channel was the lowest. As can be seen from the above description, it is clear that the maximum waiting time is shorter than in the conventional example, and the variation in waiting time of each channel is reduced.

Note that if all channels are combined into one and their priorities are changed cyclically as explained above, the waiting time for the higher-ranking channels will naturally be longer than when the priorities are fixed. A problem arises when high speed is required for the upper channel.

Therefore, the channels are classified into multiple groups consisting of one or more channels, the priority order is fixed between the groups, and within each group, the priority order is changed as described above each time a data transfer request is accepted from a channel belonging to that group. Change it cyclically like this. In this way, the latencies of channels within each group are averaged out, while channels in higher groups have lower latencies than channels in lower groups, preserving the high speed of channels belonging to higher groups. can do. In other words, if input/output devices that require high speed performance are connected to a higher-level group, data transfer performance will not be impaired.

By the way, in the embodiment of FIG. 1, the third channel (3)
The channel data transfer request signal (7) of 1 is directly connected to the lowest input of the priority encoder (18) to fix the priority at the lowest level, and 1 is used as a counter (21).
A bit counter is used, and two selectors are used as the selector circuit (14), and the first channel (1) and the second channel
Figure 3 shows a timing chart when the priority order of channel (2) is alternately changed. It can be seen that the time has been significantly improved.

[Effects of the Invention] As described above, according to the present invention, a counter is provided that increments every time a data transfer request for any channel is accepted, and the priority level for accepting data transfer requests is determined according to the count value of this counter. This makes it possible to shorten the maximum waiting time and suppress variations in transfer performance of each channel with just a slight increase in the amount of hardware, allowing high-speed input to any channel. This has the advantage that output devices can be connected and the transfer performance of each channel can be flexibly set. Furthermore, if channels are divided into groups according to their priorities and the priorities are changed within each group, the waiting time for a predetermined group can be shortened and high speed can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a data processing device to which the present invention is applied, FIG. 2 is a timing chart for explaining the operation of the embodiment of FIG. 1, and FIG. A timing chart for explaining the operation of a modified example of the embodiment, FIG. 4 is a block diagram of a data processing device using the conventional method, and FIG. 5 shows the operation of the conventional data processing device shown in FIG. It is a timing chart for explanation. (1) to (3)...channels, (4)...main memory, (5) to (7)...data transfer request signals from each channel, (11) to (13)...・Data transfer acceptance signal to each channel, (14)...Selector circuit, (1
8)...Priority encoder, (21)...
·counter. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Procedural amendment filed May 14, 1986 1. Indication of the case Patent application No. 145268 1988 2.
Title of the invention: 3. Name of the invention: 3. Person making the amendment: 5. Scope of claim to be amended. 6. Contents of amendment (1) The claims are amended as shown in the attached sheet. 2. Claims (1) In a channel priority control method for accepting data transfer requests inputted to a storage device from a plurality of channels according to a predetermined priority order, each time a channel data transfer request is accepted, an increment is made. 1. A channel priority control method, characterized in that a counter is provided, and the priority order is cyclically changed according to the count value of the counter. (2) In a channel priority control method that accepts data transfer requests input to a storage device from multiple channels according to a predetermined priority, channels are classified into groups according to their priorities, and data transfer requests for channels are A channel priority control method, characterized in that a counter is provided that increments each time a channel is accepted, and the priority order in ±domain stops within a group is cyclically changed according to the count value of this counter. (3) The channel priority control system according to claim 2, wherein the priority order is fixed between each group.

Claims (3)

[Claims] (1) In a channel priority control method in which data transfer requests input to a storage device from multiple channels are accepted according to a predetermined priority order, a counter is provided that increments each time a data transfer request for a channel is accepted. A channel priority control method characterized in that the priority is cyclically changed according to a count value of . (2) In a channel priority control method that accepts data transfer requests input to a storage device from multiple channels according to a predetermined priority, channels are classified into groups according to their priorities, and data transfer requests for channels are 1. A channel priority control method, characterized in that a counter is provided that advances each time a channel is received, and the priority of channels within a group is cyclically changed according to the count value of this counter. (3) The channel priority control system according to claim 2, wherein the priority order is fixed between each group.