JPS6263462A - Integrated circuit - Google Patents

Abstract

PURPOSE:To make it possible to input information for measuring the characteristics of DC and AC in an integrated circuit simply, by switching buffer circuits into a cascade connection state. CONSTITUTION:When a switching signal is inputted to a switching signal input terminal 10, information in a first buffer circuit 4-0 is inputted to a second buffer circuit 4-1 by switching circuit 5-1$5-n. All the buffer circuits 4-0-4-n in a peripheral buffer part 2 are connected in cascade. The information, which is inputted to the input terminal 7-0, is circulated through the peripheral buffer part 2 in an integrated circuit 1 and outputted from an output terminal 7-n. Therefore, measurement of the characteristics of the high/low level logical amplitudes at the output terminal, which is provided in the peripheral buffer part 2, can be performed without inputting a function checking pattern in an internal logic circuit part 3. Since the information, which is inputted to the input terminal 7-0, is circulated through the peripheral buffer part 2 in the integrated circuit 1 and outputted from the output terminal 7-n, the delay time from the input terminal 7-0 to the output terminal 7-n is measured and the AC characteristics are obtained. The delay time in all the buffer circuits 4-0-4-n in the integrated circuit 1 can be measured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to means for testing integrated circuits. In particular, it relates to testing means for peripheral buffer circuits.

〔overview〕

In an integrated circuit having buffer circuits at the input and output ends of a logic circuit, the present invention enables information on DC and AC characteristic measurements of the integrated circuit to be easily input by switching the buffer circuits to a cascade connection state. This is how it was done.

[Conventional technology]

Measurement of DC and AC electrical characteristics of integrated circuits
Thousands to hundreds of people test the functional test patterns using testing machines,
Measurements are performed by activating the logic path from the input terminal to the output terminal. There is also a method of easily measuring the AC characteristics by measuring the oscillation frequency of a ring oscillator in which an odd number of stages of inverter logic are connected.

[Problem that the invention seeks to solve]

In the former test method mentioned above, as the logic circuits realized on integrated circuits become more complex and the degree of integration increases, it takes a lot of time to create functional test patterns used for inspection, and The disadvantage is that the number of patterns created is enormous.

Additionally, as the depth size of integrated circuits increases, the method of using a ring oscillator, which can easily measure AC characteristics,
There is a drawback that configuring only a portion of an integrated circuit is not sufficient to measure variations in characteristics within a chip.

The present invention aims to eliminate such drawbacks by providing an integrated circuit equipped with a means for easily inputting information for measuring the DC and AC characteristics of a complex and highly integrated circuit. With the goal.

[Means for solving problems]

The present invention includes a plurality of sets of input terminals and output terminals, an internal logic circuit, and a plurality of buffer circuits inserted for each set on a path between the input terminals and output terminals and the logic circuit. The integrated circuit is characterized by comprising a switching means for temporarily switching the plurality of buffer circuits to a cascade connection state.

Here, the cascade connection state refers to a state in which the output of the buffer circuit at the previous stage is connected to the input of the buffer circuit at the next stage.

[For production]

Due to the operation of the switching means, information is input from the input terminal to the logic circuit via the buffer circuit, and the output of this logic circuit is output to the output terminal via the buffer circuit.
The buffer circuits transition to a cascade-connected state. Thereby, various tests can be performed by measuring the characteristics of high/low level logic amplitudes and measuring the delay time of the buff 21 circuit without being influenced by the logic circuit.

〔Example〕

Hereinafter, a circuit according to an embodiment of the present invention will be explained based on the drawings.

The figure is a connection diagram showing the configuration of an embodiment of the present invention. The integrated circuit 1 includes a peripheral buffer section 2 and an internal logic circuit section 3, where the peripheral buffer section 2 includes a buffer circuit 4,
A switching circuit 5 is provided with a buffer circuit 4 connected in series.

The operation of the circuit according to the embodiment of the present invention will be explained based on the drawings.

When the switching signal is input from the switching signal input terminal 10, the information of the first buffer circuit 4-0 is inputted to the second buffer circuit 4-1 by the switching circuits 5-1 to 5-n, and the information of the first buffer circuit 4-0 is input to the second buffer circuit 4-1. The buffer circuits 4-0 to 4-n are all connected in cascade, and the information input to the input terminal 7-0 goes around the peripheral buffer section 2 of the integrated circuit 1 and is output to the output terminal 7-n. . Therefore, the high/low level logic amplitude characteristics of the output terminal provided in the peripheral buffer section 2 can be measured without inputting a functional test pattern to the internal logic circuit section 3.

Further, the information inputted to the input terminal 7-0 goes around the peripheral part 2 of the integrated circuit 1 and then passes through the output terminal ? -n, the AC characteristics can be obtained by measuring the delay time from the output terminal 7-0 to the output terminal 7-n, and all buffer circuits 4-0 to 4-n of the integrated circuit 1. Since the delay time of n is measured, manufacturing variations within the integrated circuit 1 can also be measured. Furthermore, when the switching signal is not input, information is input from each input terminal to the internal logic circuit section 3, and the output of the internal logic circuit section 3 is output to the output terminal.

〔Effect of the invention〕

As explained above, the present invention enables peripheral buffer sections of integrated circuits to be temporarily connected in cascade, thereby providing information for measuring the DC and AC characteristics of complex and highly integrated circuits. This has the effect of making it easy to input simply by adding one terminal.

[Brief explanation of the drawing]

The figure is a circuit connection diagram showing the configuration of a circuit according to an embodiment of the present invention. l... integrated circuit, 2... peripheral buffer section, 3...
Internal logic circuit section, 4.8... Buffer circuit, 5...
Switching circuit, 7...input terminal (output terminal), 10...
Switching signal input terminal.

Claims (1)

[Claims] (1) A plurality of sets of input terminals and output terminals, an internal logic circuit, and a plurality of buffer circuits inserted for each set on the path between the input terminals and output terminals and the logic circuit. An integrated circuit comprising: a switching means for temporarily switching the plurality of buffer circuits to a cascade connection state.