JPS6262557A - Semiconductor device - Google Patents

Abstract

PURPOSE:To readily electrically insulate between an n-type emitter and a p-type base by selectively implanting life time killer such as gold or platinum directly under the center of a segment to shorten the carrier lifetime directly under the center of the segment, and alleviating the current concentration at turning OFF time. CONSTITUTION:A window 12 of an oxide film is opened by photoetching an oxide film at the center of a rectangular n-type emitter 4, and life time killer such as gold or platinum is thermally diffused in high density through the window 12. In order to implant tthe killer from a p-type emitter 7 side, the oxide film of the emitter 7 is removed, and the gold or platinum is again implanted to optimize the turning OFF time or tail current of a GTO thyristor. The second implanting amount is sufficiently reduced as compared with the first implanting amount from the emitter 4 side. The lives of carriers are largely differentiated between the region 12 directly under the center of a rectangular cathode electrode and a region except the region 12 by differentiating the first and second killer implanting amounts.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to semiconductor devices, particularly semiconductor devices having the ability to cut off current, such as gate turn-off thyristors (hereinafter abbreviated as GTO thyristors), static induction thyristors, and transistors. Regarding the manufacturing method.

[Prior art and its problems]

This type of semiconductor device is required to increase the cut-off current and the allowable operating voltage during cut-off. When considering a rectangular cathode electrode (hereinafter abbreviated as segment), the current density in the constant conduction state of the GTO thyristor is uniform over the entire segment. When a negative voltage is applied to the gate to turn it off, the current disappears from the end of the segment near the gate electrode, and the current is concentrated in a narrow area in the center of the segment. If this current concentration becomes extremely large, the GTO Cyrisk will be thermally destroyed. The degree of current concentration at the center of the segment determines the magnitude of the cutoff current and allowable operating voltage. In order to reduce this current concentration, the region immediately below the center of the segment can be made inactive as a GTO thyristor.

A conventional method of inactivating the operation of the area below the central portion of the seventh segment will be explained using sectional views of the segment shown in FIGS. 2, 3, and 4.

In Fig. 2, the P base region 5 is exposed at the center of the segment, dividing the N emitter 4 into two to reduce the concentration of current. There is a drawback that the isolation is only elegant.

In Figure 3, the lateral resistance is increased by reducing the thickness of the n-emitter layer 4 at the center of the segment, and an anode sheet hole 9 is formed at the position opposite to the position of this n-emitter recess. decrease concentration. In this method, n
Difficulty arises in aligning the emitter recess and the anode short hole 9.

In FIG. 4, the impurity concentration of lO in a part of the P base region 5 directly under the center of the segment is increased, and the P base region 5 in that part 10 is further increased.
By making the base layer thicker than other parts,
This method reduces current concentration at the center of the segment.

In this method, a high concentration impurity region 10 is provided in the P base region 5.
In order to make a profit, the number of diffusion steps is increased and the diffusion is performed at high temperatures and for a long time, which is disadvantageous in terms of thermal distortion of the semiconductor substrate, especially in the manufacture of large-diameter devices.

[Purpose of the invention]

The present invention alleviates current concentration during turn-off at the center of a segment, which is a basic component, in a semiconductor device having a self-extinguishing function such as a GTO thyristor, and provides electrical insulation between an n emitter and a pE3. Since there is no recess in the n emitter, it has good thermal contact with the cathode contact electrode plate (ζ).It also reduces the occurrence of thermal strain on the semiconductor substrate and improves the tolerance during cut-off, flow and turn-off. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can increase the operating voltage.

[Key points of the invention]

The present invention shortens the carrier life directly under the center of the segment by selectively injecting a lifetime killer such as gold or platinum directly under the center of the segment, or by irradiating radiation such as electron beams or gamma rays. <L/, h npn composed of emitter, n base, n base) current amplification factor α of each pnp transistor part and pnp I” transistor part composed of n base, n base, n emitter
and αpnppn are both made small, and the area directly under the center of the segment is set to GT.
By using an inactive thyristor as an O thyristor, it is intended to eliminate current concentration at the center of the segment during turn-off.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention, in which after thermally diffusing n-type impurities on both sides of a high-resistance n-type half-4K substrate 6 to a predetermined 11 degrees and depth ζ, one p-type Further, ln-type impurities are thermally diffused into the conductive region 5 to a predetermined concentration and depth. Thereafter, a photo-etching process is performed to form a rectangular cathode 4, an anode cap, a gate'! ! n-emitter 7, n-base 5. to which the pole and cathode electrodes are respectively attached. An oxide film 11 is temporarily formed on the n emitter 4 by thermal oxidation. By photo-etching the oxide film at the center of the rectangular n emitter 4, it is shaped into a shape similar to that of the rectangular n emitter 4 or rectangular, as shown in the plan view of the rectangular!1 emitter shown in Figure 6@1 (01). Open the oxide film window 12.

After such pre-processing, the window 12 here as shown in FIG.
High concentration of lifetime killers such as gold and platinum through
This heat spreads. At this time, the arsenic acid film 11 acts to prevent the diffusion of gold and platinum into the semiconductor substrate, so that gold and platinum are diffused into the semiconductor substrate only from the window of the n emitter 4 from which the oxide film is removed. .

After injecting a lifetime killer with a high degree of a degree from the n emitter side 4, the lifetime killer is also injected from the n emitter 7 side, so the oxide film 3 on the n emitter 7 side is removed, and the turn-off time and Tilmi flow of the GTO thyristor are adjusted. Gold or platinum is injected again to achieve the optimum value. This second injection amount of lifetime killer is made sufficiently smaller than the first injection amount from the n emitter side 4. Otherwise, the on-voltage will become abnormally high. In this way, by changing the injection amount of Lifetime Killer for the first and second injections, the area 1 directly under the center of the rectangular cathode
There is a large difference in carrier life between 2 and other areas.

The second lifetime killer injection may not be performed. Alternatively, if the n emitter 7 is additionally diffused with impurities such as phosphorus atoms in order to have a strong getter effect on gold, platinum, etc. in advance, it is possible to A purposeful lifetime killer can be injected simultaneously from the side 4 and the anode fl187, and the same effect as the double lifetime killer press-in of the first and two 8g injections described above can be obtained.

FIG. 5 is one of the different implementations of the invention.

Here, a radiation diverter 13 such as a single-ray or gamma ray is irradiated into the center of the segment to generate a high concentration defect area 15 directly under the center of the segment, thereby increasing the carrier lifespan compared to other areas that are not irradiated. Hide.

At this time, radiation shielding plate 14 prevents radiation from hitting areas other than the center of the segment. In the case of radiation irradiation, since the radiation transmittance is high, there may be a single oxide film 11 on the entire surface of the n emitter. Radiation used: FM
7; '1 and its energy have at least a range of n
It must be chosen to range from pace 5 to n base 6 or more. In this way, the area directly below the center of the segment can be made inactive as a GTO cyrisk.

FIG. 6 shows an embodiment of the lifetime killer injection region 12 and the radiation irradiation region 15 in the center of the segment according to the present invention. The GTO Sairisk operation inactive area has a similar shape to the segment or a rectangle, and its width is 50μ.
m or more.

FIG. 8 shows the concentration distribution in the depth direction along lines AA and B-B of the lifetime killer injection region 12 according to the present invention shown in FIG. 7. Depth on horizontal axis.

From FIG. 8, which shows the concentration distribution on the vertical axis, it can be seen that in the n-pace 5 and n-base regions 6, there is a large difference in the concentration of the lifetime killer between just below the center of the segment and at its periphery.

〔Effect of the invention〕

According to the present invention, by injecting a lifetime killer such as gold or platinum into the center of the segment at a high concentration and irradiating it with radiation, the life of the carrier directly under the center of the segment can be significantly shortened compared to that at the periphery of the segment. , it is possible to eliminate the concentration of current in the center of the segment during turn-off, and it is possible to increase the cutoff current and allowable operating voltage of the GTO Cyrisk. Moreover, there is no need to make the segments into a special shape, and electrical insulation between the n-emitter and the n-pace and thermal contact between the n-emitter and the cathode contact plate can be facilitated. Furthermore, the lifetime killer thermal diffusion can be performed at a relatively low temperature and in a short time, compared to the thermal diffusion used to create a special impurity diffusion profile to reduce current concentration. It is suitable for making high-quality semiconductor devices because it generates little thermal distortion. Furthermore, the introduction of defects directly below the center of the segment by radiation irradiation is superior to conventional manufacturing methods both from the perspective of thermal strain generation and from the perspective of controlling the depth of defect introduction.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a gate turn-off thyristor for explaining the manufacturing method of the present invention, and FIGS. 2, 3, and 4 are cross-sectional views including segment parts for explaining the conventional manufacturing method, respectively. FIG. 5 is a sectional view including a segment portion for explaining a different manufacturing method of the present invention, and FIG. 6 is a plan view of a segment portion for explaining a manufacturing method of the present invention.
FIG. 7 is a sectional view showing the lifetime killer injection region for explaining the manufacturing method of the present invention, and FIG. 8 is a diagram showing the relationship between degree and depth of the injection lifetime killer according to the present invention. . l... cathode electrode, 2... gate electrode, 3...
Anode electrode, 4...n emitter, 5...p base, 6...n base, 7...p emitter, 8...insulating film, 9...anode short hole, 10... High concentration p base region, 11... Oxide film, 12... Lifetime killer high implantation region, 13... Radiation, 14...
Shielding plate, 15...High concentration defect generation area. tf ;P1 Figure S figure 'f'4 (8) Sairi ward cathode V unseeing η゛rafei S (potato view ψ i anus) - Sai6 (
2)

Claims (1)

[Claims] The four stacked layers of the semiconductor substrate have different conductivity types, with a base layer on the inside and an emitter layer on the outside.
On one side, the first emitter region has a plurality of rectangular shapes each surrounded by a base region,
A semiconductor device characterized in that a lifetime killer concentration in each of the layer regions immediately below a central portion of a cathode electrode provided on a first emitter region is greater than a lifetime killer concentration immediately below a peripheral portion of the electrode.