JPS6262476A - Digital signal processor - Google Patents

Abstract

PURPOSE:To correctly fetch the reproducing digital data by a circuit of one system even when optionally changing a reproducing transmission speed of the digital data by providing a clock generator, a clock reproducing means, a switch means, and a means for detecting and correcting an error included in the digital data. CONSTITUTION:A switch 6 is a switch changed over by a data transmission speed. An equalizer circuit 24 and a signal processing circuit 28 have to be changed over and controlled in accordance with the data transmission speed by the switch 6 similarly to a data strobe circuit 26. The reason is that the signal processing circuit 28 is proportional to the change of the data transmission speed and required to enhance a processing speed such as correcting an error. A clock generator 27 can correctly fetch the data reproduced in magnetic heads 30A, 30B and magnetic heads 32A, 32B by changing over the switch 6, in spite of generating a clock of the same period.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Application of the Invention) The present invention relates to a digital signal reproducing device such as a rotary head type magnetic recording/reproducing device, and particularly to a digital signal processing device suitable for a system that varies transmission speed.

(Background of the Invention) Players using compact discs (CDs) are currently popular in consumer electronics as devices for recording and reproducing digital signals and obtaining high-quality music reproduction signals. In this system, irregularities called pits are carved on the disk, and the disk is rotated and optical pickup is used to detect the pits and reproduce the digital signal.This reproduced digital signal is subjected to error correction processing, etc. , in addition to the digital-to-analog converter C DAC ).

It reproduces music signals.

In order for the CD player to correctly reproduce music signals, K controls the disc so that it rotates at a predetermined speed based on a fixed frequency, and also reproduces a clock synchronized with the digital signal reproduced from the disc. A signal processing circuit is required that takes in data using a clock, performs correction processing, etc., and outputs data at a sampling frequency based on a fixed frequency.

A conventional signal processing circuit of this kind is disclosed in Japanese Patent Application Laid-Open No. 58-219.
As shown in Japanese Patent Publication No. 852 and Japanese Patent Application Laid-Open No. 59-124012, signal processing such as disk rotation control and data output is based on the frequency of one crystal oscillator, and A clock synchronized with data is generated by a PLL circuit.

A rotary head type magnetic recording/reproducing device also reproduces data using a signal processing circuit similar to that of the CD player. However, in the case of a rotating head type magnetic recording and reproducing device, in order to obtain the desired data, recording and reproducing are performed by changing the angle at which the tape is wound around a rotating cylinder. It needs to be shortened proportionately. For this reason, the transmission speed during playback changes arbitrarily depending on the tape winding angle, and a data acquisition circuit corresponding to this is required.

Therefore, in the past, dedicated data acquisition circuits were provided for tape winding according to the corners, and there was a problem in that a large number of different types of circuit components were required.

Furthermore, this has caused a problem in that the cost of the rotary head type magnetic recording and reproducing apparatus increases.

(Object of the Invention) In view of the above-mentioned prior art, an object of the present invention is to provide a rotary head type magnetic recording brass reproducing apparatus, and even when the tape winding angle is changed, the data can be processed by a single digital signal processing circuit. K provides a digital signal processing device that can incorporate

(Summary of the Invention*) A feature of the present invention is that a single system of digital signal processing circuits can adjust the reproduction data transmission speed based on a basic clock of a predetermined period output from one or more clock generators. The point is that a reproduction clock for data acquisition is created according to the requirements, and reproduction digital data can be acquired even if the reproduction transmission speed of the digital data is changed.

(Embodiment of the Invention) First, with reference to FIGS. 5 and 6, a reproduction signal trap when the same recording pattern recorded on a tape is reproduced using magnetic heads mounted on cylinders with different diameters will be explained. do.

In the figure, 35 is a cylinder with a diameter of a, and 36 is a cylinder with a diameter of a.
For a cylinder with a diameter of 2a, 30 A + 30 B I
32A*32B is a rotary head, and 31 is a magnetic tape. Further, 33 is a cylinder 35, a head 30A
.

The signal waveform reproduced at 30B, 34 is the cylinder 36,
This is a signal waveform reproduced by heads 32A and 32B.

In FIG. 5, since the angle at which the tape 31 is wrapped around the cylinder 35 is 90 degrees, the reproduced signal waveform 33 becomes a burst-like waveform, and the parts with and without the reproduced signal are at the same time. Become.

Next, in order to reproduce a tape with the same recording pattern using a magnetic head mounted on a cylinder 36 with a diameter of 2, the wrap angle of the tape 31 is 45 degrees, and the rotational speed of the cylinder 36 is 45 degrees. It needs to be the same as that of 35. If playback is performed under these conditions, the playback signal 34
In this case, a certain portion of the signal remains at 174 of the total, and the data transmission speed is twice that of the reproduced signal 33.

Next VC, As mentioned above, it is possible to take in reproduced data with different data transmission speeds reproduced by different magnetic heads with one system of digital signal processing circuit.In other words, it is possible to correctly demodulate. The digital signal processing device of the rotary head type magnetic recording/reproducing apparatus according to this embodiment will be explained with reference to FIG. 1st
The figure shows a circuit block diagram of a digital signal processing device.

In the figure, 23 is a preamplifier that amplifies the reproduced signal;
4 is an equalizer circuit for eliminating code amount interference caused by deviation in frequency characteristics of a reproduced signal received on a transmission path of a recording medium, etc., and 25 is an equalizer circuit for eliminating code amount interference caused by deviation in frequency characteristics of a reproduced signal received on a transmission path of a recording medium, etc.;
26 is a data strobe circuit which will be described in detail later in FIG. 2, 27 is a clock generator, 28 is a signal processing circuit that performs processing such as data error detection and correction, and 29 is a correction circuit. This is an output terminal to which processed data is output.

The switch 6 is a switch that is switched based on the data transmission speed fK, as will be made clear in the explanation of FIGS. 2 and 3. The equalizer circuit 24 and the signal processing circuit 28, like the data strobe circuit 26, need to be switched and controlled by the switch 6 according to the data transmission speed. The reason for this is that the signal processing circuit 28 needs to increase the processing speed of error correction etc. in proportion to the change in the data transmission speed, and the equalizer circuit 24 needs to increase the processing speed of error correction etc. in proportion to the change in the data transmission speed. This is because the frequency characteristics to be equalized change. Therefore, it is necessary to switch according to each data transmission rate so as to obtain the optimum frequency characteristics.

According to the circuit shown in FIG. 1, although the clock generator 27 generates clocks with the same period, the magnetic heads 30A and 30B are not affected by switching the switch 6.
(see FIG. 5) and magnetic heads 32A, 32B (sixth
(see figure) can correctly import the data played back.

The reason for this will be made clear by explaining the configuration and operation of the data strobe circuit in detail below.

FIG. 2 shows a data strobe circuit 26 (first
FIG. 2 is a block diagram illustrating a specific example of FIG.

FIG. 2 shows a block diagram of a clock regeneration circuit for data acquisition of a signal processing circuit that supports a regeneration trap n/m times that during normal reproduction.

As shown in the figure, the reproduced data output from the humpator 25 is applied to the input terminal IK.

Further, a clock having a frequency (n-fTr) that is n times higher than the normal data transmission speed IBi fTrK is outputted from the clock generator 27 and applied to the input terminal 3.

The reproduced data applied to the input terminal 1 is supplied to an edge detection circuit 2 that detects at least one edge of the input signal, and its output is applied to the clear 1 child of a switchable counter 4 in m-adjustment mode. . The output of the edge detection circuit 2 and the output of the counter 4 are input to an AND circuit 5, and the output thereof is applied to a clear terminal of an n-ary m-ary switchable counter 7. The output of the counter 7 is applied to a clock input terminal of a D flip-flop 8. The D7 rig 70 tube 8 takes in reproduced data using the clock and outputs it from the output terminal 9. Data after data capture and a reproduced clock are output to output terminals 9 and 10.

Note that the edge detection circuit 2. The counters 4 and 7 are operated by a clock (n-fTr) applied to the input terminal 3. Further, the switch 6 applies high-level and low-level potentials to the counters 4 and 7, and controls the counters so that when the high level is high, it is n-adary and when the low level is m-adic.

Next, a specific circuit example of the counter 4 in this circuit will be explained with reference to FIG. In Figure 3, the CLR of terminal 11 is.

The C of the skin 12 is connected to the OUT of the edge detection circuit 2 in Fig. 2.
LK is connected to CLK of input terminal 3 in FIG.
/ m is the OUT of terminal 22 at switch 6 in Figure 2.
It is connected to the AND circuit 5 shown in the figure.

The circuit configuration is 74L of NOR circuit 13, AND circuits 15 to 18, inverter 20, OR circuit 19, and general-purpose TTL.
It consists of a counter 14 that performs the same operation as S163. The output of the counter 14 is QAI QB from the least significant digit.
I QCI QD , and the circuit of FIG. 3 is -
As an example, a counter that can be switched between octal and quaternary systems is configured.

In this circuit, an AND circuit 17 performs decoding to make a quaternary counter, and an AND circuit 16 decodes it into an octal counter. , performs quaternary switching.

That is, when a voltage of KV is applied to the terminal 21 , the C-AND circuit 15 is opened, the C-AND circuit 18 is closed, and an octal output is outputted from the terminal 22 through the OR circuit 19 . Further, this octal output is input to the NOR circuit 13, and the NOR circuit 1
The counter 14 is cleared by the output of 3.

On the other hand, when the ground voltage is applied to the terminal 21, the AND circuit 18 is opened, the AND circuit 15 is closed, and a quaternary output is output from the terminal 22.

With these configurations, it is possible to switch any n-ary m-ary counter by changing the decoded values of the AND circuits 16 and 17.6 Next, the operation of the embodiment shown in FIG. This will be explained with reference to FIGS. 3 and 4. In Fig. 4, Fig. 1a) shows a timing diagram at the normal data transmission speed IJf f, r, and Fig. 4(b) shows a timing diagram at the transmission speed lf2/fTr, which is twice the normal data transmission speed. show.

First, the operation when reproducing data is taken in at the normal data transmission speed will be described (corresponding to when reproducing with the magnetic head shown in FIG. 5).

A clock having a frequency of 8·'Tr is applied to the terminal 3 in FIG. Also, for counters 4 and 7.

Since the switch 6 applies a high level voltage V to the n/mC terminal, the counter 4.7 operates as an octal counter.

As a result, as shown in FIG. 4(a), the counter 4 is cleared by the data edge detection signal and performs an octal counting operation. As a result, pulses are generated at the output of the counter 4 at a period of data transmission speed f, a in synchronization with the edge detection signal.

By creating an AND between this output and the output of the edge detection circuit 2 in the AND circuit 5, the output pressure of the AND circuit 5 is determined by the time from edge to edge of the data at the data transmission rate f
Only edges that match an integral multiple of the period of the Tr are output. As a result, it is possible to remove erroneous edges such as edges erroneously generated in the data, and obtain correct phase information of the data.

By clearing the counter 7 with the output of the AND circuit 5 and performing an octal counting operation, the output of the counter 7 becomes CLOCKOut as shown in FIG. 3(a), and data can be correctly captured at the rising edge. .

Next, the transmission stray current 2.f is twice as high as the normal data transmission speed.
The operation when reproducing data is taken in by the Tr (corresponds to when reproducing data by the magnetic head shown in FIG. 6) will be explained. Second
Terminal 3 in the figure has 1 8.'T as in the case of normal data transmission speed.
A clock of r frequency is applied. On the other hand, counter 4,
A low level is applied to the n/m terminal of 7 by switch 6, and a quaternary counter operates.

As a result, as shown in FIG. 4(b), the counter 4 is
It is cleared by the data edge detection signal, performs a quaternary output counting operation, and the output of the counter 4 is.

Data transmission rate 2 fT in synchronization with edge detection signal.

A pulse is generated with a period of .

By creating an AND between this output and the output of the edge detection circuit 2 in the AND circuit 5, the output of the AND circuit 5 can obtain correct data phase information as in the case of the normal data transmission speed.

This pulse clears the counter 7 and performs a quaternary output counting operation.As a result, the CLOCK Out signal shown in Figure 4 (bl) is obtained as the output of the counter 7, and the data can be correctly captured at the rising edge of the counter 7. can.

As is clear from the explanation of the circuit operation shown in FIGS. 2 and 3, the circuit of this embodiment uses a clock for data acquisition that supports variable data transmission speed without changing the frequency applied to the clock input terminal 3. It can be a regeneration circuit (ie, a data strobe circuit).

Next, a second embodiment of the present invention will be described using FIG. 7. This embodiment shows a digital signal processing device in which the clock generator can be further switched in the first embodiment shown in FIG. is a switch that changes the output. As a result, in the embodiment shown in FIG. 4, the data transmission rate could only take a value that is a multiple of two integral numbers, as indicated by n/m times, but by selecting the frequencies of the clock generators 27A and 27B, the data transmission rate can be changed to an integral number. It can be made to support any data transmission speed other than double.

A specific application example of this second embodiment will be described below.

FIG. 8 shows a tape being wound and brought into contact with a video tape specification cylinder of a rotary head type magnetic recording/reproducing device, where the diameter of the cylinder 100 + 162t1.
The width of the magnetic tape 101 is 1λ7n, and the angle A of the tape winding is 1800. Also, FIG. 9 shows the cylinder 100K shown in FIG. 8, the tape 102 having a width of 3.8 m, and the tape wrapping angle B at 43.55 degrees.

FIG. 10 shows an application example of the second embodiment for recording and reproducing data in the same recording format on different tapes shown in FIGS. 8 and 9.

In FIG. 10, 103 is a recording system signal processing circuit. The signal processing circuit 103 adds an error correction code and a synchronization signal to the digital signal applied to the input terminal 104, modulates it, and sends it to the recording amplifier 105. It's something to add. or,
106 and 107 are crystal oscillators, and this crystal oscillator 10 serves as the basic clock of the recording system signal processing circuit 103.
6 and 10 are switched by a switch 108 and supplied to a recording system signal processing circuit 103. The output of the recording amplifier 105 transmits signals to the rotary heads IQQA, 109B to record the signals on the tape.

During playback, signals are taken out from the heads 109A and 109B, and the taken out signals are applied to the preamplifier 23, and a circuit pressure similar to that shown in FIG. 7 is applied hereafter.

To explain the circuit operation of FIG. 10 in detail, first, in order to record and reproduce the tape shown in FIG. As a clock, the switch 108 is selected to A (II), and the crystal oscillator 106 is connected to the recording system signal processing circuit 103.
Connect to. The crystal oscillator 106 has a transmission rate 'Tr
It has an oscillation frequency of

During playback, the switch 6 controls the data strobe circuit 26 to function as a hexadecimal counter. Further, the switch 31 selects the oscillator 27A. The oscillation frequency of the oscillator 27A is 16·fTr. From this, the data strobe circuit can sample and capture data at a frequency 16 times the transmission speed.

On the other hand, I am busy recording and playing back the tape shown in Figure 9 in the same recording format as in Figure 8.

Since the winding around the cylinder has different angles, the transmission speed is reduced by 1.
It is necessary to multiply by 800743.55° - 4.13 times.

Therefore, the oscillation frequency of the crystal oscillator 107 is used as the basic clock of the recording system signal processing circuit 103.
413 times, and the switch 108 is set to Bl
Select gll. Thereby, a signal with a transmission speed of 4.13°'Tr can be sent to the head amplifier 105 and recorded on the tape.

Further, during reproduction, a reproduction signal having a transmission rate of 4.13 fT is applied to the preamplifier 23. On the other hand, the data strobe circuit 26 is controlled by the switch 6 so that it becomes a quaternary counter. Also, the switch 37 has an oscillation frequency of 16.52f.
Select the oscillator 27B of T.

This allows the data strobe circuit to sample and capture data at a frequency four times higher than the transmission rate of nine.

Therefore, in the embodiment of FIG. 10, the transmission rate is 4.
Even if it is multiplied by 13, the clock frequency of the reproduction system is still 16.
52 fT, /16 fT, = 1.03 times, without increasing the operating speed of the reproduction system signal processing circuit.

realizable.

As described above, according to the digital signal processing circuit of this embodiment, tape winding can be played back by changing the angle using magnetic heads mounted on cylinders with different diameters or magnetic heads mounted on cylinders with the same diameter. However, data can be correctly captured using a single digital signal processing circuit.

Therefore, there is no need to provide separate digital signal processing circuits for each corner when winding the tape (this makes it possible to reduce the cost of the one-rotation head type magnetic recording/reproducing apparatus).

(Effects of the Invention) According to the present invention, in a one-rotation head type magnetic recording/reproducing device, the tape winding around the cylinder has different angles, and even when the reproduction transmission speed is varied, a single system digital signal processing device can be used. This has the advantage that data can be correctly captured in the reproducing signal processing circuit, and even if the transmission number increases, it can be realized without increasing the operating speed of the circuit.

[Brief explanation of the drawings] Figure 1 is a block diagram of an embodiment of the present invention. Figure 2 is a block diagram of an embodiment of the present invention.
3 is a block diagram showing a specific example of the data strobe circuit shown in FIG. 2, FIG. 3 is a block diagram showing a specific example of the n-ary m-ary counter shown in FIG. The time charts, Figures 5 and 6 are waveform diagrams of signals when a tape with the same recording pattern is reproduced by magnetic heads mounted on cylinders of different diameters in a rotating head type magnetic recording/reproducing device. 8 and 9 are block diagrams of other embodiments of the present invention, and FIGS. 8 and 9 show the relationship between the cylinder and the tape winding corner of a rotary head magnetic recording/reproducing apparatus to which the embodiment of FIG. 7 can be applied. FIG. 10 is a block diagram of an apparatus for recording and reproducing data in the same recording format on different tapes shown in FIGS. 8 and 9. 2... Edge detection circuit, 4, 7... 1st. Second counter, 6.37...Switch, 8...D flip 70 knob, 24...Equalizer, 25
...Comparator, 26...Data strobe, 27.27A, 27B...Clock generator,
28...Signal processing circuit

Claims (4)

[Claims] (1) A clock generator that outputs a basic clock with a predetermined period, a clock regeneration means that regenerates a clock for data acquisition according to a reproduction data transmission speed, and a period of the regenerated clock that corresponds to the reproduction data transmission speed. The clock reproducing means is equipped with a switch means for instructing the clock reproducing means to change according to the clock reproducing means, and a means for detecting and correcting errors included in the digital data, so that even if the reproducing transmission speed of the digital data is arbitrarily changed, the clock reproducing means can be changed in accordance with the clock reproducing means. A digital signal processing device characterized in that reproduced digital data can be taken in by the circuit. (2) The scope of the above claims, characterized in that the clock generator is composed of two or more clock generators that generate clock signals with similar periods, and can be switched and used depending on the reproduction transmission speed. 2. The digital signal processing device according to item 1. (3) an edge detection circuit in which the clock recovery means detects at least one edge of the reproduced digital data;
a first counter that is cleared by the output of the edge detection circuit, divides the basic clock signal by a selected frequency division ratio and outputs the result; and extracts a counter output that matches the edge from the first counter output. means, a second counter that is cleared by the counter output taken out by the means, divides the basic clock signal by a selected frequency division ratio and outputs the result; and captures the output signal of the second counter as data. a clock output terminal for outputting a digital clock; and means for capturing the reproduced digital data using the data capture clock, and the switch means controls the first and second counters in accordance with the transmission speed of the reproduced digital data. 3. The digital signal processing device according to claim 1, wherein a frequency division ratio is selected. (4) The digital signal according to any one of claims 1 to 3, wherein the reproduction transmission speed of the reproduced digital data changes depending on the winding angle of the tape around the cylinder. Processing equipment.