JPS6261167B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a differential input type tuned amplifier using transistors. It is a tuned amplifier particularly suitable for monolithic integrated circuits.

[Conventional technology]

FIG. 1 is a circuit diagram of a conventional differential input type tuned amplifier. IN ₁ and IN ₂ are differential input terminals, and OUT ₁ is an output terminal. V _c is the collector power supply voltage terminal,
V _b is a base power supply voltage terminal, and V _e is an emitter power supply voltage terminal. Tr ₁ , Tr ₂ , Tr ₃ are transistors,
R _c1 and R _c2 are collector resistances, R _e is emitter resistance,
C ₁ is the capacitance of the resonant circuit, and L ₁ is the inductance of the resonant circuit.

By connecting a parallel LC resonant circuit in parallel to the collector resistor R _c2 of the differential amplifier circuit as shown in FIG. 1, a voltage gain tuning characteristic as shown in FIG. 2 can be obtained. However, this circuit included an inductance _L1 , making it difficult to integrate the tuned amplifier into a monolithic integrated circuit. For this reason, in conventional tuned amplifiers, only the differential amplifier circuit is integrated into a monolithic circuit, and the LC resonant circuit is configured externally, making it difficult to downsize.

For this reason, a tuned amplifier technology has been proposed in which a capacitive element and a resistor are connected between the emitter electrodes of a differential amplifier circuit to form a feedback circuit and compensate for the gain in the high frequency range (Japanese Patent Application Laid-Open No. 1983-1993-1). Publication No. 61814, Jitsukaiaki
57-19614). In addition, in order to provide a differential amplifier with stable bandpass characteristics, a technology has been proposed in which distributed constant circuits with equal length and 1/4 wavelength resonance characteristics are connected to the emitter electrodes of the differential amplifier ( (Japanese Unexamined Patent Publication No. 1982-19213).

[Problem that the invention seeks to solve]

However, although these technologies can obtain flat gain characteristics over a wide band, they have not been able to realize sharp tuning characteristics, that is, high-Q tuned amplifiers. was required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a differential input type tuning amplifier that does not include inductance, is suitable for integration into an integrated circuit, and has sharp tuning characteristics.

[Means for solving problems]

The present invention connects a resistor between both emitters of a pair of transistors constituting a differential amplifier circuit and a constant current circuit, further connects a capacitor and a delay line in series between both emitters, and connects the capacitor and delay line in series. The amount of negative feedback is set so that the gain becomes large at the peaking frequency determined by the resistance, and the gain becomes small in the low frequency range.
It is characterized by increasing the resonance Q using a delay line and sharpening the tuning point.

〔Example〕

FIG. 3 is a block diagram of a circuit according to an embodiment of the present invention. Differential input terminals IN ₁ and IN ₂ are connected to a pair of transistors
It is connected to the bases of Tr ₁ and Tr ₂ , respectively, and the output terminals OUT ₁ and OUT ₂ are connected to their collectors.
The emitters of both transistors Tr ₁ and Tr ₂ are connected to the collector of transistor Tr ₃ via resistors R ₁ and R ₂ , respectively. The base of this transistor _Tr3 is connected to the base power supply voltage terminal _Vb , and its emitter is connected to the emitter power supply voltage terminal Ve through a resistor _{Re .}
By connecting it to, it acts as a constant current circuit.

The feature of the present invention is that a series circuit of a capacitor C and a delay line DL is connected between each emitter of a pair of transistors Tr ₁ and Tr ₂ . With this configuration, this emitter circuit acts as a so-called peaking circuit.

A further feature of the present invention is that the gain is high at the peaking frequency determined by this peaking circuit, and the amount of negative feedback is sufficiently increased in the low frequency range to set the gain to be small, and the delay line DL By increasing the amount of delay, the resonance Q becomes high and the tuning point becomes sharp.

The delay line DL is formed by a conductor connected to a common potential point, a thin insulating layer formed on the conductor, and a strip-shaped conductor formed on the insulating layer. It is well known that the characteristic impedance is determined by the width of this strip-shaped conductor and the thickness and dielectric constant of the insulating layer, and the amount of delay is determined by the length of this strip-shaped conductor. The above example has a characteristic impedance of about 50Ω and a length of 10 mm.

A wide-pass peaking circuit is connected between both emitters, and the resistances R ₁ and R ₂ of the peaking circuit are made larger than the collector resistances R _c1 and R _c2 so that the gain is less than zero in the low frequency band. In this case, the capacitor C is used to set the impedance of the peaking circuit to be smaller than the collector resistances R _c1 and R _c2 . As a result, a wide-pass type voltage gain characteristic is realized, and by using the wide-band cutoff characteristic of the transistor itself and the delay characteristic of the delay line, it is possible to realize the tuning characteristic shown in Fig. 4. can.

FIG. 4 shows the voltage gain characteristics when the delay amount of the delay line DL is changed when the value of the capacitance C of the peaking circuit is 4 pF. Gτ ₀ ,Gτ
₁ and Gτ ₂ are the delay amount τ of 0, 50, and 100, respectively.
(psec), and by using a delay line in the peaking circuit, the maximum voltage gain and Q can be further increased.

FIG. 5 is a circuit diagram of a tuned amplifier in which two stages of the differential amplifier circuits of FIG. 3 are connected in cascade.

By using the circuit configuration shown in FIG. 3 in which two stages of differential amplifier circuits are connected in series, the maximum voltage gain and the maximum voltage gain frequency can be further increased compared to the case of a one-stage differential amplifier circuit.

〔Effect of the invention〕

As explained above, the circuit of the present invention can be monolithically integrated, and a tuned amplifier with a large maximum voltage gain and high Q can be realized in a high frequency band.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional differential input type tuned amplifier. FIG. 2 is a diagram showing an example of voltage gain characteristics of the circuit. FIG. 3 is a circuit diagram of a tuned amplifier according to an embodiment of the present invention.
FIG. 4 is a diagram showing an example of voltage gain characteristics of the embodiment circuit.
FIG. 5 is a circuit diagram of another embodiment of a tuned amplifier according to the present invention.

Claims (1)

[Claims] 1: a pair of differential input terminals IN ₁ and IN ₂ ; a pair of transistors Tr ₁ and Tr ₂ whose bases are connected to the input terminals; a constant current circuit; Resistors R ₁ and R ₂ connected between each emitter of the transistor and this constant current circuit, and a series circuit of a capacitor C and a delay line DL connected between each emitter of this pair of transistors, A tuned amplifier comprising a negative feedback circuit having a negative feedback amount set such that the gain is small in a low frequency range and becomes large at a peaking frequency determined by the capacitor, the resistor, and the delay line.