JPS6261165B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for initially adjusting mass production variations in peak temperature of a crystal resonator whose temperature characteristics are approximately given by a quadratic curve.

First, the background and purpose of the present invention will be described.
A tuning fork type crystal resonator used in an oscillation circuit such as a crystal oscillation type watch has an oscillation frequency versus temperature characteristic approximately given by a quadratic curve as shown by the solid line in FIG. 1a. In the figure, θ ₀ represents the temperature corresponding to the apex of the parabola. (Hereinafter, θ ₀ will be referred to as the peak temperature.)
FIG. 2 is a block diagram of a temperature detection section when a temperature sensor is provided in a timepiece integrated circuit to correct the temperature characteristics shown by the solid line in FIG. 1. At the same time, 201
202 is a temperature sensor, 202 is a comparator, 203 is a counter and decoder, and 204 is a reference voltage generation circuit that provides a reference potential for converting the analog temperature signal obtained in 201 into a digital value. The function of the temperature detection section in the figure is to sequentially change the level of the signal 213 by sweeping the signal 203, and by detecting the inversion of the signal 212, stop the sweep of the signal 203 and convert the analog temperature signal 211 into a digital signal 214. It is about converting. When the temperature detection circuit shown in FIG. 2 is used to adjust the rate of a clock, the frequency dividing circuit is logically adjusted in accordance with the digital signal 214. At this time, if the temperature characteristics of the crystal resonator shown in FIG. 1, particularly the peak temperature θ ₀ , deviates from the design value, a problem arises in that the rate is not adjusted accurately. The peak temperature of currently mass-produced tuning fork type crystal oscillators includes a variation of about ±4° C., which poses a major hindrance to accurate rate adjustment.

An object of the present invention is to eliminate the above-mentioned drawbacks and to suppress errors in rate heating and suddenness caused by mass production variations in peak temperature to a sufficiently small amount.

The present invention provides a peak temperature adjustment circuit in the reference voltage generation circuit 204 shown in FIG. Third
The figure shows an example of the configuration of FIG. 2 204 according to a conventional configuration. In the example in Figure 3, the number of nodes that provide the reference potential is 7.
One node is provided to provide a negative power supply potential. In the figure, 303 to 309 are integrated resistors, 311 is a positive power supply, 319 is a negative power supply, 312 to 318 are nodes that provide a reference potential, 319 are nodes that provide a negative power supply potential, and 321 to 328 are nodes that provide a negative power supply potential. These are analog switches (for example, transmission gates or transfer gates) that are sequentially set to conduct only one at a time by the sweep of the counter in FIG. 203. Further, a reference potential is supplied from the input terminal 331, and the reference potential is transmitted to the node 315 by the operation of the operational amplifier 301. On the other hand, a MOS field effect transistor (hereinafter abbreviated as MOSFET) 302 is connected to a resistor 3 so that a node 315 is at the supplied reference potential.
03 to 309.

Due to the above operation, the node 332 has 312 to 3
A reference potential corresponding to the selected node of 19 is obtained and transmitted to the input terminal of the comparator 202 in FIG. The reference potentials generated at the nodes 312 to 318 each correspond to the temperature, for example, 3
12 is 43℃, 313 is 37℃, 314 is 31℃, 31
5 is 25℃, 316 is 19℃, 317 is 13℃, 318
becomes like 7℃. When adjusting the rate of a clock, the logical adjustment is to read out the contents of a predetermined read-only memo (hereinafter abbreviated as ROM) according to the temperature signal represented by the digital value shown in FIG. 2 214. It is done by. At this time, the content of the ROM that provides the degree of speed is set, for example, in accordance with a crystal resonator whose peak temperature is 25°C. However, as mentioned earlier, the peak temperature of mass-produced crystal units has a maximum temperature of ±4℃.
Contains varying degrees of variation. Let's use Figures 1a and 1b to explain the error in rate slowing/slowing when the peak temperature deviates from the design value (setting value written in advance in the ROM). Let the design value of the peak temperature be θ ₀ .

Figure 1a relates to a crystal oscillator whose peak temperature is equal to the design value, and the dotted line shows the temperature characteristics when no logical moderation is applied, whereas the dotted line shows the temperature characteristics when logical moderation is applied. Next, the peak temperature of the crystal oscillator used is θ ₁
Assume that (θ ₁ ≠θ ₀ ). In this case, the temperature characteristics will be as shown in FIG. 1b, resulting in incorrect speed and speed being applied.

As is clear from Figure 1b, the peak temperature is θ ₁
- θ A deviation of ₀ means that the temperature sensor is θ ₁ - θ
This is equivalent to detecting the temperature incorrectly by ₀ .

Therefore, in the present invention, for a crystal resonator whose apex temperature deviates by θ ₁ - θ ₀ , the reference potential given by the circuit 204 in FIG. 2 is converted into temperature.
A fine adjustment circuit is provided that works to shift the amount by an amount corresponding to ₁ - θ ₀ . That is, in Fig. 3, the temperature setting for each node at the time of design is 312-43
℃, 313-37℃, 314-31℃, 315-25
℃, 316-19℃, 317-13℃, 318-7℃
If this is designed for a crystal resonator with a peak temperature of 25℃, the peak temperatures are 312-45℃, 313-39℃, 314-33℃,
315-27℃, 316-21℃, 317-15℃,
Fine adjustment may be made so that the temperature becomes 318-9°C.

FIG. 4 shows an embodiment of the apex temperature adjustment circuit of the present invention. The figure shows that the peak temperature of the crystal resonator is, for example, 21
This is an example of adjusting the temperature in four stages such as ℃, 23℃, 25℃, and 27℃.

The meaning of each symbol in FIG. 4 is as follows.

401...Operation amplifier 402-403...MOS field effect transistor (hereinafter abbreviated as MOSFET) 404-405...Cell for top temperature adjustment, an example of which is shown in FIG.

406...Programmable read-only memory (hereinafter abbreviated as PROM) 411-412 and 421-427...Integrated resistors 441-448...Sequentially limited to one at a time by the sweep of the counter 203 in FIG. Analog switches that conduct (e.g. transmission gates,
transfer gate) 451... Node to which the reference voltage is supplied 458... Node from which the potential of the node selected from 431 to 438 is obtained 454... Positive power supply 438... Negative power supply Resistor in the circuit of Fig. 4 When the resistance values of the resistors 411 to 412 are respectively R ₁₁ to R ₁₂ and the resistance values of the resistors 421 to 427 are R ₂₁ to R ₂₇ respectively, the contact 43
1 to 438 are contacts 312 to 31 in FIG. 3, respectively.
9, each resistor must be designed to satisfy the following conditions.

R ₁₁ /R ₁₂ =R ₂₁ +R ₂₂ +R ₂₃ /R ₂₄ +
R ₂₅ +R ₂₆ +R ₂₇ (1) When the resistance values of resistors 303 to 309 in FIG. 3 are respectively R ₀₃ to R ₀₉ , R ₀₃ /R ₂₁ =R ₀₄ /R ₂₂ =R ₀₅ / R ₂₃ =
R ₀₆ /R ₂₄ =R ₀₇ /R ₂₅ =R ₀₈ /R ₂₆ =R
₀₉ /R ₂₇ (2) MOSFETs 402 to 403 and 514 in FIG. 5 are designed to operate in the saturation region, so they function as voltage-controlled current sources controlled by the gate voltage.

In Figure 5, 511 is the transmission gate.
512 is an inverter, 513 is for fixing the gate voltage of 514 to high when 511 is off.
MOSFET, 504 is the positive power supply, 501,5
02 and 503 are respectively 453 and 455 in Figure 4
(or 456), 457. Currently, the crystal oscillator has a peak temperature of 21℃ and 23℃.
It is classified into 4 groups: 25℃, 27℃, MOSFET 402 and resistor 41.
1 and 412 so that the potential at the node 452 corresponds to a temperature of 25°C, and the resistors 421 to 427 are set so that the potential at the node 452 corresponds to a temperature of 431-43°C, 432-37°C, and 433-427.
31℃, 434-25℃, 435-19℃, 436-13
℃, 437-7℃. If the peak temperature of the crystal oscillator actually used is 25℃, the potential of node 434 is 25℃.
A combination of activation and deactivation of 404 and 405 is determined and written into the PROM 406 so that The positions of dividing points 431 to 438 in the resistor array are designed to match the crystal oscillator with a peak temperature of 25°C, so in this case, the potential at each node corresponds accurately to the temperature, and the resistor array 4
The current flowing through nodes 21 to 427 is i, and the nodes 438 and t
Letting Rt be the resistance value between the node corresponding to t°C, the potential at the node 434 is iR ₂₅ (3) and the potential at the node corresponding to t°C is iRt(4). Next, the peak temperature of the crystal oscillator used is 23
℃, the current flowing through the resistor strings 421 to 427 must be reduced by Δi by adjusting the activation/deactivation of 404 and 405 so that the potential of node 434 corresponds to 23°C. At this time, the potential of the node 434...(i-△i)R ₂₅ (5) The potential of the node corresponding to t-2℃
...(i-△i)Rt(6). From (3) and (5), △iR ₂₅ is a voltage equivalent to 2°C. Therefore, the potential expressed by equation (6) does not exactly correspond to t-2°C, but corresponds to t-2(Rt/R ₂₅ )°C.

By the way, when applying the circuit shown in Figure 4 to the temperature correction of a watch crystal oscillator, the target temperature range is -
The temperature is about 10℃ to 50℃. Furthermore, if an integrated resistor is used in the temperature sensor 201 in FIG. 2, the temperature signal obtained in 211 in FIG. 2 will vary within a range of ±20% around 25°C. Therefore,
Rt/R ₂₅ can also be considered to vary within a range of ±20%.

From the above, the maximum error expected in the detected temperature is 2
The temperature is 0.4°C when the peak temperature is adjusted to 4°C, and 0.8°C when the peak temperature is adjusted to 4°C. This detection error affects the accuracy of the clock in the worst case (such as when it is left at -10°C).
0.03 (seconds/day), which can be considered a sufficiently small amount. Incidentally, when the apex temperature is adjusted in four stages as in the example described here, the number of PROM bits required is two. Generally, when the apex temperature adjustment is performed in steps of 2 ^{n -1} to 2 ⁿ , the number of PROM bits required is n.

The present invention has the effect of significantly reducing errors caused by variations in the peak temperature of the crystal oscillator when temperature correction is performed on the crystal oscillator by providing a temperature sensor in a watch integrated circuit and applying logic adjustment. .

[Brief explanation of the drawing]

FIG. 1a shows the temperature characteristics of the crystal resonator and the corrected temperature characteristics when applying the theoretical adjustment, and FIG. 1b shows the deviation of the peak temperature of the crystal resonator.
FIG. 2 is an example of a block diagram of a temperature detection circuit. FIG. 3 shows a conventional configuration, and FIGS. 4 and 5 show an embodiment of the present invention.

Claims (1)

[Claims] 1 Approximate 2 by using a temperature detection circuit
In a temperature compensation circuit for a crystal resonator that performs temperature compensation for a crystal resonator having temperature characteristics according to the following curve, the temperature detection circuit includes a temperature sensor 201, a reference voltage generation circuit 204, and a voltage output from the reference voltage generation circuit. Counter 20 for selecting the level of reference voltage
3, and a comparator 202 that compares the output of the temperature sensor and the reference voltage to set the contents of the counter, and the reference voltage generation circuit is formed by connecting a plurality of resistors 421 to 427 in series. A resistor string and a MOSFET 514 connected in series to the resistor string.
A plurality of current source circuits 4 connected in parallel to each other including
04, 405, and a memory circuit 406 that stores the activation and inactivation of the MOSFET, and stores the activation and inactivation of the MOSFET according to the peak temperature of the crystal resonator.
1. A temperature compensation circuit for a crystal resonator, characterized in that the reference voltage is supplied from a node of the resistor string selected by the counter.