JPS6260325A - Signal changeover device - Google Patents

Abstract

PURPOSE:To transmit an input signal to other processing stage through 3 lines by applying the DELTAM system to n-set of input signals to apply A/D conversion and arranging the n-set of signals in time series to one bit of quantization so as to output them. CONSTITUTION:When switches 2, 16 of n-input/1-output exist on the position 1, a comparator 3 compares an input signal 1 and an output signal of an integration device 12, and the result is inputted to a D-FF 4. The D-FF 4 uses a clock to sample the data at a period of T1 and supplies an output on a line 13. A D-FF 8 uses a control pulse C1 to latch its output signal, which is inputted to an integration device 12, where the signal is integrated. The similar processing is applied up to the integration device (n). The input signal 1 when the switch is thrown to positions 1-n is sampled by a sampling period of nT1, the data sampled by a period of the clock T1 is arranged in time series when the switch exists on the positions 1, n to form a 1-bit signal, which is an output of the D-FF 4 and sent to the next stage.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal switching device for switching audio input signals from external audio input devices such as television receivers and stereo amplifiers.

Conventional technology In recent years, analog signal processing has changed to digital signal processing, and digital signal processing has been introduced starting with relatively low frequency signals such as audio signals. The signal is switched and converted into a digital signal by a MU/D converter.

An example of the conventional analog signal switching mentioned above will be described below with reference to the drawings.

゛　　　Figure 8 shows analog signal switching.

In FIG. 8, a number of inputs 44 are input to a switch 25 with a input and one output, and the output of the switch 25 is input to a Mu/D converter 27, where it is subjected to Mu/D conversion, and the output line 28
to obtain the digital conversion output.

The switch 26 is controlled by a control circuit 26, and the position of the switch 26 is determined by a control signal input from a control line 29.

Problems to be Solved by the Invention However, in an analog signal switching circuit as shown in FIG. 8, the number of control signals increases as the number of input signals increases. This is because each control signal is sent in the form of high level (H) or low level (L).
When the number of inputs is 1 to 2, it is 1, when it is 4 or less, it is 2, when it is 8 or less, it is 3, and when it is 16 or less, it is 4...For 1 or less, 1og21 (2'\i ), l −(21=
i>, and as the number of input signals increases, the number of control signals increases.If the switch 26 and the MU/D converter 27 are separated, and the control signal generation part is separated, it is necessary to connect The increase in the number of lines increases the cost of the lines, and the increase in the number of lines increases the complexity of the structure and the complexity of the work.

Means for Solving the Problems In order to solve the above problems, the present invention inputs n analog signals to a first n-input 1-output switch circuit,
The output of the first switch circuit is inputted to one of the comparators, the output of the comparator is inputted to the D-flip-flop which operates with a clock of period T, and the D-7
The outputs of the lip flops are input to n D-clip-flops respectively, t, and the outputs of the n D-clip-flops are
Each input is input to n integrators, and the outputs of the n integrators are input to the second n-input 1-output switch circuit. , the first switch and the second switch are configured to be switched synchronously by switch control of a switch control/control pulse generation circuit, and the switch control/control pulse generation circuit is controlled by a start pulse; , the clock with the above period T is input, and the switch control/control pulse generation circuit outputs n pulses with a period different by T1 of the period nT, and each of these pulses is inputted with the above period T.
The clock pulse is supplied as a clock pulse to two D-flip-flops.

Operation According to the present invention, the conhalator, the integrator, and the D-flip-flop basically constitute ΔM with the above-described configuration. Here, ΔM will be explained.

First, in FIG. 6, the input signal (ei, 1 is input to the comparator 31 from the line 3o, is compared with the comparison signal (ec) on the line 32, and (ei, -ec
) to obtain the error signal (ee). According to this error signal ee, the comparator 31 outputs a comparator output on line 34, and this comparator output signal is
- Quantization is performed with clock 3e by FF3s. The quantized output of the D-FF 35 becomes a 1-bit signal and is output to the line 37, a part of which is passed through an integrator 38 to obtain a comparison signal (ec) as the output of the integrator 38, which is input to the comparator 31. . That is, .DELTA.M is a method of quantizing the input signal e1 while making the 1-bit output signal follow the output of the integrator 38.

The signal switching device of the present invention uses the ΔM-based Mu/D converter as described above to perform Mu/D conversion on n input signals using the ΔM method, and converts the n input signals into 1-bit data. By treating it as a quantized signal, and by outputting each of the n signals in time series for each 1-bit quantization, the clock, start pulse, and 1-bit quantization output are This line can transmit input signals to other processing stages.

Embodiment A signal switching device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a signal switching device in an embodiment of the present invention. In FIG. 1, 1 is a switch with n input signals, 2 is a switch with n inputs and 1 output, 3 is a comparator, and 4 is a D that operates with a clock applied from line 14.
-Flip-flop (D-FF), 5.6, 7, 8 are D
-FF operates with different control pulses for each phase. 9
, 10゜11.12 is an integrator, 16 is a switch with n inputs and 1 output, and 18 is a switch 2, 160 control and D-FF5
, 6, 7.8 switch control and generates control pulses for
This is a control pulse generation circuit. A start pulse is applied from line 16 to switch control/control pulse generation circuit 18 .

Regarding the signal switching device configured as above, the following is the first section.
The operation will be explained using the diagram and FIG.
-FF7. D-FF4 and D-FF6. D-FFa and D-
D-FF31 in FIG. 6 described in the section where each of the FF5 functions
is the same as D-FF4 is operated by the clock on line 14, and D-FF8 to D-FF5 are operated by the clock on line 14, and D-FF8 to D-FF5 are operated by C1 to D-FF5 whose clock cycle is n times as long as the clock and whose clock cycle is different by one cycle.
It operates with Cn pulses. Therefore, the period of the clock is T.

Then, it operates at the cycle of the pulse unT on line 17, and has a sampling cycle of 1/nT. Therefore, when the n-input and 1-output switches 2 and 16 are in the position (1) in Fig. 1 (see the state of switch 2.16 in Fig. 2)
, comparator 3 receives (1) of input signal 1 and integrator 1
The two output signals are compared and the result is input to the D-FF4. D
-FFa uses a clock to sample the data at a period of T, and outputs it on line 13. The output signal is latched by D-FFa using the control pulse C4, and is input to the integrator 12 for integration. This integrator 12 holds the integrated output until the next data arrives.

Next, when the states of switches 2 and 16 become 02), comparator 3 outputs (2) of input signal 1 and integrator 1.
Compare the output signals of 1 and input the result to D-FFa. D
-FF4ij clock samples the data at a period of T, and outputs the output to line 13. As described above, the same thing is done up to the integrator n, and the switch control/control pulse generation circuit 1 uses the start pulses shown in Figs.
8 is reset and the same thing is done from input signal (1). As described above, (1) to (n) of input signal 1 are each
sampled with a sampling period of n'r, and the second
As shown at the bottom of the figure, the data sampled at the clock cycle is arranged in time series as shown in (1) and (n) and becomes a 1-pit signal, which becomes the output of D-FFa and goes to the next stage. transmitted.

The data on line 13 transmitted in the above state is received by the receiving side, and if there is a clock and start pulse, control pulses C4 to Cn are created from the clock and start pulse in the same way as above, and D- If it passes through an FF, the input signal ΔV
You can get the signal. Its block diagram is shown in FIG. In this figure 3 and figure 4, from figure 1, D
-The output data of FF4, clock, and start pulse signals are input to the D-FF20, and the clock and start pulses are input to the control unit 24, and the signals are output at the same timing as Ck of the control pulses in Fig. A control pulse is generated from one control unit 24 and inputted to the D-FF 20 as a clock pulse for the D-FF 20. Then, the data at the D-FF output with period nT in FIG.
Input signal 1 (k) in the figure can be reproduced.

Further, the output of the D-FF 20 in FIG. 3 is input to a digital integrator 39 as shown in FIG. Digital LPF 40, switch 41. If digital conversion is performed using the quantization circuit 42, a PCM code is obtained on the output line 43, so that the signal can also be subjected to digital signal processing. Regarding this conversion circuit,
! Ln, D, J,): The application op delta modulation to analog to bcm encoding ("The applic &
tion ofDelta modulation
o person nalog to PCMθncoding”,)
Bell System Technology (Bell 5yst, T
ech, N J,, 48.2, PP, 321-342.
(Feb, 19e9)), (The Institute of Electronics and Communication Engineers Watata, “Applications of Digital Signal Processing” JP, P, 144. (June 1986)
It is introduced in detail on the 20th of May)).

Effects of the Invention As described above, according to the present invention, an analog signal can be converted into a 1-pit ΔM signal using ΔM, and the ΔM signal can be converted into a PCM signal using a digital circuit, and digital signal processing can be performed. As mentioned above, n input signals can be transmitted using three lines: data, clock, and start pulse.
Using F, it is possible to easily extract one signal from n input signals, and signal processing can be performed by converting ΔM reproduced by simple digital processing into PCM. In addition, the block shown in Figure 1 can be easily integrated into an IC, and the analog part consists of switches, comparators, and integrators, and everything else can be constructed from digital circuits, so it can be manufactured at a lower cost than a normal A/D converter. It also has the advantage of being able to

[Brief explanation of drawings]

FIG. 1 is a block diagram of a signal switching device according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIGS. 3 and 4 are block diagrams of ΔM7 analog conversion means and 5 is a block diagram of the ΔMPCM conversion means, 6 and 7 are block diagrams showing the principle configuration of ΔM and a waveform diagram for explaining the operation, and FIG. 8 is a diagram of the conventional ΔMPCM conversion means. FIG. 2 is a block diagram of a signal switching device. 2...n input 1 output switch, 3...
Comparator, a・----D −F F(o),
5...--D-F F(n), 6...--D-
F F (n-1), 7-・-D-F F (2), 8・
...D -F F (1), 9 ... Integrator (n), 10 ... Integrator (n-1), 11
......Integrator (2), 12...Integrator (
1), 16...n input 1 output switch, 18...
...Switch control/control pulse generation circuit 0 Name of agent Patent attorney Toshio Nakao and one other person Figure 2 Figure 3 Figure 4 η-Tl Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] n analog signals are input to a first n-input 1-output switch circuit, the output of the first switch circuit is input to one of the comparators, and the output of the comparator is input with a period T.
The outputs of the D-flip-flops are input to n D-flip-flops, and the outputs of the n D-flip-flops are each subjected to n integrals. input the outputs of the n integrators to a second n-input 1-output switch circuit,
A second n-input, one-output switch is input to the other side of the comparator, and the first switch and the second switch are configured to be switched synchronously by switch control of a switch control/control pulse generation circuit. , the switch control/control pulse generation circuit is controlled by a start pulse and is inputted with the clock of period T_1, and the switch control/control pulse generation circuit is controlled by the start pulse and receives the clock of period T_1.
A signal switching device characterized in that it outputs n pulses each having a different period and supplies each of these pulses as a clock pulse for the n D-flip-flops.