JPS6260320A - Error correction circuit - Google Patents

Abstract

PURPOSE:To ensure the error position of 2-bit or over simply by giving a syndrome to an address of a storage device and outputting a data representing the bit error location decided by a syndrome from the storage device. CONSTITUTION:A received data M'(X) is inputted to a syndrome detection circuit 11 in an error correction circuit to obtain a syndrome S(X). An error position detection ROM 12 uses the syndrome S(X) as an address input and a data E(X) representing the bit error location specified by the syndrome S(X) is outputted. That is, each data is stored in a storage location of the ROM 12 addressed by using the syndrome corresponding to all bit errors. Then the error bit of the received data M'(X) is inverted by a circuit composing of the error bit inverting circuit 13 based on all data E(X). Thus, the error correction is applied without a complicated algorithm and then the circuit constitution is simplified and the reliability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an error correction circuit used when accepting and decoding block code data having error correction capability.

[Technical background of the invention and its problems]

In recent years, with the development of digital communication technology, error correction codes have been widely used. Error correction technology is an essential technology, especially in wireless digital communications where the reliability of the transmission path is low, such as satellite communications and mobile communications.Furthermore, in recent years, error correction technology has also been used for recording and reproducing digital signals on magnetic recording devices. Widely used. Error correction codes can be broadly divided into block codes and convolutional codes, but block codes using cyclic codes are known to have various levels of redundancy and error correction ability, and are widely used. has been done.

By the way, among the cyclic codes, the BC)-1 (Porth Chaudhry Ockenziem) code is a code that corrects random errors, and algorithms for determining error positions of 2 or more bits include Peterson's method, Verrenkumbe's method, Various methods have been proposed, such as Matsushii's method. However, all of these methods require extremely complex calculations, so it is difficult to say that they are useful in practice, and they are generally not used for corrections of 2 bits or more. That was the actual situation.

(Objective of the Invention) The present invention was made based on the above circumstances, and its purpose is to provide an error correction circuit that can determine the error position of two or more bits using an extremely simple method. It's about doing.

[Summary of the invention]

The present invention provides a syndrome detection means for calculating a syndrome by dividing received data consisting of information bits and redundant bits by a generating polynomial, and a syndrome detection means for inputting this syndrome detection means as an address and bits uniquely specified by the syndrome. It is characterized by comprising a storage means for outputting data indicating the error position, and an error bit correction means for correcting the error bits of the received data using the output data from the storage means.

〔Effect of the invention〕

According to the present invention, a syndrome is given to the address of the storage device, and data indicating the bit error position determined by the syndrome is outputted from the storage device as output data. This can be done without using. Therefore, the circuit configuration is simplified, and the communication system thereby
It can contribute to improving the reliability of magnetic recording devices, etc. This effect becomes more noticeable as the number of bits that can be corrected increases.

[Embodiments of the invention]

The present invention will be explained in detail below.

Here, we will consider a case where a BCH code is used as an example.

Now, the code word M(X) of the error correction code is a Galois field GF (
Q), whose generating polynomial G(×) is GF
When defined by the element of the extension field GE(qm) of (q), the code IM(X) is divisible by G(X). If such a code word M(X) is adopted, the input code word M'
Whether or not an error has occurred can be determined by whether (X) is a generator polynomial and is divisible by G(X).

If the input code word M' (X) includes a transmission error, the remainder when the code word M' (X) is divided by G (X) will not be O. The bit where the error occurred is set to “1'',
Let E (X) be a code string in which the rest is 0, then M' (X) = M (X) + E (X) ('10' is modulo 2 addition), so M' (X) can be The remainder after dividing by a<X> is equal to the remainder of E (X)/G (X).
This remainder is called syndrome 5(X). If this syndrome 5(X) can take different values for all patterns of errors up to 2 bits, then errors up to 2 bits from syndrome 5(X) can be corrected.

FIG. 1 is a diagram showing an embodiment of the present invention. That is,
This error correction circuit includes a syndrome detection circuit 11 that obtains the above-mentioned syndrome from received data M'(X);
Syndrome 5(X) outputted from this syndrome detection circuit 11 is inputted as an address,
Data E indicating the bit error position specified by
(X) and the data E (X>
The error bit inverting circuit 13 inverts the error bits of the received data M'(X) based on the error bits of the received data M'(X).

Now, the received data M' (X) has a code bit length of 31 (
Assume that the BCH code has an information bit length of 16, a redundancy bit length of 15), and is capable of correcting errors of up to 3 bits (31.16). Then, the generator polynomial is defined as Q (X) =X1
' +X11 +XI O+X9+ Xll + X
7 + X5 + Xl + X2+x+1.

Such 31-bit received data M' (X) is
When input to the syndrome detection circuit 11, the syndrome detection circuit 11 divides the received data M'(X) by the generating polynomial a(X) to calculate syndrome 5(X). Syndrome 5(X) is the generator polynomial a (X)
Since the order of is 15, the data is 15 bits.

FIG. 2 shows an example of syndrome 5(X) detection. Note that here, for simplicity, the generator polynomial is g' (X)
An example where =X5+X2+i is shown.

That is, first, before data input, the delay circuit 21.2
2.23.24.25 are all cleared. Next, the received data serially input from the higher order bit is E
The X-OR circuit 26 performs an exclusive OR with the output signal of the delay circuit 25 and provides the result to the delay circuit 21 . The bit data input to the delay circuit 21 is sequentially shifted to the delay circuits 22 to 25 according to a predetermined clock, but is again exclusive to the output of the delay circuit 25 in the EX-OR circuit 27 between the delay circuits 22 and 23. The logical OR is taken. For syndrome 5 (X), the last bit of the received data is input to the syndrome detection circuit 11 and roughly EX-OR
When the signal is output from the delay circuit 21 via the circuit 26, it is obtained as the output signal of the delay circuits 21-25. 1 mentioned above
Even in the case of a fifth-order generator polynomial 〇(X), the delay circuit is 15
A detection circuit based on the same principle as the circuit shown in FIG. 2 can be constructed by simply using the stages.

The syndrome S(X> thus obtained is given to the error position detection ROM 12 as address data.

For example, if the lower 16 bits are incorrect, the syndrome is the remainder when X15 is divided by Q (X), so S (X> =X” 1 +xl O+X9 +X8+
XT+XS +X3 +X2 +X +1. Therefore, the following address data is given to the address of the ROM 12. Then, the storage location of the ROM 12 indicated by this address contains oooooooooooo
ooooooiooooooooooooooo.

This data is stored and output.

For example, if the 3-bit data of the lower 4th bit, 16th bit, and 17th bit is incorrect, the syndrome S (X) is
), so S (X) −Xl 2+
It becomes X7 +X6+X'+X' +X3+1. Therefore, the following address data is given to the address of the ROM 12. Then, data is stored in the storage location of the ROIv 112 indicated by this address, and this data is output.

In this way, the RO addressed by the syndrome corresponding to all 1-bit errors, 2-bit errors, and 3-bit errors
In each storage location of M12, 31-bit data with "1" set at each bit error position is stored in advance.

The errors that can be corrected are 31 1-bit errors, 3102 = 465 2-bit errors, and 3 t3-bit errors.
Since C3 = 4495 ways, 21 & = 327
This corresponds to about 1/6 of the 68 addresses. Hey,
If no bit error has occurred, the syndrome detection circuit 11 specifies the address (00...OO), so data (00...00) is stored in this location. If an address other than this is specified, this indicates that an error of 4 bits or more has occurred, and in this case, error correction is impossible. therefore,
All of the storage locations in the ROM 12 designated by such addresses store special data indicating that correction is impossible, for example, data (11...11).

The output data of the ROM 12 is input to the error bit inversion circuit 13. The error bit inversion circuit 13 is configured as shown in FIG. 3, for example. That is, the received data M
'(X) is serially input to a 31-bit shift register 31. When all bits of the 31-bit received data are stored in the shift register 31, the received data is transferred from the shift register 31 to the 31-bit latch circuit 3.
It is latched to 2. And each bit data is EX
It is given to one input of the -○R circuits 331, 332, . . . , 3331. On the other hand, the error position data E(X) from the error position detection ROM 12 is also latched in the 31-bit latch circuit 34, and the EX-OR circuits 331 and 332 are respectively latched.
, . . , 33 is given to the other input of 1. Further, the output of the latch circuit 34 is also input to an AND circuit 35.

If there is no error in the received data, the latch circuit 34
Since the output of is all 0'', the received data is EX-
OR circuit 33, 332,...

333 It is not influenced in any way by the construction and is output as is.

On the other hand, if there is an error of 3 bits or less in the received data, the ROM 12 outputs data with "1" set at the error position, so the input data is sent to the EX-OR circuit 331.
．． 332, . . . , 3331, and error-corrected data M (X> is
Circuits 33t, 332.

..., output from 3331.

Furthermore, if an error of 4 bits or more occurs, all the outputs of the latch circuit 34 become "'1", so the AND circuit 3
The output of 5 is inverted from "○" to 1, and this is output as the error detection signal ERR.

In this way, according to this embodiment, the error position detection ROM 12
It is clear that random errors of 2 bits or more can be corrected by using an extremely simple circuit configuration using an extremely simple circuit configuration, and without using any complicated algorithms, and it will greatly contribute to the practical application of error correction codes.

Note that the present invention is not limited to the embodiments described above.

For example, in the above embodiment, 31 EX-OR circuits are used to perform an EX-OR operation between the received data and the data indicating the bit error position.
Although the OR is performed in parallel, since the received data is input serially, if the output data of the error bit inversion circuit 13 is also output one by one, EX-O
One R circuit is sufficient. FIG. 4 shows a circuit constructed based on this idea.

That is, of the address given to the error position detection ROM 41, the lower 15 bits are given with syndrome 5(X) similar to the above embodiment, and the upper 5 bits are given with a 5-bit counter 4.
Gives the output from 2. Then, the counter 42 is sequentially counted up according to a predetermined clock to update the address.

In the ROM 41, for example, as shown in FIG.
Out of the 31-bit bit error position data specified by the syndrome, only 1 bit of bit data at the bit position determined by the upper 5 bits is stored as data in the storage location of the address configured by combining and the syndrome. has been done. For example, as shown in Figure 5,
As mentioned above, when the syndrome is , the bit error position data is . However, in this example, only 1-bit data at the bit position specified by the output of the counter 42 out of the 31-bit data is stored in the ROM 41 . I am trying to store it internally. Then, the output of the ROM 41 and the received data are input to an EX-OR circuit 43 for error correction.

With this configuration, 31-bit data is serially output from the ROM 41 by counting up the counter 42, so the 31-bit shift register 31 and latches 32 and 34 as shown in FIG. 31
There is an advantage that (7) EX-OR circuits 331 to 3331 are not required.

Furthermore, in the above embodiment, 31-bit data is used as the data indicating the error position, and the pitch data of this data is 1''.
Although this part has been shown to be an error, this 31-bit data may be represented as 5-bit binary data. An example of this is shown in FIG.

That is, the error position detection ROM 51 is divided into a first area where the highest address of the memory space is "O11" and a second area where the highest address is "1". and,
5-bit binary data indicating the position of the higher-order error bit among the 2-bit errors is stored in the storage location specified by the corresponding syndrome in the first area, and 5-bit binary data indicating the position of the lower-order error bit Bit binary data is stored in the memory location specified by the corresponding syndrome in the second area. Initially, the most significant bit of the address of the ROM 51 is set to “OII.”
The output of 51 is introduced into a first input terminal of comparator 52. On the other hand, the second input terminal of the comparator 52 is supplied with the output from the 5-bit counter 53.

The counter 53 is driven by a high-speed clock φ and is (0
) to (31) are output. The comparator 52 outputs 1°' when both human force data match. On the other hand, the received data M'(X) is introduced into the shift register 54.

This shift register 54 is driven by the high speed clock φ of the counter 53. Therefore, comparator 52
When 1" is output from the shift register, the bit data being output from the shift register is an error. Therefore, when the output of the comparator 52 becomes 1111+, the output of the shift register 54 is sent to the EX-OR circuit 55. If it is reversed, error correction can be performed.
Since the "1" output from the comparator 52 is given to the set (S) terminal of the RSS flip flow path 56, the output of the RSS flip flow path 56 changes from O" to "
1", and the high-order bit of the address in the ROM 51 becomes "1". Then, the second bit error correction is performed again in the same procedure. When the error correction is completed, the counter 53 and the RS flip-flop 56 reset (R
) terminal is given an external reset signal R8.

If the number of error bits that can be corrected increases, the number of RS flip-flops can be increased.

With such a configuration, the capacity of the error position detection ROM 51 can be reduced to 5/31 compared to that of each of the embodiments described above.

In addition, the present invention may use other storage devices such as a RAM or a magnetic disk as a storage device for detecting bit error positions from syndromes.

Further, the type of cyclic code is not limited to BCH, and the present invention can be applied to any code having an error correction ability that can identify bit error positions from syndromes.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an error correction circuit according to an embodiment of the present invention, Fig. 2 is a block diagram showing an example of a syndrome detection circuit in the error correction circuit, and Fig. 3 is an error bit inversion in the error correction circuit. 4 is a block diagram showing a part of an error correction circuit according to another embodiment of the present invention; FIG. 5 is a block diagram showing the contents of a ROM in the error correction circuit; FIG. The figure is a block diagram showing a part of an error correction circuit according to still another embodiment of the present invention. 21-25... Delay circuit, 31... Shift register, 32.34... Latch circuit, 56... RSS flip flow path. Applicant's representative Patent attorney Takehiko Suzue Figure 1 E (X) Figure 4 Figure 5 5 (X) Figure 6

Claims (3)

[Claims] (1) Syndrome detection means for dividing received data consisting of information bits and redundant bits by a generating polynomial to obtain a syndrome, and inputting the syndrome outputted from this syndrome detection means as an address and uniquely determining the syndrome from the syndrome. The method is characterized by comprising: a storage device that outputs data indicating a bit error position of the received data determined by the storage device; and an error bit correction means that corrects error bits of the received data using output data from the storage device. error correction circuit. (2) The storage device outputs data that only indicates that there is an error in the received data when the bit error position cannot be uniquely determined from the syndrome. The error correction circuit described in Section 1. (3) The storage device includes a counter, gives the syndrome to a part of the addresses of the storage device, and gives the output of the counter to the remaining addresses, so that among the data indicating the bit error position specified by the syndrome, 2. The error correction circuit according to claim 1, wherein the error correction circuit outputs bit data at a position specified by the counter.