JPS6260218A - Thin film growth method - Google Patents

Thin film growth method

Info

Publication number
JPS6260218A
JPS6260218A JP20087285A JP20087285A JPS6260218A JP S6260218 A JPS6260218 A JP S6260218A JP 20087285 A JP20087285 A JP 20087285A JP 20087285 A JP20087285 A JP 20087285A JP S6260218 A JPS6260218 A JP S6260218A
Authority
JP
Japan
Prior art keywords
thin film
compound semiconductor
substrate
molecular beam
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20087285A
Other languages
Japanese (ja)
Inventor
Yuichi Matsui
松居 祐一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP20087285A priority Critical patent/JPS6260218A/en
Priority to AU62456/86A priority patent/AU590327B2/en
Priority to DE8686112487T priority patent/DE3688028T2/en
Priority to EP86112487A priority patent/EP0215436B1/en
Priority to CN86106177.2A priority patent/CN1004455B/en
Priority to EP92107691A priority patent/EP0499294A1/en
Priority to KR1019860007530A priority patent/KR870003552A/en
Publication of JPS6260218A publication Critical patent/JPS6260218A/en
Priority to CN88108172A priority patent/CN1009885B/en
Pending legal-status Critical Current

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  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

PURPOSE:To prevent the electric characteristics from deteriorating by a method wherein a compound semiconductor substrate or compound semiconductor basic film is irradiated with Sb molecular beam before they are epitaxially grown and after removing any impurity atoms on the surface, a specified compound semiconductor thin film is grown. CONSTITUTION:An InP substrate 28 is heated while keeping the degree of vacuum near the substrate 28 at 1X10<-6>Torr-1X10<-5>Torr using As4 molecular beam (a) and then further irradiated with Sb molecular beam (b) at the intensity of 1X10<-8>Torr. Later the cell shutter 31 of an In cell 33 and the other cell shutter 34 of Ga cell 36 are opened and then an InGaAs thin film is continuously grown on the InP substrate 28. In other words, the compound semiconductor thin film is irradiated with electrically neutral Sb molecular beam immediately before said thin film is molecular beam-epitaxially grown. Through these procedures, the impurity carrier concentration can be reduced by one figure to increase the electron mobility improving the electric characteristics of InGaAs thin film.

Description

【発明の詳細な説明】 本発明は、マイクロ波素子あるいは発光・受光素子とし
て使用する化合物半導体薄膜を形成するための結晶成長
方法に関する。たとえば第2図に示すような高電子移動
度トランジスタ(以下、「HEMT」と略す)において
は、チャンネル層として数100A〜数100OA厚の
薄膜を形成する必要があり、本発明は、このような構造
を形成するための薄膜成長方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a crystal growth method for forming a compound semiconductor thin film used as a microwave device or a light emitting/light receiving device. For example, in a high electron mobility transistor (hereinafter abbreviated as "HEMT") as shown in FIG. 2, it is necessary to form a thin film with a thickness of several 100 Å to several 100 OA as a channel layer. This invention relates to a thin film growth method for forming structures.

(従来技術とその問題点) 薄膜成長を行なう前の、基板表面あるいは下地の薄膜層
表面上に不純物原子が残留していると、その上に形成し
な薄膜層の電気特性が低下したり、あるいは表面状態が
あれる。このことから、従来より、以下に述べるような
薄膜成長方法が行なわれている。
(Prior art and its problems) If impurity atoms remain on the surface of the substrate or the underlying thin film layer before thin film growth, the electrical properties of the thin film layer formed thereon may deteriorate, or Or there is a surface condition. For this reason, thin film growth methods such as those described below have been conventionally used.

第8図、第4図、第5図は、従来の■−V族化合物半導
体薄膜を形成するための分子線エピタキシャル成長方法
(以下、MBE法と略す)を説明するための図で、MB
E装置の成長室を上から見た概略図である。
8, 4, and 5 are diagrams for explaining the conventional molecular beam epitaxial growth method (hereinafter abbreviated as MBE method) for forming a conventional ■-V group compound semiconductor thin film.
FIG. 2 is a schematic diagram of the growth chamber of the E apparatus viewed from above.

第3図において、■は基板ホルダー、■は基板、■はセ
ルシャッター、■は■族原料(たとえば、Ga あるい
はIn)、■はセル、■はV族原料(たとえばAsある
いはP)、■はセルである。
In Figure 3, ■ is a substrate holder, ■ is a substrate, ■ is a cell shutter, ■ is a ■ group raw material (for example, Ga or In), ■ is a cell, ■ is a V group raw material (for example, As or P), and ■ is a It is a cell.

従来のMBE成長による■−V族化合物半導体薄膜成長
方法の内、第3図においては、真空度の高い成長室内に
おいて、セル■からV族元素を分子または原子状にして
、基板■に照射させることにより、基板■からのV族元
素の脱離を抑制しながら基板温度を上昇させ、基板表面
上の不純物原子のみを脱離させる。しかしながら、この
ような方度以上の高温に、基板を加熱する必要がある。
In the conventional method for growing ■-V group compound semiconductor thin films by MBE growth, in Figure 3, group V elements are made into molecules or atoms from cell ■ and irradiated onto substrate ■ in a growth chamber with a high degree of vacuum. By doing so, the substrate temperature is increased while suppressing the desorption of Group V elements from the substrate (1), and only the impurity atoms on the substrate surface are desorbed. However, it is necessary to heat the substrate to a high temperature higher than this temperature.

しかし、基板を、上記臨界温度以上の高温にまで加熱す
ることによって、熱伝導により基板ホルダー■も高温に
加熱され、基板ホルダー■からの不純ガスの脱離も多く
なる。この結果、成長室内のハッククラランド真空度全
低下させることになり、このことは、引きつづき成長さ
れる薄膜層の不純物濃度と増大させ、電気特性に劣化さ
せる。また、これとは別に、たとえば基板上に薄膜層全
成長した後、電極などの形成、あるいは微細加工と、成
長室外の大気中で施した後、さらに、その上に、上部薄
膜層を再成長させる場合には、下地の薄膜層上の不純物
を除去する必要が生じる。この際、前記臨界温度以上の
高温にまで加熱すると、下地の薄膜層と電極金属との間
で合金化反応が必要以上に生じてしまい薄膜層の特性が
劣化する。あるいは、下地の薄膜層が多層薄膜構造であ
る場合には、隣接する薄膜層間でのドーピング原子の拡
散や、母相原子の拡散が生じ、薄膜層界面や薄膜層自体
の電気特性を劣化させてしまう。
However, by heating the substrate to a high temperature higher than the above-mentioned critical temperature, the substrate holder (2) is also heated to a high temperature due to thermal conduction, and more impurity gas is desorbed from the substrate holder (2). This results in a total reduction of the Huck-Clland vacuum in the growth chamber, which increases the impurity concentration of the subsequently grown thin film layer and deteriorates the electrical properties. Separately, for example, after the entire thin film layer is grown on the substrate, electrodes are formed or microfabrication is performed in the atmosphere outside the growth chamber, and then the upper thin film layer is regrown on top of it. In this case, it becomes necessary to remove impurities on the underlying thin film layer. At this time, if the material is heated to a high temperature higher than the critical temperature, an alloying reaction will occur between the underlying thin film layer and the electrode metal more than necessary, and the properties of the thin film layer will deteriorate. Alternatively, if the underlying thin film layer has a multilayer thin film structure, doping atoms or matrix atoms may diffuse between adjacent thin film layers, deteriorating the electrical properties of the thin film layer interface or the thin film layer itself. Put it away.

1[1−V化合物半導体薄膜を成長するための他のMB
E法として、第4図に示す方法も従来より成されている
。第4図において、■は基板ホルダー、■ハ基板、[相
]はイオンガン、■、■はセルシャッター、Oは■族原
料、■はセル、■はV族原料、[相]はセル、OはAr
ガス導入口である。第4図の方法においては、真空装置
内に、Arガスを導入することによって、基板■の表面
に、イオンガン[相]k用いてArイオンビームを照射
する。この結果基板■の表面は、基板温度全土げること
なく清浄化されることができる。しかしながら、Arイ
オンビームによる照射によって、基板■の表面は著しい
照射損傷と受けることになり、基板■の表面の結晶格子
は著しく乱れ、多くの欠陥が発生してしまう。このなめ
、引きつづいて、基板表面上に成長された薄膜層の結晶
性も著しく低下してしまい電気特性も低下する。
1 [Other MB for growing 1-V compound semiconductor thin film
As the E method, the method shown in FIG. 4 has also been conventionally used. In Figure 4, ■ is a substrate holder, ■ is a substrate, [phase] is an ion gun, ■, ■ is a cell shutter, O is a group ■ raw material, ■ is a cell, ■ is a group V raw material, [phase] is a cell, O is Ar
This is the gas inlet. In the method shown in FIG. 4, Ar gas is introduced into a vacuum apparatus, and the surface of the substrate (1) is irradiated with an Ar ion beam using an ion gun (phase) (k). As a result, the surface of the substrate (1) can be cleaned without increasing the substrate temperature. However, due to the irradiation with the Ar ion beam, the surface of the substrate (1) is severely damaged by radiation, and the crystal lattice on the surface of the substrate (2) is significantly disturbed, resulting in the generation of many defects. As a result of this, the crystallinity of the thin film layer grown on the substrate surface is also significantly reduced, and the electrical properties are also deteriorated.

さらに、第5図に示すように、気相エピタキシャル成長
法などで一般に行なわれている成長直前における反応性
ガス(たとえばHCA’ガス)による基板表面の化学的
な気相エツチングに、MBE法に応用することも考えら
れる。第5図において、[相]は基板ホルダー、[相]
は基板、■、[相]はセルシャッター、■は■族原料、
@はセル、[有]はV族原料、[相]はセル、[相]は
反応性ガス導入口である。第5図の方法においては、第
3図に示す方法のように、基板温度?高温まで加熱する
必要はなく、さらに第4図に示す方法のように、加速さ
れんイオンビームによる照射損傷も起こさずに、基板表
面と清浄化することができる。しかしながら、このよう
な反応性ガスt1超高真空装置に導入することは超高真
空装置を構成する素材や排気系素材をもエツチングする
ことになり、さらに、ヒーター線のように、高温に加熱
される細線とも反応する。
Furthermore, as shown in FIG. 5, chemical vapor phase etching of the substrate surface using a reactive gas (such as HCA' gas) immediately before growth, which is commonly performed in vapor phase epitaxial growth, can be applied to MBE. It is also possible. In Figure 5, [phase] is the substrate holder, [phase]
is the substrate, ■, [phase] is the cell shutter, ■ is the ■ group raw material,
@ indicates a cell, [Yes] indicates a group V raw material, [phase] indicates a cell, and [phase] indicates a reactive gas inlet. In the method shown in FIG. 5, as in the method shown in FIG. It is not necessary to heat the substrate to a high temperature, and furthermore, as in the method shown in FIG. 4, the substrate surface can be cleaned without causing irradiation damage by an unaccelerated ion beam. However, introducing such reactive gas t1 into the ultra-high vacuum equipment will also etch the materials that make up the ultra-high vacuum equipment and the exhaust system materials. It also reacts with fine lines.

このことは、超高真空装置を安定稼動させる上で著しい
問題である。また、基板表面以外の装置構成材料がエツ
チングされるということは、エツチングされて新たに不
純物ガスが発生することを意味し、引きつづいて成長さ
れるI−V化合物半導体薄膜の電気特性を劣化させる原
因にもなる。
This is a significant problem in stable operation of ultra-high vacuum equipment. Furthermore, etching of device constituent materials other than the substrate surface means that new impurity gas is generated due to etching, which deteriorates the electrical characteristics of the subsequently grown I-V compound semiconductor thin film. It can also be a cause.

(問題点分解法するための手段) そこで、本発明者は、上記の問題点を解決する目的で、
化合物半導体基板または化合物半導体下地膜表面のオー
ジェ電子分光分析全行ない、種々研究を行なった。その
結果、以下に示す現象を発見した。すなわち、たとえば
第6図に示すようにV族元素であるAs分子全照射しな
がら400°Cで1時間の加熱クリーニングに行なった
後のInP基板表面には、炭素Cや酸素Oの不純物原子
が残留している。しかしながら、As分子を照射しなが
ら400°Cで1時間の加熱クリーニングと行ない加熱
クリーニング終了間際にsb分子線分約2秒−〇− 間照射することにより、第7図に示すように、炭素Cや
酸素Oの不純物原子に起因したオージェ電子ピークが完
全に消失している。同様の現象は、400°Cで10分
間の加熱クリーニングを行なった後、加熱クリーニング
終了間際にSb分子線を照射した場合にも見られた。さ
らに、Sb分子線を照射する場合には、照射するSb原
子の個数が、化合物半導体基板または化合物半導体下地
膜上で1原子層全形成するのに要する個数よりも少ない
ととが必要である。なぜならば、1原子層を形成するの
に要する個数以上の■族原子を照射すると酸素Oや炭素
Cなどの不純物原子を除去した後、著しい余剰Sb原子
が残留し、化合物半導体基板または化合物半導体下地膜
表面の組成や原子間隔を変えることになり、その後ひき
つづいて行なわれる化合物半導体薄膜の成長に悪影響を
与える。
(Means for problem decomposition method) Therefore, in order to solve the above problems, the present inventors
Various studies were carried out including Auger electron spectroscopic analysis of the surface of compound semiconductor substrates or compound semiconductor underlayers. As a result, we discovered the following phenomena. That is, for example, as shown in Figure 6, impurity atoms such as carbon C and oxygen O are present on the InP substrate surface after heating cleaning at 400°C for 1 hour while irradiating all As molecules, which are group V elements. remains. However, by performing heating cleaning at 400°C for 1 hour while irradiating As molecules, and irradiating the sb molecular beam for about 2 seconds just before the end of the heating cleaning, carbon C Auger electron peaks caused by impurity atoms such as oxygen and O have completely disappeared. A similar phenomenon was observed when heating cleaning was performed at 400° C. for 10 minutes and then Sb molecular beam was irradiated just before the end of heating cleaning. Furthermore, when irradiating with an Sb molecular beam, it is necessary that the number of Sb atoms to be irradiated is smaller than the number required to form an entire one atomic layer on the compound semiconductor substrate or the compound semiconductor base film. This is because when irradiation with more group III atoms than is required to form one atomic layer results in the removal of impurity atoms such as oxygen O and carbon C, a significant surplus of Sb atoms remains. This changes the composition and atomic spacing of the surface of the ground film, which adversely affects the subsequent growth of the compound semiconductor thin film.

第7図においては、Sb分子線kx 1原子層を形成す
るのに必要な原子の個数の約a/l Oだけ供給した場
合のオージェ電子分光のスペクトルを示したものである
が、酸素や炭素Cのピークが消失しているにもかかわら
ず、sbのピークは現れておらず、このことは、余剰の
sb原子’tInP基板表面に残留させることなく、ク
リ−リングが行なわれていることに意味する。このよう
なSb分子線を照射することによる表面のクリーニング
効果は、基板温度が300〜500°Cにおいても見ら
れた。
Figure 7 shows the spectrum of Auger electron spectroscopy when approximately a/l O, the number of atoms required to form one atomic layer of Sb molecular beam kx, is supplied. Although the C peak has disappeared, the sb peak has not appeared, indicating that cleaning is being performed without leaving excess sb atoms on the InP substrate surface. means. The surface cleaning effect of irradiation with Sb molecular beams was observed even when the substrate temperature was 300 to 500°C.

このように、sb分子線全、■原子層を構成する化合物
半導体基板または化合物半導体下地膜表面上の不純物原
子と除去することができ、また、加速されたイオンビー
ムとは異なり、中性原子であるため表面に照射損傷2与
えることもない。さらに、反応性ガスのように、真空装
置そのものをエツチングすることもない。
In this way, all of the sb molecular beams can be removed from the impurity atoms on the surface of the compound semiconductor substrate or compound semiconductor base film constituting the atomic layer, and unlike accelerated ion beams, neutral atoms can be removed. Therefore, there is no irradiation damage 2 to the surface. Furthermore, unlike reactive gases, it does not etch the vacuum device itself.

(実施例) 第1図は、本発明による薄膜成長方法の一実施例を説明
するための図である。第1図において、[相]は基板ホ
ルダー、[相]はInP基板、[相]はsb原料[相]
はセル、■はセルシャッター、■は■族原料のIn% 
@はセル、0はセルシャッター、[相]ハGa、[相]
はセル、OはAs原料、■はセルである。第1図の実施
例においては、As4分子線を用いて基板近傍の真空度
f 1xlO’Torr〜1xlO’Torr(バック
グラウンドの真空度は約5 x 10 ”Torr)に
保持しながら、InP基板[相]の温度を約400 ’
Qに10分間加熱した後、さらにSb分子線を約セルシ
ャッター[有]k開くことによって、連続してInP基
板[相]の上#CI n O,53Ga O,47As
薄膜を約Q、 211m成長させた。半絶縁性InP基
板上のI n o、5a Ga O,47As薄膜につ
いて本実施例を用いて0.2μm形成した場合には、そ
の室温での電子移動度は、11oooa!/V−3ec
であり、キャリア濃度はlXl015an−8であった
のに対し、1xlO’TorrのAs 4分子線に照射
しながら、400°Cで10分間の加熱クリーニングを
行なったのみで、0.2μm形成しん場合には、その室
温での電子移動度は、8000 crl/V−secで
あり、キャリア濃度は2×IO”QT+−8であっに0
すなわち、本実施例によると、不純物キャリア濃度に1
けな低くすることができ、電子移動度も増大し、I n
 O,53Ga O,47As薄膜の電気特性を向上さ
せることができる。
(Example) FIG. 1 is a diagram for explaining an example of the thin film growing method according to the present invention. In Figure 1, [phase] is the substrate holder, [phase] is the InP substrate, [phase] is the sb raw material [phase]
indicates the cell, ■ indicates the cell shutter, and ■ indicates the In% of the ■ group raw material.
@ is cell, 0 is cell shutter, [phase] Ga, [phase]
indicates a cell, O indicates an As raw material, and ■ indicates a cell. In the embodiment shown in FIG. 1, an InP substrate [ temperature of about 400'
After heating for 10 minutes at Q, the Sb molecular beam was further heated on the InP substrate [phase] by opening the cell shutter [with] about #CI n O, 53Ga O, 47As.
The thin film was grown to approximately Q, 211 m. When an Ino, 5a GaO, 47As thin film on a semi-insulating InP substrate is formed to a thickness of 0.2 μm using this example, its electron mobility at room temperature is 11oooa! /V-3ec
, and the carrier concentration was lXl015an-8, but when heating cleaning was performed at 400°C for 10 minutes while irradiating with the As 4 molecular beam at 1xlO'Torr, no particles of 0.2 μm were formed. The electron mobility at room temperature is 8000 crl/V-sec, and the carrier concentration is 2×IO”QT+-8, which is 0.
That is, according to this example, the impurity carrier concentration is
can be significantly lowered, electron mobility also increases, and I n
The electrical properties of the O,53Ga O,47As thin film can be improved.

さらに、同様の効果は、基板温度が300〜500℃の
範囲においても認められ、I n oss Ga O,
47AS薄膜の電気特性が向上した。
Furthermore, similar effects are observed even when the substrate temperature is in the range of 300 to 500°C, and Inoss GaO,
The electrical properties of the 47AS thin film were improved.

(発明の効果) 以上のようにこの発明は、化合物半導体基板または化合
物半導体下地膜上に、化合物半導体薄膜を分子線エピタ
キシャル成長させる直前に、電気的に中性なSb分子線
を、Sb原子が1原子面を形成するよりも少ない個数だ
け照射することにより基板または下地膜の温度を低温に
保持したままで照射による損傷と与えることなく、基板
または下地膜表面上の残留不純物を除去することができ
るという特有の効果を奏する。
(Effects of the Invention) As described above, the present invention allows electrically neutral Sb molecular beams to be grown immediately before molecular beam epitaxial growth of a compound semiconductor thin film on a compound semiconductor substrate or a compound semiconductor base film. By irradiating a smaller number of particles than the number needed to form an atomic plane, residual impurities on the surface of the substrate or underlying film can be removed without causing damage due to irradiation while maintaining the temperature of the substrate or underlying film at a low temperature. It has a unique effect.

この効果は、基板または下地膜の温度が300°C以上
においても観察されん。
This effect is not observed even when the temperature of the substrate or underlying film is 300°C or higher.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明による薄膜成長方法全説明するための
図、第2図は、高電子移動度)・ランジスタの断面概略
図、第8図は、従来の加熱クリーニング法を説明するた
めの図、第4図は、従来のイオンスパッタクリーニング
法を説明するための図、第5図は、反応性ガスを用いた
クリーニング法ヲ説明するための図、第6図は、低温で
の加熱クリーニングと行なった後のInP基板表面のオ
ージェ電子分光分析結果と示す図、第7図は、低温での
加熱クリーニングを行なった後、さらにsb分子線を照
射した後の、InP基板表面のオージェ電子分光分析結
果を示す図である。 ■、■、■、[相]基板ホルダ ■、■、[相]、[相]化合物半導体基板または化合物
半導体下地膜■、■、^、■、[有]セルシャッター■
、[相]、■  ■族原料 ■、[相]、[相]  ■族セル ■、[相]、[有]  V族原料 ■、[相]、[相]  V族七ル ■     イオンガン ■ Ar ガス導入口 [相] 反応性ガス導入口 [相] 半絶縁性GaAs基板 [相] GaAsバッファ層 ■ GaAsチャンネル層 @ 電子供給層 @ 高濃度のP型不純物を含有し、大きな電子親和力を
有する半導体よりなる層 ■ ゲート電極 [有] 合金化領域 [相] ソース電極およびドレイン電極■ 二次電子蓄
積層 [相] In 原料 [相] In セル [相] Ga 原料 [相] Ga セル [相] As原料 [相] As セル [相] sb原料 第1 図 集2N 隼3回 悴4靭
Figure 1 is a diagram for explaining the entire thin film growth method according to the present invention, Figure 2 is a schematic cross-sectional diagram of a transistor with high electron mobility, and Figure 8 is a diagram for explaining the conventional heating cleaning method. Figure 4 is a diagram for explaining a conventional ion sputter cleaning method, Figure 5 is a diagram for explaining a cleaning method using a reactive gas, and Figure 6 is a diagram for explaining a cleaning method using a reactive gas. Figure 7 shows the results of Auger electron spectroscopy on the surface of an InP substrate after thermal cleaning at a low temperature and further irradiation with an sb molecular beam. It is a figure showing an analysis result. ■, ■, ■, [Phase] Substrate holder ■, ■, [Phase], [Phase] Compound semiconductor substrate or compound semiconductor base film ■, ■, ^, ■, [With] Cell shutter ■
, [Phase], ■ ■ Group raw material ■, [Phase], [Phase] ■ Group cell ■, [Phase], [Yes] Group V raw material ■, [Phase], [Phase] Group V seven group ■ Ion gun ■ Ar Gas inlet [phase] Reactive gas inlet [phase] Semi-insulating GaAs substrate [phase] GaAs buffer layer ■ GaAs channel layer @ Electron supply layer @ Semiconductor containing a high concentration of P-type impurities and having a large electron affinity ■ Gate electrode [with] Alloyed region [phase] Source electrode and drain electrode ■ Secondary electron storage layer [phase] In Raw material [phase] In Cell [phase] Ga Raw material [phase] Ga Cell [phase] As Raw material [phase] As Cell [phase] sb raw material No. 1 Diagram collection 2N Hayabusa 3 times 4 times

Claims (1)

【特許請求の範囲】[Claims] (1)化合物半導体基板または化合物半導体下地膜上に
、III族元素とV族元素よりなる化合物半導体薄膜を成
長する分子線エピタキシャル成長法において、成長を行
なう前に、アンチモン(Sb)分子線を、化合物半導体
基板または化合物半導体下地膜に照射することによつて
、化合物半導体基板または化合物半導体下地膜表面上の
不純物原子を除去した後、III族元素とV族元素よりな
る化合物半導体薄膜を成長させることを特徴とする薄膜
成長方法。
(1) In the molecular beam epitaxial growth method for growing a compound semiconductor thin film made of group III elements and group V elements on a compound semiconductor substrate or a compound semiconductor base film, an antimony (Sb) molecular beam is After removing impurity atoms on the surface of the compound semiconductor substrate or compound semiconductor base film by irradiating the semiconductor substrate or the compound semiconductor base film, a compound semiconductor thin film consisting of group III elements and group V elements is grown. Characteristic thin film growth method.
JP20087285A 1985-09-09 1985-09-10 Thin film growth method Pending JPS6260218A (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP20087285A JPS6260218A (en) 1985-09-10 1985-09-10 Thin film growth method
AU62456/86A AU590327B2 (en) 1985-09-09 1986-09-08 Method of growth of thin film layer for use in a composite semiconductor
DE8686112487T DE3688028T2 (en) 1985-09-09 1986-09-09 METHOD FOR THE GROWTH OF A THIN LAYER FOR A COMPOSED SEMICONDUCTOR.
EP86112487A EP0215436B1 (en) 1985-09-09 1986-09-09 Method of growth of thin film layer for use in a composite semiconductor
CN86106177.2A CN1004455B (en) 1985-09-09 1986-09-09 Method of growth of thin film layer for use in a composite semiconductor
EP92107691A EP0499294A1 (en) 1985-09-09 1986-09-09 Method of molecular epitaxial growth of single crystal layers of compound semiconductors
KR1019860007530A KR870003552A (en) 1985-09-09 1986-09-09 Method of manufacturing compound semiconductor device
CN88108172A CN1009885B (en) 1985-09-09 1988-11-23 Method of growth of thin film layer for use in composite semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20087285A JPS6260218A (en) 1985-09-10 1985-09-10 Thin film growth method

Publications (1)

Publication Number Publication Date
JPS6260218A true JPS6260218A (en) 1987-03-16

Family

ID=16431635

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20087285A Pending JPS6260218A (en) 1985-09-09 1985-09-10 Thin film growth method

Country Status (1)

Country Link
JP (1) JPS6260218A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6365969B1 (en) 1999-03-25 2002-04-02 Sumitomo Electric Industries, Ltd. Ohmic electrode, method of manufacturing the same and semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54125967A (en) * 1978-03-23 1979-09-29 Matsushita Electric Ind Co Ltd Crystal growth method
JPS6127621A (en) * 1984-07-18 1986-02-07 Fujitsu Ltd Crystal growth method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54125967A (en) * 1978-03-23 1979-09-29 Matsushita Electric Ind Co Ltd Crystal growth method
JPS6127621A (en) * 1984-07-18 1986-02-07 Fujitsu Ltd Crystal growth method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6365969B1 (en) 1999-03-25 2002-04-02 Sumitomo Electric Industries, Ltd. Ohmic electrode, method of manufacturing the same and semiconductor device

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