JPS6259815B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address generation circuit externally attached to a microprocessor to provide an address to a memory or an input/output device (herein simply referred to as memory) connected to the microprocessor. More specifically, the present invention relates to an address generation circuit having a function of checking the operation of the address generation circuit.

For example, Intel's 8085 microprocessor has a 16-bit address bus, and the lower 8-bit bus ( _AD0-7 ) serves as a dual-purpose address and data bus. That is, the lower 8 bits are configured to function as an address bus in the first clock cycle of the machine state, and to function as a data bus in the second and third clock cycles of the machine state. It is necessary to separately provide an address bus (16 bits) and a data bus (8 bits) to the memory, so an address control circuit 2 as shown in Figure 1 has traditionally been added to the microprocessor 1. ing. This circuit latches the address output from the lower 8 bits AD _{0 to 7} of the microprocessor 1 to the address latch 3 every time ALE (Address Latch Enable) is output, and transfers the output to the address output from the 8 bits AD _{8 to 15} mentioned above. The addresses are combined to form a 16-bit (AD _{0 to 15} ) address bus and applied to the memory 7, and when AD _{0 to 7} are used as a data bus, the data bus bidirectional buffer 4 is activated and the data bus is I am trying to configure it. By the way, in order to check whether the address control circuit 2 is operating normally, a circuit for sequentially incrementing the address is added to the address control circuit 2. That is, it includes an instruction generation circuit 5 for forcibly generating a one-word instruction such as adding 1 to an address, and a switch circuit 6 for selectively activating this instruction generation circuit 5 and the bidirectional buffer 4. A circuit is added. The check circuit 6 is connected to the C contact side and the command generation circuit 5 is activated.
A read signal ( ) is issued from the microprocessor 1 (that is, the CPU of the microprocessor 1 fetches the instruction). Each time , the instruction generation circuit 5 outputs a one-word instruction that increments the address by 1. As a result, the CPU increments the program counter (PC) by 1 only through internal processing, and the result is output to addresses AD 0 to AD ₇ and given to the memory.

By sequentially incrementing the address in this manner, it is possible to check the operation of the address control circuit 2 by confirming that the incremented address is also given to the memory.

However, the circuit for generating a one-word instruction generates 8-bit data;
The disadvantage is that reliability during normal operation is reduced because the number of parts is large and a large number of bits are connected to the data bus.

The present invention solves these drawbacks,
The purpose is to provide an address generation circuit which has a small number of parts, has a small component mounting area, and has a small number of bits to control data buses _{AD0 to AD7} , which is a circuit that increments an address by 1.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 is a block diagram showing an embodiment of the address generation circuit according to the present invention. 2 differs from FIG. 1 in the gate 21 and pull-up resistor group 23. In FIG. That is, the signal from the microprocessor 1 and the contact signal from the switch circuit 6 are input to the gate 21, and the output of the gate 21 is led to the data bus AD7 via the output switch ₂₂ . The pull-up resistor group 23 is composed of eight resistors, and pulls up each of the data buses _{AD0 to AD7} to the +5V power supply via the resistors.

The operation in such a configuration will be explained next.

(1) During normal operation Turn off the output switch 22 and turn on the switch circuit 6 to the D contact side. As a result, the data bus bidirectional buffer (usually a three-state buffer) 4 becomes active, while the gate 21 becomes inactive. Therefore, the microprocessor 1 can sequentially fetch instructions from the memory 7 via the buffer 4.

(2) When checking the address generation circuit Turn on the output switch 22 and close the switch circuit 6 to the C contact side. As a result, the buffer 4 becomes inactive and the gate 21 becomes active. On the other hand, data buses AD _{0 to AD 7} are pulled up to +5V via pull-up resistors 23. Every time a pulse is issued by the microprocessor 1 (that is, the CPU fetches an instruction), AD ₇ goes to the "LOW" level via the gate 21.

When fetching instructions, the CPU always fetches instructions with a pattern of "01111111". By specifying that this instruction is an instruction whose execution is completed only by the internal processing of the CPU, the program counter is incremented by 1 every time an instruction is fetched, and as a result, the address bus (address where the instruction is fetched) is added.
will be +1. By sequentially incrementing the address in this way and checking the address given to the memory 7, the operation of the address generation circuit can be checked.

In the example, we used Intel's 8085 microprocessor as an example.
Similar control is possible even when using other microprocessors. Although the gate 21 is generally constructed of a three-state buffer like the buffer 4, it can also be an open collector type buffer. Note that if the gate 21 is a three-state buffer, the output switch 22 can be omitted. Furthermore, the bit to be set to "LOW" in the output of the gate 21 is not limited to _AD7 , but other bits may be used.

As described above, according to the present invention, the operation of the address generation circuit can be checked with a simple configuration. That is, the conventional 8-bit configuration instruction generation circuit can be replaced with a 1-bit gate, and the number of components and mounting area can be reduced. Although the component mounting area increases by the amount of the pull-up resistor group, it still decreases as a whole. Furthermore, since the data bus is controlled by one bit, reliability during normal operation is excellent.
Furthermore, even when disconnecting the gate from the bus, a 1-bit switch is sufficient, which is much simpler than the conventional system, which requires 8 bits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional address control circuit, and FIG. 2 is a block diagram showing an embodiment of the address control circuit according to the present invention. 1... Microprocessor, 3... Address latch, 4... Data bus bidirectional buffer, 6...
Switch circuit, 7...Memory, 21...Gate,
23...Pull-up resistance group.

Claims (1)

[Claims] 1. In an address generation circuit that gives an address output from a microprocessor to a memory, and connects the memory's data bus to the microprocessor's data bus via a data bus bidirectional buffer during data transfer, A group of pull-up resistors that pull up the data bus between the processor and the data bus bidirectional buffer, and a switch circuit that makes the data bus bidirectional buffer inactive and transfers data every time a read signal is issued from the microprocessor. A driving means consisting of a gate that drives one bit in the data bus to "LOW" and a switch connected to this gate is provided, and when an operation check is performed, a command that causes one bit in the data bus to become "LOW" is sent to the microprocessor. 1. An address generation circuit characterized in that an operation check is performed by giving an address incremented and output from a microprocessor to a memory.