JPS5924333A - Address generating circuit - Google Patents

Abstract

PURPOSE:To decrease the number of parts and to simplify the constitution of the titled circuit and improving the circuit reliability, by giving an instruction to turn 1-bit to LOW in a data bus to a microprocessor then supplying the address outputted incrementally from the processor to a memory to perform a working check. CONSTITUTION:In a normal working mode, an output switch 22 is turned off, and a switch circuit 6 is supplied to the side of a contact D. Thus a data bus bidirectional buffer 4 and a gate 21 are made active and inactive, respectively. Therefore, a microprocessor 1 checks successively the instructions given from a memory 7 via the buffer 4. When an address generating circuit is checked, the switch 22 is turned on with the circuit 6 applied to the side C. Thus the buffer 4 and the gate 21 are made inactive and active, respectively. Then a data bus AD7 is set at level L via the gate 21 every time a -RD bus is delivered from the processor 1, and the address bus is added by +1 to increment the addresses successively.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address generation circuit externally attached to a microprocessor in order to give an address to a memory connected to the microprocessor. More specifically, the present invention relates to an address generation circuit having a function of checking the operation of the address generation circuit.

For example, Intel's 8085 MicroPro has a 16-bit address bus, and the lower eight bits of the
The − bus (ΔD o to 7) is a dual-purpose address and data bus. That is, the lower (1'78) bits are configured to be an address bus in the first clock cycle of the machine data, and a data bus in the second and 33rd clock cycles. For this purpose, it is necessary to provide an address bus (16 bits) and a data bus (8 bits) separately, and therefore an address control circuit 2 as shown in FIG. 1 has been added to the microprocessor 1 and used. This circuit converts the addresses output from the lower 8 bits AI) o to 7 of the microprocessor 1 into 8 LEs (Address 1-atch).
Every time [nable) is output, it is latched into the address latch 3, and its output is combined with the upper 8 bits ADs to I5 address to form a 16-bit (ADo=s) address bus and given to the memory 7, and △ When Do to 7 are used as a data bus, the data bus bidirectional buffer 4 is activated to form a data bus. By the way, in order to check whether the address control circuit 2 is operating normally, a circuit is added to the address control circuit 2 to sequentially increment the address. That is, an instruction generation circuit 5 that forcibly generates a one-book instruction such as adding +1 to an address, this instruction generation circuit 5, and a bidirectional buffer 4.
A circuit is added with a switch circuit 6 for selectively activating the. At the time of checking, the switch circuit 6 is connected to the C contact side, the command generation circuit 5 is activated, and the read signal (RD) is sent from the micro 10 retsuri 1.
(The CPU of the hit microprocessor 1 fetches the instruction (Fetch)).

Every time RD occurs, the instruction generation circuit 5 outputs an address of -1-1! A one-word command is output. To this, C
I) U is a program counter (+') for internal processing only.
C> is-! 1, and the result is address ADo”・7
It is output to the media and given to the media.

J
:The operation of the address control circuit 2 is checked by confirming that the address to be incremented is also given to the re-memory.

(However, the circuit for generating a one-word instruction is 8
This system avoids data transmission and transmission, has a large number of parts, and has a drawback that reliability during normal operation is low because a large number of parts are connected to the data bus.

The purpose of the present invention is to eliminate such drawbacks.
An object of the present invention is to provide an address generation circuit that has a smaller number of bits to control than those of the present invention.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 is a block diagram showing an embodiment of the address generation circuit according to the present invention. The difference between FIG. 2 and FIG. 1 is the gate 21 and pull-up resistor group 23.

That is, the RD signal of the microprocessor 1 and the C contact signal of the switch circuit 6 are input to the gate 21.
The output of is led to data bus ΔD7 via output switch 22. The pull-up resistor 8Y23 is composed of eight resistors, and pulls up each of the data buses ΔD○ to 7 to the +5V power supply via this resistor.

The operation in such a configuration will be explained next.

(1) During normal operation, turn off the output switch 22 and turn on the switch circuit 6 to the D contact side. This allows data bus bidirectional buffers (usually 3-state buffers)
4 goes into the aqua-live state, and the -h gate 21 goes into the in-a-kive state. Therefore, the microphone unit 1 can sequentially fetch instructions from the memory 7 via the buffer 4.

(2) When checking the address generation circuit, turn on the output switch 22 and set the switch circuit 6 to the C contact side. This causes buffer 4
is inactive, and goo 1 to 21 are in active state. On the other hand, 7-tabas ADo to 7 are in the pull-up resistor 23
It is pulled up to -5V via . Microbe D t = As soon as the RD pulse is emitted from tree 1, C
Every time the PU issues an instruction), Δ1]7 becomes the LOW level through the gate 21.

CI) Always “”01111 when fetching an instruction
111'' pattern. By specifying that this instruction is an instruction whose execution is completed only by the internal processing of the CP LJ, the program counter is incremented by 1 each time an instruction is fetched, and as a result, the address The bus (address for fetching instructions) will be incremented by 1. By incrementing the address sequentially in this way and checking the address given to the memory 7, the operation of the address generation circuit can be checked.

Although the embodiment has been described using the Intel 8085 microprocessor as an example, the same control can be achieved using the Haku microprocessor 1y. Although the gate 21 is generally configured as a 3-state buffer like the buffer 4, it can also be referred to as an open collector type buffer. Note that if the gate 21 is a three-state buffer, the output switch 22 can be omitted. Further, the bit to be set to ``LOW'' at the output of the gate 21 is not limited to AD7, but may be other bits.

As described above, according to the present invention, the operation of the address generation circuit can be checked with a simple configuration. That is,
The conventional instruction generation circuit having the ε3 pit configuration can be replaced with a 1-bit bit, and the number of components and mounting area can be reduced. Although the component mounting area increases by the amount of the Norara 1 resistor group, it still decreases overall. In addition, since the data bus is controlled by 1 bit C, it has excellent reliability during normal operation (
There is. Furthermore, if Goo1- is separated from the bus, C・ra1
A one-bit switch is sufficient, making it much simpler than the conventional one, which requires 8 bits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional address system rJ11 circuit, and FIG. 2 is a block diagram showing an embodiment of an address control circuit according to the present invention. 1... Microprocessor 33... Address latch 4... Data bus bidirectional button 1 6... Switch circuit 7... Memory 21... Gate 23... Pull-up resistor BY source 1 figure

Claims (1)

[Claims] Microbe Ot? The microprocessor and the data bus are connected to each other in an address generation circuit that gives the address output from the connector to the memory and connects the memory data bus to the microprocessor's data bus via a data bus bidirectional buffer during data transfer. a group of pull-up resistors that pull up the data bus between the bidirectional buffer 1;
A means is provided for inactivating the data bus bidirectional buffer and driving one bit in the data bus LOW every time a read signal is issued from the microprocessor. No. 1
An address generation circuit characterized in that an operation check is performed by giving a command to a microprocessor that causes a bit to be 10 W, and giving an address incremented and output from the microprocessor to a memory. .