JPH0553868A - Debugging device - Google Patents

Abstract

PURPOSE:To debug a program at a host computer while running the program on a target computer with simple hardware configuration. CONSTITUTION:A halt control circuit 24 detects that a target computer 10 executes a specified instruction, the target computer is turned to a halt state, an interruption request signal is supplied to a host computer 12, and the host computer 12 accesses the register of the target computer 10. In this case, buffer gates 20D and 20A are automatically turned to a conducted state by an address decoder 12, the halt control circuit 24 detects that the host computer 12 executes the other specified instruction, and the target computer 10 is turned to an operated state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a computer (DSP).
And an image processor, etc.) for debugging a program.

[0002]

2. Description of the Related Art In the case where a plurality of target computer programs are debugged in parallel by one host computer, or when the storage area for loading the debug program on the target computer is insufficient,
The method of emulating the program of the target computer by the host computer can be applied. However, not all input / output devices of the target computer can be emulated.

Therefore, debugging is performed by connecting the host computer and the target computer and operating the target computer by the host computer.

[0004]

However, since the host computer and the target computer exchange data according to a certain sequence so as not to cause a bus collision, a complicated hardware configuration is required.

In view of the above problems, an object of the present invention is to provide a debugging device having a simple hardware configuration, which allows a program to run on a target computer and to debug the program on a host computer. is there.

[0006]

A debug device according to the present invention will be described with reference to the reference numerals of corresponding constituent elements in the embodiments.

This debugging device is for debugging the program of the target computer 10 by the host computer 12, and the host computer 12
To the first signal from the host computer 12 and the buffer gates 20D and 20A for electrically connecting / disconnecting the data bus 16D and the address bus 16A1 of the target computer 10 and the data bus 18D and the address bus 18A of the target computer 10 according to the control signal. In response, the gate control circuit for supplying the control signal to the buffer gates 20D and 20A, for example, the address decoder 22 and the second signal from the target computer 10 side, stop the operation of the target computer 10 with respect to the target computer 10. And a halt control circuit for notifying the host computer 12 that the operation of the target computer 10 is stopped by, for example, an interrupt request signal IRQ, and canceling the operation stop in response to a third signal from the host computer 12 side. And a 4.

In the above structure, a specific instruction is written in a word for setting a breakpoint before executing a program to be debugged in the program RAM of the target computer 10.

When the target computer 10 executes this specific command, the halt signal HALT is supplied from the halt control circuit 24 to the MPU of the target computer 10 to bring the MPU into a stopped state and to send a signal notifying that the target computer has stopped operating. It is supplied from the halt control circuit 24 to the MPU of the host computer 12.

In response to this, the host computer 12 reads the contents of the registers and the like in the MPU of the target computer 10.

Next, the host computer 12 executes another specific command. As a result, the halt state of the MPU of the target computer 10 is released. Further, the buffer gates 20D and 20A are turned off. The target computer 10 executes the next program section and the above process is repeated.

According to the present invention, a program is run on a target computer by a simple hardware configuration, that is, a buffer gate, a gate control circuit, and a halt control circuit having a simple configuration, and the host computer executes the program. Can be debugged. The hardware configuration is simplified because the target computer 10 stops its operation and causes the host computer 12 to use the bus 18.

In the first aspect of the present invention, the first signal is
This is data on the address bus 16A2 of the host computer 12.

In this configuration, the buffer gates 20D and 20A are automatically turned on when an access instruction to the target computer 10 is executed, so that the debugging process is simplified.

In the second aspect of the present invention, the second signal and the third signal are data on the buses 18D and 18A on the target computer 10 side.

In the case of this configuration, the halt control circuit 24 has only to process based on the data on the bus of the target computer 10, so that the configuration of the halt control circuit 24 is generally simple.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of the debug device.

A debug device 14 is provided between the target computer 10 and the host computer 12 in order to run a program on the target computer 10 and debug the program on the host computer 12. The target computer 10 is, for example, model MB86232 M
A host computer 12 equipped with a PU (DSP)
Comprises, for example, an MPU of model 68030.

The bus 16 of the host computer 12 is, for example, a VME bus, and includes a data bus 16D including data lines D31 to D0 and address lines A17 to A2.
Address bus 16A1 and address line A2
The address bus 16A2 composed of 3 to A18 and the control bus are for connection with 14. Similarly, the bus 18 of the target computer 10 may be, for example, a model M
External bus of B86232, data line MD31
To MD0, the data bus 18D, address lines EA15 to EA0, and the control bus are connected to each other.

The data bus 16D and the data bus 18D are connected via a buffer gate 20D, and the address bus 16A1 and the address bus 18A are connected via a buffer gate 20A. Further, the address decoder 22 makes the buffer gates 20D and 20A conductive / interruptive based on the data on the address bus 16A2.

For example, as shown in FIG. 2, the buffer gate 2
Each of 0D and 20A has a simple structure in which an n-channel MOS transistor is connected between both lines, and the address decoder 22 is composed of a simple AND gate.

In FIG. 1, the data line MD0 of the address bus 18A and the data bus 18D is connected to the input terminal of the halt control circuit 24. The halt control circuit 24, for example, stores 16 bits of data on the address bus 18A.
When it is a decimal number "FFFF" and the data on the data line MD0 is "1", the halt signal HALT and the interrupt request signal IRQ as shown in FIG. 4 are output.
The halt signal HALT is supplied to the MPU of the target computer 10 via the control bus of the bus 18. Further, the interrupt request signal IRQ is sent to the bus 16
It is supplied to the MPU of the host computer 12 via the control bus. The halt control circuit 24 also determines that the data on the address bus 18A is hexadecimal'FFF.
When it is F'and the data line MD0 is '0', the halt signal HALT is set to the low level as shown in FIG.

Next, the operation of this embodiment constructed as described above will be explained.

In the program RAM of the target computer 10, before executing the program to be debugged, as shown in FIG. 3, an instruction to set, for example, the 0th bit of the address "FFFF" in the word for setting the breakpoint. BSET 0 and FFFF are written in advance. In FIG. 3, for example, the bit set instruction is executed after executing each of the program sections 1, 2 and 3.

The target computer 10 first executes the program section 1. Next, as shown in FIG. 4A, when this bit set instruction is executed, the halt control circuit 24 causes the MPU of the target computer 10 to operate.
Is supplied with a halt signal HALT as shown in FIG. 4B, and this MPU is, for example, D of model MB86232.
Like SP, the execution of the program is stopped as soon as the currently executed instruction is completed, and the external access to the internal RAM and internal register is enabled. Immediately after this, the halt control circuit 24 supplies an interrupt request signal IRQ as shown in FIG. 4C to the MPU of the host computer 12. Host computer 12 interrupt request signal IRQ
The target computer 10 has already stopped operating at the time of reception, and the host computer 12 has
8 can be used. Therefore, a special hardware configuration for the host computer 12 to access the internal register of the target computer 10 is unnecessary.

In response to this, the host computer 12 responds to the target computer 1 as shown in FIG.
The contents of the register in the MPU of 0 are read out and stored in a predetermined area of the memory of the host computer 12. When the address decoder 22 is composed of an AND gate as shown in FIG.
23 to A18 are all set to "1", and the buffer gate 2
0D and 20A become conductive. That is, the buffer gates 20D and 20A become conductive only when the host computer 12 accesses the internal register of the target computer 10.

Next, the host computer 12 executes the instruction BRST 0,3FFFFF for resetting the 0th bit of the word of the address '3FFFFF' as shown in FIG. 4D, for example. As a result, the halt control circuit 24 has the configuration shown in FIG.
As shown in (B), the halt signal HALT is set to the low level, and the halt state of the MPU of the target computer 10 is released. The target computer 10 executes the next program section, and the above processing is repeated.

As described above, the host computer 12 can debug a program running on the target computer 10 by using the debug device 14 having a simple structure.

The present invention includes various modifications other than the above. For example, the configuration is such that a plurality of debug devices 14 are connected in parallel to the bus of one host computer 12, the target computer 10 is connected to each debug device, and the programs of the plurality of target computers are debugged sequentially or in parallel. May be. Further, the bit lengths of the data buses of the host computer 12 and the target computer 10 may be different from each other. Further, the target computer 10 may be in a halt state and the program RAM of the target computer 10 may be accessed from the host computer 12 to set a breakpoint on the target computer 10 on the host computer 12 side.

[0031]

As described above, the debug device according to the present invention has an excellent effect that the program can be run on the target computer and the host computer can debug the program with a simple hardware configuration. It greatly contributes to cost reduction.

According to the first aspect of the present invention, since the buffer gate is automatically turned on by simply executing the access instruction to the target computer, there is an effect that the debugging process is simplified.

According to the second aspect of the present invention, since the halt control circuit only needs to process based on the data on the bus on the target computer side, generally, the effect of simplifying the configuration of the halt control circuit is obtained. Play.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a debug device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a buffer gate and an address decoder in FIG.

FIG. 3 is an explanatory diagram of breakpoint setting.

FIG. 4 is an operation sequence diagram of the circuit of FIG.

[Explanation of symbols]

 14 Debugging device 16, 18 bus 16D, 18D Data bus 16A1, 16A2, 18A Address bus 20D, 20A Buffer gate HALT Halt signal IRQ Interrupt request signal

Claims (3)

[Claims] 1. A debug device for debugging a program of a target computer (10) by a host computer (12), the data bus (16D) and address bus (16A1) of the host computer and the data bus (18D) of the target computer. And a buffer gate (20D, 20A) that conducts / blocks between the address bus (18A) and the address bus (18A), respectively, and the control signal is supplied to the buffer gate according to a first signal from the host computer. Gate control circuit (2
2) and a second signal from the target computer side,
A third signal from the side of the host computer is notified to the target computer by stopping the operation of the target computer (HALT) and by notifying the host computer of the stop of the operation of the target computer (IRQ). And a halt control circuit (24) for canceling the operation stop according to the above. 2. The debug device according to claim 1, wherein the first signal is data on an address bus (16A2) of the host computer (12). 3. The second signal and the third signal are sent to the bus (18D, 1D) on the side of the target computer (10).
The debug device according to claim 1 or 2, which is data on 8A).