JPS6258594B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sensitivity adjustment method for a solid-state imaging device. It is known that solid-state imaging devices perform photoelectric conversion using an amorphous semiconductor layer instead of the conventional silicon (Si) single crystal substrate. This uses a conventional Si single crystal substrate for the signal readout section. Since the amorphous semiconductor layer is located on the signal readout section made of this Si single crystal substrate, it is called a two-story sensor and is distinguished from a conventional solid-state imaging device made only of a Si single crystal substrate. The present invention relates to a driving method for performing automatic sensitivity adjustment in this two-story sensor.

FIG. 1 is for explaining the automatic sensitivity adjustment method previously proposed by the present inventor. Here, an explanation will be given using a device using a CCD (Charge Coupled Device) in the reading section. For example, as shown in FIG. 1a, a first N ⁺ layer 2, which is a signal charge transfer section of a CCD, is connected to an amorphous semiconductor layer 3 by a metal electrode 4 on a p-type semiconductor substrate ^1.
There is layer 5. and the first N ⁺ layer 2 and the second
Adjacent to the N ⁺ layer 5 are p ⁺ layers 6-1 and 6-2 which are channel stoppers. Further, a transparent electrode 7 is provided on the amorphous semiconductor layer 3. The signal charges (electrons) photoelectrically converted in the amorphous ^{semiconductor} layer 3 are transferred to the first
Transfer it to the N ⁺ layer and read it. Here, on the first N ⁺ layer 2 there is a transfer electrode 9 of the CCD. Insulating films 10-1 and 10-2 made of oxide films are present around the read gate electrode 8 and transfer electrode 9. The voltage applied to this transparent electrode 7 is V _G , and the surface potential of the second N ⁺ layer 5 is V _N
shall be. The amorphous semiconductor layer 3 sandwiched between the metal electrode 4 and the transparent electrode 7 can be equivalently described as one diode. V _G and V _N are applied to both ends of this amorphous semiconductor layer 3 as shown in FIG. In FIG. 1a, V _N immediately after a voltage is applied to the read gate electrode 8 and signal charges are read out is assumed to be V _NO .

Here, the voltage V _G applied to the transparent electrode 7 is changed over time as shown in FIG. In other words, V _G is held at the V _NO for an arbitrary period that is continuous with the signal read period in an imaging operation in which one cycle consists of a signal read period for reading signal charges and an accumulation period for accumulating signal charges. , the voltage V _I is set lower than the V _NO for the remaining period. Automatic sensitivity adjustment is performed by changing this low voltage period T _I according to the amount of incident light. Here, V _I is a voltage at which the signal charges accumulated in the diode capacitance formed by the amorphous semiconductor layer 3 and the second N ⁺ layer in FIG. 1A do not overflow into the first N ⁺ layer 2 of the CCD. As explained above, during the _VNO holding period of the storage period, no voltage is applied to the diode made of the amorphous semiconductor layer 3, so no signal charge is stored. Then, signal voltage accumulation can be performed only during the low voltage V _I holding period. Furthermore, by setting V _G to a negative voltage during the signal charge readout period, the diode formed by the amorphous semiconductor layer 3 is reliably brought into a reverse bias state, and the signal charge is reliably transferred to the CCD.

As explained above, according to this method, automatic sensitivity adjustment can be easily performed by temporally changing the voltage applied to the transparent electrode.

However, even with this method, there are driving problems that need to be improved. That is, as described above, the voltage applied to the transparent electrode 7 following the signal readout period must be accurately set to the _VNO . The V _NO is the surface potential of the second N ⁺ layer 5 immediately after the signal charges are read out by applying a voltage to the readout gate electrode 8 as described above. More precisely, the voltage V _NO applied to this transparent electrode is such that signal charges generated in the amorphous semiconductor layer 3 are not accumulated and charges (electrons) are transferred from the second N ⁺ layer 5 to the first N ⁺ layer. This is an applied voltage that does not cause any overflow to 2. Therefore, this potential V _NO is not automatically and instantaneously determined, but is determined after an operation to approach this V _NO . Here, transparent electrode 7
If the voltage applied to V _NO is set to a lower level voltage than VNO, some problems will occur because signal charges can actually accumulate even though the amount of signal charge that can be accumulated during this low level voltage period is small. .
That is, when a solid-state imaging device using this method is used as a self-black camera, there is almost no practical problem, but when it is used, for example, in a color camera, a problem arises in the color reproducibility of a subject where the amount of signal is small. This is not a fatal drawback as it does not mean that the signal itself cannot be obtained, but the biggest problem is that when the voltage applied to the transparent electrode 7 is set to a high level voltage from the V _NO The problem is that the signal of the dark part of the image may not be obtained as an output.

This development will be explained using FIG. 2. FIG. 1a is a cross-sectional structural diagram of one cell portion of the solid-state imaging device shown in FIG. 1a. Figures b, c, d, and e are semiconductor substrates for explaining temporal changes in signal charge accumulation due to the drive voltage waveform when a voltage higher than V _NO is applied to the transparent electrode 7 in this cell structure. 1 is a potential distribution diagram on one surface.

b shows the potential distribution when a voltage higher than V _NO is applied to the transparent electrode 7 after the signal charge readout period. Here, what is indicated by the dotted line is the second
This is the potential of the N ⁺ layer 5 portion after the signal charge readout operation is completed, and its value is _VNO . Here, as described above, by applying a voltage higher than V _NO to the transparent electrode 7, the charges (electrons) in the second N ⁺ layer 5 flow out to the transparent electrode 7, and the second
The surface potential of the N ⁺ layer 5 is set to a higher level than the V _NO . During this high-level voltage holding period, the signal charges (electrons) generated in the amorphous semiconductor layer 3 flow to the transparent electrode 7 side, and no signal charges are accumulated. Next, when a voltage V _I for accumulating signal charges is applied to the transparent electrode 7, the signal charges are accumulated. During the holding period, this V _I is
Signal charges generated by light irradiation within the layer travel within the layer and reach the metal electrode 4, thereby lowering the potential of the second N ⁺ layer 5. Then, in order to read out signal charges, a voltage is applied to the readout gate electrode 8 to transfer the signal charges to the first N ⁺ layer 2 of the CCD, and the potential distribution is shown in FIG. Here, the surface potential of the semiconductor substrate 1 under the readout gate electrode 8 is V
Therefore, the signal charge 11 having a potential lower than the potential V _NO determined by the voltage applied to the readout gate electrode 8 is transferred to the first _N ⁺ layer 2 of the CCD; The signal charge 12 having the above potential is not transferred and remains in the second N ⁺ layer 5 as shown in FIG.

The present invention has been made in view of the above points.
That is, the present invention eliminates, for example, deterioration of color reproducibility in color development or signal of a dark part of an imaged object, which occurs because the voltage to be applied to the transparent electrode 7 is not applied accurately following the signal charge readout period described above. Prevent problems that do not appear in the output,
The present invention also aims to provide a solid-state imaging device that performs sensitivity adjustment.

An embodiment of the present invention will be described using FIG.

FIG. 1A is an explanatory diagram of a cross-sectional structure of one cell of a solid-state imaging device for explaining the present invention. ^What differs from ^FIG .
An overflow control electrode 14 for controlling the surface potential of the semiconductor substrate 1 between the N ⁺⁺ layer 13 and the N ⁺ layer 5 is provided. FIG. 1B shows the voltage waveforms of the voltage V _G applied to the transparent electrode 7, the voltage φ _OFG applied to the overflow control electrode 14, and the voltage φ _OFD applied to the overflow drain 13. As shown in this figure, in the storage period following the signal readout period, the transparent electrode 7 is maintained at a level higher than the V _NO for an arbitrary period of time. Then, in order to accumulate signal charges, the voltage V _I is held at a lower level than V _NO . At the beginning of the holding period of this V _I voltage, φ _O
By changing _FG from V _B to a high level voltage V _C and changing φ _OFD from V _D to a lower level voltage V _E , charges (electrons) are transferred from the overflow drain 13 to the second N ⁺ is injected into layer 5 to set the surface potential of this second N ⁺ layer 5 at a voltage V _C of φ _OFG . The voltage V _C applied to the overflow control electrode 14 has the same value as the high-level voltage applied to the readout gate electrode 8 in the figure a during the readout period, as shown in the figure c. In this way, the signal charges explained in ^FIG .
By applying a voltage that causes the voltage to remain and then injecting an insufficient amount of charge from the overflow drain 13, it is possible to prevent the above-mentioned problem in which the signal of the dark part of the imaged object does not appear as an output. Here, both the readout gate electrode 8 and the overflow control electrode 14 are under the semiconductor substrate 1, and because they are located very close to each other, the surface potentials of both with respect to the applied voltage are very close to each other. Problems caused by potential setting of the N ⁺ layer can be significantly improved.

This operation will be explained using FIG. 4. 3A shows a cross-sectional structure of one cell of the solid-state imaging device, which is the same as FIG. Figure b shows the transparent electrode 7 following the signal readout period.
The potential distribution is shown when a voltage V _A at a higher level than V _NO is applied to. In this case, some of the charges in the second N ⁺ layer 5 flow out to the transparent electrode side, and the second N ⁺
The potential of layer 5 is higher than said _VNO . Then, V _G is the voltage V _I for accumulating signal charge.
At the initial stage where φ _OFG was held at V _B to V _C
Figure c shows the potential distribution when φ _OFD is changed from V _D to V _E . Here, charges 16 are injected from the overflow drain 13 into the second N ⁺ layer 5, and then by returning φ _OFD to the original voltage V _D , the overflow control electrode 14 is injected as shown in d of the figure. The potential V _NO determined by the applied voltage V _C acts as a barrier, and since the charge 15 determined by this remains in the second N ⁺ layer 5, the potential of the second N ⁺ layer 5 is fixed at V _NO be done.
Then, as shown in FIG. 3e, the potential φ _OFG of the overflow control electrode returns to V _B , thereby accumulating signal charges. Thereby, the potential of the second N ⁺ layer 5 can be set more reliably than in the conventional method.

Another embodiment of the present invention will be described with reference to FIG. This provides a more desirable method than the one method of the present invention explained using FIGS. 3 and 4. That is, according to the method shown in FIGS. 3 and 4, the voltages applied to two adjacent electrodes, the overflow control electrode 14 and the readout gate electrode 8, are made the same, and charge is injected from the overflow drain 13. During the initial period of the accumulation period for performing sensitivity adjustment, the potential of the second N ⁺ layer 5 which became higher than the V _NO is returned to V _NO . This method utilizes the fact that the electrical properties of the surface of the semiconductor substrate 1 under the readout gate electrode 8 and the overflow control electrode 14 are almost the same.
A potential setting for the second N ⁺ layer 5 is prepared. However, unless the above-mentioned electrical properties are exactly the same, this may cause a very small number of problems. On the other hand, as shown in FIG. 5a, a voltage _VH lower than the voltage V _C applied to the readout gate electrode 8 during the signal readout period is applied to the overflow control electrode 14, and _VG shown in FIG. _A to V
Apply a changed initial period to _I. As a result, as shown in the potential distribution shown in Fig. 3b, an additional charge of 1 is added to the load 15 determined by V _NO in the method of Fig. 3.
7 remains in the second N ⁺ layer 5. According to this method, the above-mentioned development in which the signal of the dark part of the imaged object does not appear as an output does not occur, and according to this method, each cell accumulates a certain amount of charge 17 as well as a signal charge. This eliminates the problem of poor color reproducibility in areas where the subject is photographed with a small amount of signal.

As described above, the method of the present invention can prevent problems caused by conventional methods, such as deterioration of color reproducibility in color development or development in which dark areas of an imaged subject do not appear in the output.

In the embodiment, a stepped voltage was applied to the transparent electrode, but a pulse or sinusoidal voltage may also be applied as in the conventional example, and the V _I retention period for accumulating signal charges in the accumulation period For example, the sensitivity adjustment and the photoelectric conversion characteristics may be controlled simultaneously by applying a voltage that changes stepwise or continuously over time.

Although the embodiments have been described using a photoconductive amorphous semiconductor, it goes without saying that various other photosensitive materials can be used. Therefore, although the amorphous semiconductor layer 3 in the embodiment has been described as a single layer, it may be formed of a plurality of layers. Moreover, the same thing can be said about other constituent substances. Although the present invention has been explained using a CCD as a signal charge readout section, for example, a BBD (Bucket Brigade)
Device). That is, the present invention can be applied to a "two-story sensor" in which one cycle consists of signal accumulation and readout, and is not limited to CCDs. It goes without saying that the present invention can be applied to both one-dimensional and secondary sensors. Furthermore, as an example, an explanation has been given of an example in which the amorphous semiconductor layer 3 is sandwiched between the transparent electrode 7 and the metal electrode 4, which utilizes the characteristics in the thickness direction of the amorphous semiconductor layer 3. It goes without saying that the present invention can also be applied to things.
Furthermore, although a single transparent electrode 7 has been described, it is also possible to control a plurality of transparent electrodes.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are diagrams for explaining the conventional example,
3 to 5 are diagrams for explaining embodiments of the present invention, respectively. 1: p-type semiconductor substrate, 2: first N ⁺ layer, 3:
Amorphous semiconductor layer, 4: conductor electrode (first conductor electrode), 5: second N ⁺ layer, 6-1, 6-2: p ⁺
layer, 7: transparent electrode (second conductor electrode), 8: readout gate electrode, 9: CCD transfer electrode, 10-1,
10-2: Insulating film, 11, 12: Signal charge, 1
3: overflow drain, 14: overflow control electrode, 15, 16: charge injected from the overflow drain.

Claims (1)

[Claims] 1. An opposite conductivity type layer provided on a semiconductor substrate of one conductivity type, a photoelectric conversion semiconductor layer that performs photoelectric conversion electrically connected to the opposite conductivity type layer, and a a readout section provided on the substrate adjacent to the layer of opposite conductivity type for reading signal charges; and a readout section provided on the substrate adjacent to the layer of opposite conductivity type, and spaced apart from the layer of opposite conductivity type on the opposite side to the readout section when viewed from the layer of opposite conductivity type. In a solid-state imaging device having a drain provided on the substrate and capable of removing the signal charges, the solid-state imaging device includes a period for reading out the signal charges from the readout section and an accumulation period for accumulating the signal charges generated in the photoelectric conversion semiconductor layer. Consists of one cycle of operation,
During an arbitrary period following the signal charge readout period, a voltage is applied to an electrode provided in contact with the photoelectric conversion semiconductor layer to cause charges of the same polarity as the signal charges to flow from the opposite conductivity type layer to the photoelectric conversion semiconductor layer. and then, at the beginning of a period in which a voltage for accumulating the signal charges in the opposite conductivity type layer is applied to the electrode, charges having the same polarity as the signal charges are injected from the drain into the opposite conductivity type layer. A method for adjusting the sensitivity of a solid-state imaging device.