JPS6257803U - - Google Patents
Info
- Publication number
- JPS6257803U JPS6257803U JP15065585U JP15065585U JPS6257803U JP S6257803 U JPS6257803 U JP S6257803U JP 15065585 U JP15065585 U JP 15065585U JP 15065585 U JP15065585 U JP 15065585U JP S6257803 U JPS6257803 U JP S6257803U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- signal
- card
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000903 blocking effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Programmable Controllers (AREA)
Description
第１図は、本考案の具体的な一実施例に係る入
出力カード選択回路を有するプログラマブルコン
トローラの全体の構成を示したブロツクダイヤグ
ラム、第２図は、１６点出力カードの構成を示し
た電気回路図、第３図は、８点出力カードの構成
を示した電気回路図、第４図は、同実施例に係る
入出力カード選択回路の構成を示した電気回路図
である。
FIG. 1 is a block diagram showing the overall configuration of a programmable controller having an input/output card selection circuit according to a specific embodiment of the present invention, and FIG. 2 is an electrical diagram showing the configuration of a 16-point output card. FIG. 3 is an electric circuit diagram showing the configuration of an eight-point output card, and FIG. 4 is an electric circuit diagram showing the configuration of an input/output card selection circuit according to the same embodiment.
Claims (1)
指定して選択するアドレス信号をプログラム制御
を行う処理装置から入力し、 入出力要素を接続し、接続された入出力要素の
２値状態を示す２値データが、前記処理装置から
のアドレス指定により、該処理装置から入出力制
御される入出力カードに接続され、 前記アドレス信号の内、前記１の入出力カード
内における前記入出力要素のアドレスを決定する
下位４ビツトの信号を除く上位アドレス信号に応
じて該入出力カードを選択するカード選択信号を
前記入出力カードに出力する プログラマブルコントローラの入出力カード選
択回路において、 前記入出力カードから、そのカードの端子数が
８点か１６点かを識別する２値信号からなる点数
識別信号を入力し、 前記アドレス信号の下位４ビツトのうち前記入
出力要素のカード内のアドレスを上位と下位に２
分する分割アドレス信号を入力し、 前記点数識別信号が８点状態を示すレベルにあ
り且つ、前記分割アドレス信号が予め定められた
何れか一方のレベルにある時には前記カード選択
信号の出力を阻止するカード選択禁止回路を設け
たことを特徴とするプログラマブルコントローラ
の入出力カード選択回路。[Claims for Utility Model Registration] An address signal for selecting an input/output element by designating the address assigned to it is input from a processing device that performs program control, connects the input/output elements, and selects the input/output element by specifying the address assigned to it. Binary data indicating a binary state is connected to an input/output card whose input/output is controlled by the processing device according to an address specification from the processing device, In the input/output card selection circuit of a programmable controller, the input/output card selection circuit of the programmable controller outputs a card selection signal for selecting the input/output card according to the upper address signal excluding the lower 4-bit signal that determines the address of the input/output element to the input/output card. A point identification signal consisting of a binary signal that identifies whether the card has 8 or 16 terminals is input from the input/output card, and the address of the input/output element in the card is input from the lower 4 bits of the address signal. to the top and bottom 2
inputting a division address signal for dividing the number of points, and blocking output of the card selection signal when the point identification signal is at a level indicating an 8-point state and the division address signal is at one of predetermined levels. An input/output card selection circuit for a programmable controller, characterized in that a card selection prohibition circuit is provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985150655U JPH0313766Y2 (en) | 1985-09-30 | 1985-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985150655U JPH0313766Y2 (en) | 1985-09-30 | 1985-09-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6257803U true JPS6257803U (en) | 1987-04-10 |
| JPH0313766Y2 JPH0313766Y2 (en) | 1991-03-28 |
Family
ID=31066988
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985150655U Expired JPH0313766Y2 (en) | 1985-09-30 | 1985-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0313766Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60140105U (en) * | 1984-02-23 | 1985-09-17 | 日本電気精器株式会社 | Expansion base address setting circuit |
-
1985
- 1985-09-30 JP JP1985150655U patent/JPH0313766Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60140105U (en) * | 1984-02-23 | 1985-09-17 | 日本電気精器株式会社 | Expansion base address setting circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0313766Y2 (en) | 1991-03-28 |
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