JPS6257457U - - Google Patents

Info

Publication number
JPS6257457U
JPS6257457U JP14770185U JP14770185U JPS6257457U JP S6257457 U JPS6257457 U JP S6257457U JP 14770185 U JP14770185 U JP 14770185U JP 14770185 U JP14770185 U JP 14770185U JP S6257457 U JPS6257457 U JP S6257457U
Authority
JP
Japan
Prior art keywords
circuit
line
sending period
voltage
during
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14770185U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14770185U priority Critical patent/JPS6257457U/ja
Publication of JPS6257457U publication Critical patent/JPS6257457U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来におけるミユート回路を示す回路
構成図、第2図は本考案の一実施例におけるミユ
ート回路を示す回路構成図である。 1a,1b……回線、2……通話回路、4……
アウトダイヤルパルス(OPD)制御回路、10
……ミユート回路、11……スイツチングドラン
ジスタ、12……制御トランジスタ、14,15
……抵抗、16……バイアス回路、18……コン
デンサ。
FIG. 1 is a circuit diagram showing a conventional mute circuit, and FIG. 2 is a circuit diagram showing a mute circuit according to an embodiment of the present invention. 1a, 1b...Line, 2...Telephone circuit, 4...
Out dial pulse (OPD) control circuit, 10
... Mute circuit, 11 ... Switching transistor, 12 ... Control transistor, 14, 15
...Resistor, 16...Bias circuit, 18...Capacitor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ダイヤルパルスの送出期間に通話回路を回線か
ら電気的に切離す電話機のミユート回路において
、前記回線と通話回路との間に介挿されたスイツ
チングトランジスタと、ダイヤルパルスの送出期
間に前記スイツチングトランジスタを遮断させる
制御トランジスタと、ダイヤルパルスの非送出期
間に前記回線の電圧に応じて変化する電圧を前記
制御トランジスタにバイアス電圧として印加する
バイアス回路とを具備したことを特徴とする電話
機のミユート回路。
In a mute circuit of a telephone that electrically disconnects a calling circuit from a line during a dial pulse sending period, a switching transistor inserted between the line and the calling circuit, and a switching transistor inserted during a dial pulse sending period. 1. A mute circuit for a telephone set, comprising: a control transistor that cuts off a dial pulse; and a bias circuit that applies a voltage that changes according to the voltage of the line to the control transistor as a bias voltage during a non-sending period of dial pulses.
JP14770185U 1985-09-27 1985-09-27 Pending JPS6257457U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14770185U JPS6257457U (en) 1985-09-27 1985-09-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14770185U JPS6257457U (en) 1985-09-27 1985-09-27

Publications (1)

Publication Number Publication Date
JPS6257457U true JPS6257457U (en) 1987-04-09

Family

ID=31061301

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14770185U Pending JPS6257457U (en) 1985-09-27 1985-09-27

Country Status (1)

Country Link
JP (1) JPS6257457U (en)

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