JPS6257260B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary insulated gate field effect semiconductor integrated circuit device, and in particular, when a complementary insulated gate field effect semiconductor integrated circuit device becomes defective due to an increase in power supply current during standby, The present invention relates to a complementary insulated gate field effect semiconductor integrated circuit device having a structure that allows easy analysis.

It is generally said that the advantage of complementary insulated gate field-effect semiconductor integrated circuit devices (hereinafter referred to as CMOSICs) is low power consumption. The reason for this is that the power supply current (hereinafter referred to as Iccs) when the circuit operation is stopped is theoretically zero.

In actual products, the maximum value of Iccs standard is 30μA.
It is set to ~100μA. On the other hand, in a P-type or N-type MOS integrated circuit device, a DC current always flows through the load MOS transistor even when the circuit operation is stopped, so the power supply current does not become zero. A current of about several milliamps is flowing. By the way, as mentioned above
The advantage of CMOSIC is low power consumption, but as the integration density has increased in recent years and the wafer manufacturing process has become more complex, the above-mentioned Iccs problem has emerged, and it is extremely important to investigate the cause and solve it. It's summery. In other words, the value of Iccs tends to exceed the standard value. In wafer testing, if 100 functioning pellets were collected, about 30 of them would have Iccs exceeding the standard value and become defective pellets. In other words, as many as 30% of the pellets exceed the Iccs value and are considered defective.

Therefore, it is urgent to investigate the cause of the Iccs standard deviation, as it can be expected to significantly improve the non-defective product rate. However, it has been difficult to clearly and quickly determine the cause. This is because the defective Iccs value is caused by the conventionally thought problems such as defective withstand voltage of diffusion layers and wells, pattern abnormalities due to disconnections and shorts in various wirings, fluctuations in threshold voltage V _T , and increases in subthreshold current. by MOS
This was due to many factors and various combinations, such as abnormal characteristics of the transistor. Conventional methods for investigating the cause have been to insert various check patterns into a part of the chip, but in any case it has not been possible to determine the exact cause. .

The purpose of the present invention is to solve the above-mentioned cause of Iccs value overflow without providing any special patterns or wiring layers.
Furthermore, it is an object of the present invention to provide a CMOSIC with a means for clearly determining the high integration density without significantly impairing the integration density.

The present invention is characterized in that, as a method for connecting the well region and the substrate to the power supply line, highly concentrated diffusion layers of the same conductivity type as the wells and the substrate are formed in a plurality of wells and in the substrate, and This CMOSIC has type diffusion layers connected to each other through a metal wiring layer, and then connected to a power supply wiring only through a low-resistance polycrystalline silicon or metal wiring layer at one end of the metal wiring.

Hereinafter, embodiments of the present invention will be explained using drawings, taking as an example a case where a P-type well is adopted with a silicon gate structure, and low-resistance polycrystalline silicon is used for connection to the well region and the power supply wiring of the substrate. I will do it. Note that the circuit of the pattern is a two-stage inverter circuit.

FIG. 1 is a layout pattern showing the connection of a conventionally used P-type well region and an N-type substrate to power supply wiring, and FIG. 2 shows an equivalent circuit of FIG. 1. In Figures 1 and 2, 101
and 102 are an Nch transistor and a Pch transistor of the first stage inverter circuit. 103 and 1
04 is an Nch transistor and a Pch transistor of the second stage inverter circuit. 105 and 106 are gate polysilicon gates of the first and second stage transistors. 107 is an output terminal. 108 and 109 are a P-type high impurity diffusion layer in the P-type well and an N-type high impurity diffusion layer in the N-type substrate, respectively. The source electrodes of the Nch transistors 101 and 103 are commonly connected together with the P-type diffusion layer 108 by an aluminum wiring 110 that is a Vss power source. Further, the source electrodes of the Pch transistors 102 and 104 are commonly connected together with the N type diffusion layer 109 by an aluminum wiring 111 which is a Vcc power source. Note that 112 indicates a P-type well. According to such a conventional structure, the Vcc wiring 110 and
Since the Vcc wiring 111 serves as the circuit power supply and the power supply for the P-type well and the N-type substrate, for example, the P-type well, the N-type diffusion layer in the P-type well, and the P-type
It has been difficult to accurately know the breakdown voltage or leakage current of the type diffusion layer because it is combined with the circuit current.

Therefore, in this embodiment, the potential of the P-type well and N-type substrate is separated from the Vss wiring and Vcc wiring of the circuit, the P-type wells and the N-type substrates are connected with aluminum wiring, and finally, By connecting one end of the aluminum wiring to the circuit's Vss wiring and Vcc wiring via low-resistance polysilicon, it becomes easy to investigate the cause of the Iccs standard value exceedance by performing a small amount of work during failure analysis. It is something. FIG. 3a shows an embodiment of the present invention, FIG. 3b shows a sectional view taken along line a-a' in FIG. 3a, and FIG. 4 shows an equivalent circuit of FIG. 3a.
In these figures, FIGS. 1 and 2, which are conventional examples,
The difference from the diagram is the Vss aluminum wiring 210 connected to the source electrode of the Nch transistor and the aluminum wiring 213 for taking the potential of the P-type well.
and connected to the source electrode of the Pch transistor
A Vcc aluminum wiring 211 and an aluminum wiring 214 for taking the potential of the N-type substrate are formed separately, and a Vss wiring 214 is further formed via low resistance, for example, 50Ω polysilicon 215 and 216.
10 and Vcc wiring 211. Note that 217 and 218 are small parts used when investigating the cause of exceeding the Iccs standard, and are at the same potential as the aluminum wirings 213 and 214, respectively. With such a pattern layout configuration, even if the pellet exceeds the Iccs standard value and becomes a defective pellet, the polysilicon 215 or 216
By passing a current through and blowing it out, the withstand voltage and leakage current of the P-type well, N-type and P-type diffusion layers can be determined separately. The so-called polysilicon 215 and 216 have a role as a fuse in addition to the P-type well and the base potential contact. Furthermore, since the P-type well and N-type substrate are separated from the Vss wiring and Vcc wiring on the circuit,
Even if the cause of Iccs failure is circuit-related, it can be known.

As described above, according to the present invention, the cause of exceeding the Iccs standard can be clearly and quickly determined without providing any special patterns or wiring layers.

In this embodiment, polysilicon for the fuse is used for the P-type well and the N-type substrate at the same time, but the purpose of the present invention will not be impaired even if only one of them is used. In addition to polysilicon for fuses, if spot exposure or laser beams can be used, aluminum wiring may be used to directly connect to the power supply line. Furthermore, it is also effective to apply the present invention only to a memory element group of a complementary insulated gate field effect semiconductor memory circuit device.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing the connection of a conventionally used P-type well region and N-type substrate to power supply wiring, FIG. 2 is an equivalent circuit of FIG. 1, and FIG. 3a is an embodiment of the present invention. FIG. 3b is a sectional view taken along line a-a' in FIG. 3a, and FIG. 4 is an equivalent circuit of FIG. 3a. In the figure, 101 to 104...Nch and
Pch transistor, 105-106...gate polysilicon, 107...output terminal, 108...P
Type diffusion layer, 109...N type diffusion layer, 110...
Vss power supply aluminum wiring, 111...Vcc power supply aluminum wiring, 112...P-type well, 21
0...Vss power supply aluminum wiring, 211...
Vcc power supply aluminum wiring, 213...aluminum wiring for P-type well connection, 214...aluminum wiring for N-type substrate connection, 215-216...polysilicon for fuse, 217-218...small pads for analysis.

Claims (1)

[Claims] 1. A metal wiring connected to the semiconductor substrate or the well region via a contact in order to apply a potential to the semiconductor substrate of one conductivity type or the well region of the opposite conductivity type formed in the semiconductor substrate, and another power source. A complementary insulated gate field effect semiconductor integrated circuit device, characterized in that connection with wiring is made only at one end of the metal wiring.