JPS6256591B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic recording and reproducing device, which reproduces signals such as wow and flutter detection, and based on the reproduced signals, reproduces signals of tracks recorded in the longitudinal direction of a tape. It is an object of the present invention to provide a device that can substantially improve the effects of wow and flutter that appear through electrical signal processing.

In recent years, home magnetic recording and reproducing apparatuses have tended to have longer recording and reproducing times, and as a result, not only the track pitch has become narrower, but also the running speed of the magnetic tape has become smaller than in the past. However, if the rotational speed of the capstan is reduced in order to reduce the magnetic tape running speed, even if the tape running variables due to disturbances, capstan eccentricity, etc. are constant, the relative speed will be lower than when the tape running speed is high. It has been extremely difficult to mechanically reduce wow and flutter because the changes are large and the effect of wow and flutter (uneven rotation) on the length of elongation or contraction of the same magnetic tape is large. Of the recording tracks on the magnetic tape, this wow and flutter is applied to the reproduction signal to the fixed head from the audio track and control track, which are formed in the longitudinal direction of the tape, rather than the video track, which is formed at an angle with respect to the longitudinal direction of the tape. It is well known that the impact is significant.

Therefore, in order to eliminate the above-mentioned drawbacks, the present applicant proposed a "wow and flutter improvement device" in Japanese Patent Publication No. 55165/1983 (Japanese Patent Application No. 145268/1983). The outline of this proposal is as follows.

A wow and flutter detection signal having a frequency change corresponding to the wow and flutter reproduced from a track recorded in the longitudinal direction of the magnetic tape is supplied, and a frequency change (or phase change) of the wow and flutter detection signal is detected. A circuit for converting the wow and flutter into an electric signal and outputting it, and a circuit provided in a part of a transmission path for an analog information signal reproduced from a track different from the track recorded in the longitudinal direction of the magnetic tape. a variable delay element, and the delay time of the variable delay element is determined by the output signal of the circuit.
It is composed of a control circuit that performs variable control to give the information signal a frequency change of opposite polarity to the frequency change of the flutter, and the audio heads 1 and 2 and the control circuit in the positional relationship shown in FIG. 1B. The head 3 records audio signals on the audio tracks Tr ₁ and Tr ₂ on the magnetic tape 4 shown in FIG. A, and a control signal and a wow/flutter detection signal on the control track Tr ₃ It is. Therefore, during reproduction, a reproduction signal S as shown in FIG. 2 is obtained by the control head 3, the positive polarity portion of this reproduction signal S is used as a control pulse, and the negative polarity portion is used as a wow/flutter detection pulse.

However, as shown in FIG. 2 in the above proposal, there was a problem in that the negative polarity portion of the pulse causes a phase shift in a certain region of the positive polarity portion of the pulse. That is, the period of the pulse in the negative polarity part of the region is t, and the period of the same pulse in the region is
t′, and the period of the same pulse in the area is t″, then
There is a problem in that period fluctuation occurs due to the relationship t'<t<t'', resulting in inaccurate wow/flatter detection signals.

The present invention eliminates the above-mentioned problems, and one embodiment thereof will be described with reference to FIGS. 3 to 21.

FIGS. 3A and 3B show schematic diagrams of the positional relationships between the patterns on the magnetic tape and the various heads in this embodiment. In this embodiment, the conventional control head 3 is divided into parts to form a control head 5, a wah and
The control head 5 records and reproduces control pulses as in the conventional manner, and the wow and flutter detection pulse recording and reproducing head 6 records and reproduces wow and flutter detection pulses. Although the two heads 5 and 6 may be adjacent to each other or separated from each other, the width W of the conventional control head 3 and the width W' of the heads 5 and 6 of this embodiment are made the same.

FIGS. 4A and 4B show block diagrams of an example of a recording system and a reproducing system for a wow/flutter detection signal used by the apparatus of the present invention, respectively. In the block diagram of the recording system shown in Figure A, input terminal 7 receives, for example, a vertical synchronization signal separated from the video signal to be recorded.
A control pulse a of a two-head helical scanning VTR as shown in FIG. . This thin pulse is supplied to a sampling and holding circuit 9. The sampling hold circuit 9 converts the sawtooth wave from the sawtooth wave generator 10 into the waveform shaping circuit 8.
Sampling and holding are performed using a narrower pulse, and the output thereof is applied to a voltage controlled oscillator (hereinafter referred to as "VCO") 12 via a low-pass filter 11 to control its output oscillation frequency. After the output signal of this VCO 12 is divided by 1/n by the 1/n frequency divider 13,
The output of the VCO 12 is supplied to a sawtooth wave generator 10 to generate a sawtooth wave, while the output of the VCO 12 is supplied to a waveform shaping circuit 14. The sampling hold circuit 9, low-pass filter 11, VCO 12, 1/n frequency divider 13, and sawtooth wave generator 10 constitute a phase locked loop (PLL), and the frequency is the control pulse from the input terminal 7. The VCO 12 outputs a rectangular wave b as shown in FIG. 5B having a frequency n times a (for example, 5 times).

The waveform shaping circuit 14 generates and outputs a narrow pulse c (shown in FIG. 5C) synchronized with the rising edge of the rectangular wave b, and applies it to the sawtooth wave generator 15. The sawtooth wave generator 15 generates a sawtooth wave d, as shown in FIG. 6 and recorded on the track Tr ₅ of FIG. 3A formed in the longitudinal direction of the magnetic tape 4. The input control pulse a is also supplied to the control head 6, and is recorded by forming a control track _Tr4 as shown in FIG. 3A in the longitudinal direction of the magnetic tape 4.

As described above, according to this embodiment, the track width W of the conventional control head 3 is divided into two parts, and one of the track widths is divided into two parts.
By using the other track width as the track width of the wow/flutter detection pulse recording/reproducing head 6, the control pulse and the wow/flutter detection pulse are formed into separate tracks Tr ₄ and Tr ₅ . It was designed so that it could be recorded.

Furthermore, in this embodiment, as the above-mentioned wow and flutter detection pulse, a pulse having a high level only in the polarity opposite to the polarity of the reproduction control pulse used in the servo circuit during reproduction (the fifth pulse described later) is used.
As described above, the sawtooth wave d is recorded so as to be reproduced as f in FIG. As is clear from FIGS. 5A and 5D, the phases of the sawtooth wave d and the input pulse a are adjusted by the VCO 12 so that the rising portion of the pulse a is located at the center of the slope of the sawtooth wave d.

Next, the operation of the reproduction system will be explained with reference to FIG. 4B. The wow and flutter detection pulse (sawtooth wave) d recorded by the head 6 on the track Tr ₅ is differentiated by the inductance of the winding of the head 6 during reproduction, and is different from the recorded waveform, as shown in FIG. 5F. The reproduced signal is outputted from the head 6 as a pulse waveform reproduction signal whose level increases only in the negative polarity as shown in FIG. The reproduced wow/flatter detection pulse (reproduced signal) f is inverted and amplified by an inverting amplifier 17, then converted to a low impedance by an emitter follower 18, and supplied to a differentiating circuit 19, a comparator 20, and a peak hold circuit 21, respectively. The output signal of the differentiating circuit 19 is a signal i obtained by differentiating the polarity inverted signal of the reproduced signal f, as shown in FIG. 5I, and the comparator 22 determines whether the signal is positive or negative. That is, the reference voltage input terminal of the comparator 22 is grounded (not shown), and by detecting the zero potential of the differential signal i,
The peak point of the signal before differentiation and the falling peak point of the reproduced signal f are detected. The output of the comparator 22 changes from low level to high level when the differential signal i changes from positive to negative.

The output of the comparator 22 is supplied to a waveform shaping circuit 23, where it is converted into a pulse j with a narrow pulse width as shown in FIG. applied. On the other hand, the peak hold circuit 21
detects and holds the peak voltage of the positive polarity portion of the signal whose polarity is inverted from that of the reproduction signal f, and supplies this detected peak voltage to the reference voltage input terminal of the comparator 20 via the voltage dividing variable resistor 25. The comparator 20 uses this reference voltage and the emitter follower 18
The voltage is compared with the output signal of the output signal, that is, the inverted amplified signal of the reproduced signal f, and a pulse h having a waveform as shown in FIG. Output k.
Therefore, the output signal of the gate circuit 24 becomes a pulse k synchronized with the negative polarity portion of the reproduced signal f (the zero potential that crosses when the differential signal i changes from positive to negative) as shown in FIG. The signal is supplied as a flutter detection signal to a wow/flutter improvement device, which will be described later. The purpose of generating the pulse h is to
This is to eliminate the period in which the differential signal i is at zero potential in addition to the portion in which the differential signal i required to generate the flutter detection signal changes from positive to negative.

On the other hand, the reproduced control pulse e shown in FIG. 5E, which is reproduced from the control track Tr ₄ by the control head 5, is supplied to a known servo circuit in a VTR (not shown), where only the positive pulse portion is transmitted to the rotating drum or caps. used to control the rotational phase of

When the magnetic tape 4 shown in FIG. 3A recorded by the recording device according to the present invention is reproduced by the conventional control head shown in FIG. 1B, the control pulse e and the wow/flutter detection pulse f are reproduced simultaneously. The result is a pulse g shown in FIG. 5G, and this pulse g is supplied to the servo circuit. During recording, the rising edge of pulse a is positioned approximately at the center of the slope of pulse d, so that the upward pulse used in the servo circuit is not affected by the wow/flatter detection pulse.

Since the wow and flutter detection signal k taken out from the gate circuit 24 changes in frequency according to the wow and flutter of the magnetic tape of the VTR, wow and flutter can be detected by detecting the frequency change of the wow and flutter detection signal k. can be detected.

As an example, the device of the present invention uses the above-mentioned wow and flutter detection signal k to reduce fluctuations due to wow and flutter in the playback signal of a track recorded in the longitudinal direction of a magnetic tape. Let's discuss an example.

FIG. 6 shows a block system diagram of the first embodiment of the device of the present invention, and FIG. 7 shows a specific circuit diagram of FIG. 6, and the same components in both figures are given the same reference numerals. In FIGS. 6 and 7, the audio signal reproduced from the audio track formed in the longitudinal direction of the magnetic tape of the VTR (not shown) is input to the input terminal 2.
6 to a low-pass filter 27, where unnecessary high-frequency components are removed, and then supplied to a bucket brigade device (BBD) 28, which is an example of a variable delay element. As is well known, the BBD 28 imparts a delay time determined by the clock frequency and the number of clock stages to the input playback audio signal, but as will be described later, the BBD 28 removes the quantization noise of the wow/flutter detection signal without using a reduction filter. ,
The average delay time is controlled to match the period of the wow/flutter detection signal, and the delay time is variably controlled depending on the frequency of the wow/flutter.

The reproduced audio signal delayed and extracted by the BBD 28 is filtered through a reduction filter 29 to remove unnecessary components such as the clock frequency, and then output to the output terminal 3.
Sent to 0. As shown in FIG. 7, the BBD 28 is composed of, for example, 1024 stages of BBDIC 40, etc. The variable resistor VR ₁ is for bias adjustment of the BBDIC 40, and the variable resistor VR ₂ is a variable resistor for adjusting the clock leakage balance of the BBDIC 40. It is.

On the other hand, the wow and flutter detection signal reproduced from the control track input to the input terminal 38 is reproduced because the control track is formed in the longitudinal direction of the magnetic tape like an audio track and is reproduced by a fixed head. The wow and flutter frequency fluctuates at the same wah and flutter frequency as the audio signal, and this wow and flutter frequency is detected by the phase comparator 36.
and is detected by the PLL consisting of VCO37.
In the block system diagram shown in FIG. 6, the monostable multivibrator 41 for pulse shaping shown in FIG.
The illustration of is omitted.

As shown in FIG. 7, the phase comparator 36 is composed of two operational amplifiers 42 and 43, etc.
The signal taken out from the 3rd terminal of the IC 44 constituting the VCO 37 and the wow/flatter detection signal are compared in phase, and the operational amplifier 43 outputs an error voltage corresponding to the phase difference to the 5th terminal of the IC 44. The variable resistor VR ₃ in the VCO 37 shown in Figure 7 is
This is for adjusting the output frequency. The PLL consisting of the phase comparator 36 and VCO 37 is configured not to respond to the 1 Hz wow and flutter frequency by reducing the loop gain in consideration of the wow and flutter frequency (frequency change of the wow and flutter detection signal). has been done.

Figure 8 shows the above for wow and flutter frequency detection.
This figure shows an example of the frequency characteristics of a PLL, showing the characteristics of a low-pass filter with a cutoff frequency of 0.8 Hz, and the error voltage on the vertical axis is the output error voltage of the phase comparator 36.

The output error voltage of the phase comparator 36 is an electrical signal representing information on wow and flutter, and after phase correction in the phase correction circuit 35, it is amplified in the amplifier 33 and applied to the VCO 32 as a control voltage. Here, the phase correction circuit 35 is a resistor as shown in FIG.
It is a so-called lag lead filter mechanism consisting of R ₁ , R ₂ and capacitor C ₁ , and is provided for the purpose of correcting the phase characteristics in the low frequency range of the PLL consisting of the phase comparator 36 and VCO 37.
It has a frequency-gain characteristic as shown in the figure and a frequency-phase characteristic as shown in the same figure. In Figure 9, the characteristics shown by the solid line are the characteristics when the resistance R ₁ is 22 kHz, R ₂ is 10 kHz, and C ₁ is 10 μF, and the broken line is the characteristics when R ₁ is 39 kHz, and R ₂ is 10 μF.
The characteristics are shown when _C1 is 8.2μF at 15kHz.

The amplifier 33 has a configuration in which two operational amplifiers 45 and 46 are connected in series as shown in FIG. 7, and VR ₄ is a variable resistor for adjusting the gain of the operational amplifier 46. The VCO 32 is composed of an IC 47 and a variable resistor VR ₅ for adjusting its free-running oscillation frequency, and after the voltage from the amplifier 33 is divided by resistors R ₃ and R ₄ as shown in FIG. 5
The frequency of the oscillation frequency signal input to the No. 3 terminal and output from the No. 3 terminal is varied. Therefore,
The output oscillation frequency of the VCO 32 will change according to the wow and flutter.

The output oscillation frequency signal of the VCO 32 is supplied to the clock drive circuit 31, where the waveform is shaped and applied as a clock pulse to the BBD 28 shown in FIGS. 6 and 7. Therefore, the VCO
Since the output oscillation frequency of BBD2 changes according to the wow and flutter, the frequency of the clock pulse mentioned above also changes according to the wow and flutter.
The delay time of No. 8 is also variably controlled according to the wow and flutter. As shown in FIG. 7, the clock drive circuit 31 includes an NPN transistor Q whose base receives a signal from the VCO 32, amplifies it, and outputs it from its collector to the 7th terminal of the clock driver IC 48, and the clock driver IC 48. IC48 and clock driver IC4
8 divides the input signal frequency by 1/2 and outputs rectangular waves of opposite polarity from the 2nd and 4th terminals of the clock driver IC 48, respectively, and applies them to the 6th and 2nd terminals of the BBDIC 40.

Here, since wow and flutter is a frequency change, when a sine wave is applied to the VCO 32 and a frequency change similar to that which causes wow and flutter is applied to the sine wave, the audio signal supplied to the BBD 28 (here, the characteristic For convenience, we use a 3kHz sine wave without wow or flutter.
The signal frequency change when extracted from 8 is as shown in FIG. The characteristics in Figure 10 are as follows: The average clock frequency is 85kHz, and the stage of BBD32.
In the example when 1024 steps are used, the average delay time of BBD28 is 6.02ms, and as a result, the average delay time is
A frequency of 165.9Hz with a period equal to 6.02ms and its natural number multiples of frequencies 331.8Hz, 497.5Hz, 663.3Hz,...
It can be seen from FIG. 10 that no wow or flutter occurs in the output signal of the BBD 28. Therefore, in this embodiment, in consideration of this fact, in order to remove the quantization noise caused by sampling at the period of the wow/flatter detection signal in the output waveform of the phase comparator 36 as shown in FIG. The period of the wow/flutter detection signal and the average delay time of the BBD 28 are made to match each other without using the . Further, the clock frequency of the BBD 28 is variably controlled in order to provide the audio signal with a wow and flutter of opposite polarity to the wow and flutter detected by the PLL consisting of the phase comparator 36 and the VCO 37.

If the delay time of BBD28 and the period of wow and flutter match, the audio signal is
While passing through the clock, the high and low clock frequencies appear to have the same length, resulting in the same length as in the case of a constant clock frequency.

Wow/Fluttering is a frequency change, BBD2
The relationship is obtained by differentiating the time change given by 8. This is exactly the opposite of detecting frequency changes with the phase comparator 36 in the PLL, and has the characteristics shown in Figure 8.
By combining the PLL and the control of the BBD 28 having the characteristic shown in the 10th figure, the cutoff frequency of the PLL is 0.8.
The improvement characteristics become flat at frequencies above Hz. Also,
Since the phase correction circuit 35 is provided, the phase correction circuit 3
The frequency-gain characteristics and frequency-phase characteristics are improved as shown in FIG. 13, compared to the frequency-gain characteristics and frequency-phase characteristics of the wow/flatter correction circuit shown in FIG.

FIG. 14 is a characteristic diagram showing how much the phase of the wow and flutter component changes while an audio signal having wow and flutter at the frequency shown on the horizontal axis passes through the BBD 28. The broken line shows the characteristics when a delay time of 3.4 ms (clock frequency 150 kHz) is applied to a 3 kHz signal, and the broken line shows the characteristics when a delay time of 6.8 ms (clock frequency 75 kHz) is applied to an audio signal of 3 kHz. In other words, Figure 14 is BBD28, here
This shows the phase characteristics when a signal such as a 3kHz carrier wave frequency-modulated with a wow/flatter frequency is supplied. The frequency-phase characteristics shown in Figure 13 are
Since this is a characteristic of a system in which flutter is to be improved, it is ideal that the phase characteristic be exactly 180 degrees different from the phase characteristic shown in FIG. 14 when the clock frequency is the same. Here is the wow/flatter improvement system.
Flutter detection signal input terminal 38, phase comparator 36
and PLL consisting of VCO37, phase correction circuit 3
5. Refers to the transmission system that reaches the raw power terminal 30 via the amplifier 33, VCO 32, clock drive circuit 31, BBD 28, and low-pass filter 29.

By the way, it would be ideal to control the average oscillation frequency of the VCO 32 by detecting the frequency drift of the wow/flatter detection signal, but this frequency drift is very small, and the VCO
Since the relationship between the oscillation frequency of VCO 32 and the control voltage is relatively stable, this embodiment is provided with a frequency stabilization circuit 34 that integrates the voltage applied to the VCO 32 and controls the average DC voltage to a constant value. It is being Although this frequency stabilization circuit 34 can be made unnecessary by configuring the phase comparator 36, VCO 37, phase correction circuit 35, and amplifier 33 with sufficiently stable circuits, the frequency stabilization circuit 34 as in this embodiment is provided. It is easier to design and can be manufactured using cheaper parts if the configuration is adopted.

In addition, as described above, the phase comparator 36 and the VCO
Wow and flutter detected by PLL consisting of 37
In order to give the audio signal a wow and flutter with a 180° phase shift (opposite polarity), the amplifier 33 has a phase inversion function, and the VCO 37 and 32
The configuration is such that control voltages of opposite polarity are applied to each of them.

FIG. 15 is a diagram showing an example of the wow and flutter improvement characteristics of the device of this embodiment, where the horizontal axis is the frequency of wow and flutter, and the vertical axis is the output terminal 30 shown in FIGS. 6 and 7.
is connected to a wow and flutter meter, which is an F-V converter, and the actual measured value of the wow and flutter meter is shown. As is clear from FIG. 15, according to the device of this embodiment, an improvement of 6 dB or more can be obtained from wow and flutter frequencies of 0.6 to 40 Hz, and an improvement of 20 dB or more at 4 Hz.

16A to 16C are waveforms obtained by sequentially passing through a signal circle F-V converter with wow and flutter, and a low-pass filter, respectively, and A, B, and C in the same figure are waveforms obtained after passing through a signal circle F-V converter with wow and flutter, and a low-pass filter. The waveforms are shown when the upper limit cut-off frequency of the low-pass filter installed is 120Hz, 40Hz, and 20Hz. In addition, in FIGS. 16A to 16C, the waveform in the period _T1 is a signal waveform having wow and flutter observed without passing through the device of this embodiment, and in the period _T2 , the output terminal 30 of the device of this embodiment is connected to the F - The waveform diagram when connected to a V converter is shown, and the wah
It can be seen that the flatness has been improved. Note that in home VTRs, wow and flutter usually only become a problem up to a few Hz, but with this embodiment, wow and flutter are a problem in the relatively high frequencies below 120Hz and below 40Hz, as shown in Figures 16A and B. In addition to the improvement effect on wow and flutter, the actual problem of wow and flutter below 20Hz is improved as shown in Figure C.
As can be seen from the scale of 1% RMS of wow and flutter, it is large and particularly effective.

Note that in the above embodiment, in order to remove quantization noise as shown in FIG. 11, the period of the wow/flatter detection signal is
This is done by matching the average delay time of the BBD28, but the low-pass filter is replaced by the phase comparator 36.
The quantization noise may be removed by providing it in the transmission path leading to the VCO 32. In this case, since the low-pass filter exhibits the characteristic that the phase lags as the frequency becomes higher, the low-pass filter 27 and
The above-mentioned wah-wah filter is inserted with the above-mentioned low-pass filter than the transmission system through which the audio signal passes through the BBD 28 and the low-pass filter 29, respectively, and reaches the output terminal 30.
In the system that improves flutter, the phase lags more in the higher frequencies. However, regarding this phase delay, by inserting and connecting a delay element with a fixed delay time between the BBD 28 and the low-pass filter 27, the amount of phase delay in the high frequency range of the system through which the audio signal passes is increased, and the delay is By appropriately selecting the amount, it is possible to match the phase characteristics between the system through which the audio signal passes and the system for improving wow and flutter, so there is no problem.

Further, in the above embodiment, wow and flutter were detected by the PLL consisting of the phase comparator 36 and VCO 37 shown in FIGS. 6 and 7, but it can also be detected by an F-V converter. If a signal with wow and flutter up to about 10 Hz is input to the input terminal 38 at a specific frequency (for example, 3 kHz), the flutter frequency vs. detection output voltage characteristic will be a flat characteristic as shown in Figure 17. In order to match the wow and flutter improvement characteristics, it is necessary to add a frequency characteristic correction circuit to the position after detection. As an example of this frequency characteristic correction circuit,
A circuit with low-pass filter characteristics having an upper cutoff frequency of 0.2 Hz and a slope of -6 dB/oct can be considered, and in this case, it also has the function of the phase correction circuit 35, so the phase correction circuit 35 can be omitted. In Figure 6, the audio system is one system, but in the case of two channels, the low-pass filter 27, BBD 28, low-pass filter 2
9. It is sufficient to prepare another system similar to the clock drive circuit 31.

Next, a second embodiment of the device of the present invention will be described. FIG. 18 shows a block system diagram of a second embodiment of the apparatus of the present invention. In the figure, the same components as in FIG. 6 are given the same numbers. In Figure 18,
The audio signal that has entered the input terminal 26 is filtered with high frequency components by a low-pass filter (not shown), sampled and held in a sample-and-hold circuit (not shown), and further supplied to the AD converter 60, where the high-frequency components are removed. Analog-to-digital conversion is performed by a command pulse from a memory control unit 63, which will be described in detail later.
However, if a Δ modulator is used instead of the AD converter 60, the low-pass filter and sample-and-hold circuit, which are not shown above, become unnecessary.

The digital data taken out from the AD converter 60 is applied to the memory 61, and the data selector 6
The output memory write pulse of the memory control circuit 63 writes to the write address specified by the address designation signal from No. 4. Analog-digital conversion of AD converter 60 and memory 61
The writing speed of input terminal 38 is
This is done at a speed that corresponds to the wow and flutter (frequency change) of the wow and flutter detection signal that comes into the circuit.

On the other hand, the wow and flutter detection signal input to the input terminal 38 is detected by a PLL 68 comprising a phase comparator 65, a VCO 66, and a counter 67. PLL68 has a sufficiently fast response to respond to wow and flutter, so
In response to the wow and flutter, the VCO 66 outputs a clock pulse whose frequency changes to the address counter 69 and the memory control circuit 63, respectively.

Note that as a circuit for generating a clock pulse whose frequency changes in response to wow and flutter, instead of using the PLL 68 described above, as shown in FIG. 19, a wow and flutter detection circuit 75, a phase and gain correction circuit 76, A circuit consisting of the VCO 77 may be used, and when the circuit shown in FIG. 19 is used, it is an open loop similar to the first embodiment.

On the other hand, reading of the memory 61 is controlled by the output of the VCO 70 which oscillates a high frequency clock pulse, and the output clock pulse of the VCO 70 is divided by the counter 71 to have the same frequency as the output clock pulse of the VCO 66, and then the read address counter is used. 72. The outputs of the most significant bit of the address counter 69 and the most significant bit of the address counter 72 are compared in phase by a phase comparator 73, and their phase error voltages are passed through a loop filter 74 to the VCO.
70 as a control voltage, thereby forming a PLL that causes the read address designation signal output from the address counter 72 to lag slightly behind the write address designation signal output from the address counter 69. The cut-off frequency of this PLL is set sufficiently low, so that the output of the VCO 70 is at a constant frequency without responding to wow and flutter, and a digital signal at a constant speed is supplied from the counter 71 to the memory control circuit 63.

As a result, the stored digital data at the address specified by the read address designation signal applied from the address counter 72 to the memory 61 via the data selector 64 is read out at a constant speed, and the digital data is read out at a constant speed by the AD converter 62. - Analog converted back to the original analog audio signal without wow and flutter. This analog audio signal is outputted from the output terminal 30 after unnecessary high frequency components are removed by a low frequency filter (not shown).

Next, the operation of the memory control circuit 63 will be explained in more detail. FIG. 20 shows a block system diagram of one embodiment of the memory control circuit 63 and its peripheral circuits. In the figure, the same components as those in FIG. 18 are given the same numbers, and their explanations will be omitted. A 5-bit counter 71 counts down the output clock pulse of the VCO 70, and outputs the least significant bit, the second bit from the least significant, the third bit from the least significant, the fourth bit from the least significant, and the most significant bit. Therefore, "1", "2", "4",
It outputs pulses as shown in "8" and "16" respectively, among which the least significant bit, the second bit from the lowest, and the third bit from the lowest are shown in A in the figure as "1", "2", and "4". The output pulse from each output terminal of the th bit is supplied to a BCD decimal conversion circuit 84. As a result, as is well known, the BCD decimal conversion circuit 84 selects one of its output terminals "0" to "7".
“0” → “1” → “2” →… → “6” → “7” →
High-level pulses are sequentially and cyclically output from the output terminals in the order of "0" → . . . Among the output terminals of the BCD decimal conversion circuit 84, the pulse b as shown in FIG. A pulse c as shown in C is supplied to a gate circuit 85. Pulse b is in memory 61
The pulse c is used to create the write clock pulse for the memory 61, and pulse c is used to create the read clock pulse for the memory 61.

Further, the third lowest bit output of the counter 71 shown as "4" in FIG. 21A is applied to the data selector 64, and when it is at a low level, the output write address designation signal of the address counter 69 shown in FIG. 18 is selected. and apply it to the memory 61,
On the other hand, when the level is high, the address counter 72
A data selector 64 selects an output read address designation signal and applies it to the memory 61.
control.

Writing to memory 61 is performed by the second input from VCO 66.
This is carried out in sequence from the rising edge of the clock pulse e shown in FIG. MM by this MM80 trigger
80 to a command pulse f as shown in FIG. 21F.
is applied to the AD converter 60 to perform analog-to-digital conversion, while it is applied to the MM81 and triggers it at the falling edge of the MM81. As a result, the MM81 outputs a pulse g as shown in FIG. Ru.

The FF 82 is triggered by the fall of the pulse g, and applies a pulse h as shown in FIG. 21H to the gate circuit 83 as a gate pulse, and
Open the gate for a period of high level. Therefore, a pulse i as shown in FIG. 21I is taken out from the gate circuit 83, and at the same time this pulse i inverts the output of the FF 82, it is applied to the memory 61 as a write pulse, and the digital data is written to the designated write address. to be written.

On the other hand, reading from the memory 61 is performed as described above.
This is done by the output clock pulse of VCO 70. That is, the stored digital data is constantly read from a specified read address in the memory 61 and temporarily held in a latch (not shown).
An analog signal obtained by digital-to-analog conversion by the AD converter 62 is taken out as a read output. This AD converter 62 has two bit outputs, respectively shown as "8" and "16" in FIG. Gate circuit 85 that outputs level pulses
An output pulse d (shown in FIG. 21D) is applied as a read pulse.

In this way, AD conversion and writing to the memory 61 are performed at a speed that corresponds to the wow and flutter, and reading from the memory 61 and AD conversion are performed at a constant speed. Can improve the effects of wow and flutter.

In both the first and second embodiments described above, a signal as shown in FIG. However, the present invention is not limited to this, and the desired purpose can be similarly achieved by using a wow/flutter detection signal recorded on a track formed in the longitudinal direction of the magnetic tape. Further, even if the control signal is used as is, wow and flutter can be improved, although the performance is not as good as in the embodiment.

It should be noted that, like the reproduced signal f obtained by reproducing the waveform as shown in FIG.
As mentioned above, is used as a wow/flutter detection signal, but this is not the only signal such as pulse k, which is reproduced with the opposite polarity to the control pulse. For example, it can be used to detect tape position. It can be used for signals such as address signals, batch signals, queue signals, tape type discrimination signals, and signals for identifying the contents of audio multiplex signals.

As described above, the magnetic recording/reproducing apparatus according to the present invention divides the track width of the control head into two, and arranges the control pulse recording/reproducing head and the detection pulse recording/reproducing head side by side, and separates the control pulse and the detection pulse. A sawtooth wave or Since we recorded a signal with a waveform similar to this,
The detection pulse can be recorded and reproduced on a track other than the control track without being affected by the control pulse, and the control track and the detection pulse recording track on the magnetic tape recorded by the apparatus of the present invention can be Even if a single control head performs simultaneous reproduction using a conventional magnetic recording/reproducing device, the polarity of the reproduction detection pulse is opposite to the polarity of the reproduction control pulse used in the servo circuit, so there is no adverse effect on the servo circuit. It has features such as ensuring compatible reproduction of control pulses.

[Brief explanation of the drawing]

1A and 1B are diagrams showing the positional relationship between a track on a magnetic tape and a magnetic head in the prior art, FIG. 2 is a diagram of a reproduction signal obtained from a conventional control head, and FIGS. Figures 4A and 4B show an example of the recording system and reproduction system of the wow/flutter detection signal used by the apparatus of the present invention, respectively. Block diagram, No. 5
Figures A to K are signal waveform diagrams for explaining the operation of Figures 4A and B, respectively, Figure 6 is a block system diagram showing the first embodiment of the device of the present invention, and Figure 7 is a diagram of the first embodiment of the device of the present invention. A diagram showing a specific circuit, FIG. 8 is a diagram showing the frequency characteristics of the main parts of the devices shown in FIGS. 6 and 7, and FIG. 9 is a diagram showing the frequency-gain characteristics of the phase correction circuit of the devices shown in FIGS. 6 and 7. , a diagram showing the frequency-phase characteristics; FIG. 10 is a diagram showing the characteristics of the wow and flutter frequency that generates the output signal of a variable delay element (BBD) whose delay time is varied by a clock pulse having wow and flutter; FIG. 12 is a diagram showing the output waveform of the PLL for wow and flutter detection in the first embodiment of the device of the present invention, and FIG. 12 is the frequency-gain characteristic and frequency when the phase correction circuit is not provided in the device shown in FIGS. 6 and 7. - A diagram showing the phase characteristics; FIG. 13 is a diagram showing the frequency-gain characteristics and frequency-phase characteristics of the apparatus shown in FIGS. 6 and 7; FIG. 14 is a diagram showing the information signal having wow and flutter passing through a variable delay element. FIG. 15 is a diagram showing an example of the wow and flutter improvement characteristics of the first embodiment of the device of the present invention, and FIGS. 16A to C are diagrams showing how much the phase changes during the FIG. 1 is a diagram showing signal waveforms with wow and flutter when the first embodiment of
Fig. 7 is a diagram showing the wow/flutter frequency versus detected output voltage characteristic of the F-V converter used in a modification of the first embodiment of the device of the present invention, and Fig. 18 is a diagram showing the second embodiment of the device of the present invention. 19 is a block system diagram showing a modification of the main part of FIG. 18,
20 is a detailed block system diagram of the main part of FIG. 18, and FIGS. 21A to 21 are signal waveform diagrams for explaining the operation of FIG. 20, respectively. 5...Control head, 6...Wah and flutter detection pulse recording/reproducing head, 7...Control pulse input terminal, 16...Reproduction signal input terminal, 26...Audio signal input terminal, 28...
Bucket Brigade Device (BBD), 30
...Audio signal output terminal, 38...Wah and flutter detection signal input terminal, 36, 65, 73...
Phase comparator, 37, 40, 66, 70, 77...
VCO, 35... Phase correction circuit, 61... Memory, 63... Memory control circuit, 64... Data selector, 69, 72... Address counter, 84
...BCD decimal conversion circuit.

Claims (1)

[Claims] 1. In order to control the rotational phase of at least one of the rotating drum and the capstan, a control head records control pulses on a control track on a magnetic tape, reproduces the control pulses, and supplies them to the servo circuit. In a magnetic recording/reproducing device, a control pulse recording/reproducing head, which is formed by dividing the track width of the control head into two, and a detection pulse recording/reproducing head are arranged side by side, and the control pulse and the detection pulse are simultaneously transmitted to separate tracks. A sawtooth wave or a waveform approximating it is used to record and reproduce the detection pulse so that it is reproduced as a pulse with a high level only in the polarity opposite to the polarity of the reproduction control pulse used in the servo circuit. A magnetic recording/reproducing device characterized by recording waveform signals.