JPS6255742B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an FM receiver having a switching type FM multiplex demodulation circuit.

In an FM radio receiver, the carrier wave level is small enough to be equivalent to the noise generated in the receiver. When such noise-containing input is input to the mixer circuit of the receiver, the noise is FM-modulated by the mixer circuit. In this case, it is known that high-frequency noise components tend to increase.

Therefore, when the intermediate frequency signal that is the output of the mixer is demodulated with an FM detector, the output will have a large high-frequency noise component. This is generally called triangular noise, and its level has a wide frequency range as shown in FIG.

When receiving monaural signals, it is only necessary to consider the audible frequency range, so the area a surrounded by a small triangle up to 15KHz in Figure 2 is the FM noise amount.

On the other hand, in the case of FM stereo playback, 23
A subcarrier band of ~53KHz is also used, and the noise b contained in this subcarrier band is included in the audible frequency range due to multiplication during stereo reproduction. As a result, the amount of noise increases significantly.

Therefore, as shown in Figure 3, as the input electric field strength decreases, the S/
N (signal S to noise N ratio) deteriorates by approximately 20 dB compared to S/N during monaural reproduction.

Therefore, in FM radio receivers, it has been considered that a predetermined threshold is set for the input electric field strength to automatically switch between stereo and monaural.

However, in this system, when the input level changes around the threshold, stereo-monaural switching is always performed, making it difficult to hear. In particular, for devices such as car radios where the input electric field strength changes greatly, even if the threshold level has some hysteresis characteristics, the change in the amount of noise due to the stereo/monaural switching, the sound field There is a big change in sensation, making it extremely difficult to hear.

FIG. 1 is a circuit diagram shown in Japanese Patent Application No. 1982-8237 entitled "FM Multiplex Demodulation Circuit" prior to the present invention.

A transistor Q ₁ to which a stereo composite signal V _CPNP is applied to its base, and differential switching transistors Q ₂ and Q ₃ provided to its collector.
constitutes the main switching circuit 20, which multiplies the composite signal and the 38 KHz switching signal to obtain stereo demodulated outputs OUT ₁ and OUT ₂ of the left channel and right channel.

In order to improve the crosstalk in the main switching circuit 20, the level of the negative phase composite signal is adjusted by the separation adjustment resistors _R1 to _R3 and applied to the emitter of the transistor _Q4.
and differential switching transistors Q ₅ and Q ₆ provided at the collector thereof. That is,
Transistor Q ₄ of this sub-switching circuit 21
The multiplication output of the opposite-phase composite signal having a predetermined level formed by the 38 KHz switching signal is combined with the multiplication output of the main switching circuit 20, and as a result, the crosstalk component in the main switching circuit 20 is canceled.

The FM multiplex demodulation circuit having the above-mentioned main switching circuit and sub-switching circuit is
IEEE TRANSACTIONS ON, published October 1968
BROADCAST AND TELEVISION
RECEIVFRS VOLUME BTR―14 NUMBER
3 Reported on pp58-73. If there is no need to significantly increase the separation between the stereo demodulated outputs of the left and right channels, the sub-switching circuit 21 described above can be omitted.

According to the above-mentioned Japanese Patent Application No. 54-8237, in order to improve the S/N ratio when receiving a weak input electric field, a 38KHz switching signal is transmitted through a signal supply circuit 22 in the form of a differential amplifier circuit as shown below. This signal is supplied to the multiplex demodulation circuit.

That is, this signal supply circuit 22 is a differential transistor to which a 38KHz switching signal is applied.
Q ₇ , Q ₈ , collector load resistances R ₁₀ , R ₁₁ , a transistor Q ₉ to whose base a control voltage V _C is applied, and an emitter resistance R ₁₂ .

The detection circuit 23 generates a DC output whose level changes according to the FM intermediate frequency signal IF level,
This DC output is applied to the base of transistor _Q9 as the control voltage _Vc .

In addition, the above 38KHz switching signal is 19K
Tuning method that directly amplifies and multiplies the Hz synchronization signal (pilot signal), or 38KHz or 76K
It can be formed using a phase locked loop method (PLL circuit, etc.) in which the Hz generating circuit is synchronized with a pilot signal.

According to the circuit of this prior application described above, the gain of the differential amplifier circuit configured as the signal supply circuit 22 changes depending on the emitter current of the transistor Q ₉ , and therefore the gain of the differential amplifier circuit configured as the signal supply circuit 22 changes depending on the emitter current of the transistor Q ₉ ,
Even if the 38KHz switching signal applied to the base of _Q8 is at a constant level, the gain of the differential amplifier circuit described above is reduced in accordance with the decrease in the input level (intermediate frequency signal level), so that the demodulation circuit 2 described above
The level of the 38KHz switching signal applied to 0, 21 can be lowered.

When the level of the 38KHz switching signal in the demodulation circuits 20 and 21 becomes small, the differential switching transistors Q ₂ , Q ₃ , Q ₅ and Q ₆ operate in a linear region. Therefore, as the input level decreases, in other words, as the 38KHz switching level decreases, the crosstalk increases, the stereo separation gradually decreases, and the demodulation circuits 20, 2
1 gradually switches from stereo reproduction operation to monaural reproduction operation due to the decrease in the level of this 38KHz switching subcarrier signal.

Therefore, with the above differential amplifier circuit, the input level decreases below 38K, which is below the input electric field level V _i just before the noise during stereo demodulation becomes unpleasant.
By gradually reducing the Hz switching signal level, the noise level in the subcarrier band can be reduced, and the deterioration of the S/N ratio as shown by line S' in FIG. 3 can be prevented.

Therefore, according to the circuit of the above-mentioned prior application, even when the input electric field strength changes significantly as in the case of a car radio, sudden changes in the noise level and sound field sensation that cause harshness can be prevented. High-quality and rational reception operations can be achieved.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an FM receiver that is improved over the FM receiver according to the earlier Japanese Patent Application No. 8237/1983.

FIG. 4 shows a circuit diagram of an FM receiver using an FM multiplex demodulation circuit according to a specific embodiment of the present invention.

FM radio frequency signal V received by antenna 24
_ANTT is amplified by radio frequency amplifier 25 and applied to mixer 26 . A local oscillation signal generated by a local oscillator 27 is applied to the mixer 26 . In this way, the FM intermediate frequency signal V _IFIN is obtained from the output terminal of the mixer 26, and this FM
The intermediate frequency signal is applied to filter 28.

The broken line ICI indicates a semiconductor integrated circuit 100 for processing FM intermediate frequency signals, and its No. 1 terminal serves as an input terminal to which the FM intermediate frequency signal V _IFIN from the filter 28 is applied. The FM intermediate frequency signal applied to the first terminal as an input terminal is amplified by a first intermediate frequency amplifier 29, a second intermediate frequency amplifier 30, and a third intermediate frequency amplifier 31 connected in multiple stages. Since the first, second, and third intermediate frequency amplifiers 29, 30, and 31 connected in multiple stages operate as an FM limiter, undesired AM signal components in the FM input signal are removed by the FM limiter. be able to.

Nos. 8, 9, and 10 of the semiconductor integrated circuit 100 composed of inductors L ₁ , L ₂ , capacitor C ₂₁ , and resistor R ₂₁
The phase shift circuit 32 and gate detector 33 connected to the number terminal constitute an FM detector. this kind of
The FM detector was published in November 1967 by the IEEE
TRANSACTIONS, ON BROADCAST AND
TELEVISION RECEIVERS VOLUME BTR―
13 NUMBER 3 Reported on pp60-65.

The first, second and third intermediate frequency amplifiers 29, 3
0, 31 and the above 9th terminal are connected to the 1st and 9th terminals, respectively.
2nd, 3rd, 4th level detector 34, 35, 3
6 and 37 are connected, and these detectors 34 to 37
detects the peak value of the FM intermediate frequency signal at each part. The output signals of these peak detectors 34 to 37 are applied to a tuning meter drive circuit 38.
The output signal No. 8 is applied to the tuning meter 39 via the No. 13 terminal and the resistor R ₂₂ . These peak detectors 34-37 and tuning meter drive circuit 38 are reported in US Pat. Nos. 3,673,499 and 3,701,022.

The other output of the first level detector 34 is applied as an automatic gain control voltage to the radio frequency amplifier 25 via the 15th terminal, and the amplification gain of this amplifier is controlled.

The first output signal of the gate detector 33 is applied to an automatic frequency control amplifier 40, and the output signal of the amplifier 40 is applied to the local oscillator 27 via the No. 7 terminal. In this way, the frequency of the local oscillation signal obtained by the local oscillator 27 is controlled, so that the FM
The receiver can perform stabilized tuning without becoming detuned from the predetermined radio frequency signal.

The second output signal of the gate detector 33 is a stereo composite signal,
1 to terminal 6.

The other output signal of the fourth level detector 37 is applied to the mute drive circuit 42.
The output signal of 2 is sent to the 12th terminal. The output signal of the 12th terminal is applied to the audio output control amplifier 43 via resistors R ₂₃ and R ₂₄ and the 5th terminal. This audio output control amplifier 43
The output signal of is applied to the audio amplifier 41.

As the semiconductor integrated circuit 100 for FM intermediate frequency signal processing described above, it is possible to use an integrated circuit type CA3089 sold by RCA Corporation in the United States or an integrated circuit type HA1137W sold by Hitachi.

A broken line IC2 is a semiconductor integrated circuit 200 for FM stereo demodulation according to the present invention. The stereo composite signal at the No. 6 terminal of the semiconductor integrated circuit 100 described above is applied to the preamplifier 44a of the semiconductor integrated circuit 200 via the capacitor _C23 . Phase detector 45, low pass filter 46, DC amplifier 47, voltage controlled oscillator 48, frequency divider 4
9 and 50 are phase lock loop (PLL) circuits 5
1.

The voltage controlled oscillator 48 generates an oscillation signal having a frequency (for example, 76 KHz) that is an integral multiple of the 19 KHz pilot signal included in the stereo composite signal. Since the frequency divider 49 divides the frequency of the 76 KHz oscillation signal, two 38 KHz output signals having opposite phases and equal amplitude values are sent out on the output lines l ₁ and l ₂ . Furthermore, the frequency divider 50
divides the 38KHz signal on output line _l2 , so a 19KHz output signal is sent on output line _l3 . The phase detector 45 detects the difference between the phase of the 19KHz pilot signal in the stereo composite signal obtained from the output of the preamplifier 44 and the phase of the 19KHz output signal obtained from the frequency divider 50. The output signal of the phase detector 45 is passed through a low pass filter 46.
and a voltage controlled oscillator 48 via a DC amplifier 47
, so that the 38 KHz signal obtained from frequency divider 49 is substantially perfectly synchronized with the accurate 19 KHz pilot signal in the stereo composite signal. Therefore, the frequency divider 4
The 38KHz signal obtained from 9 is applied to a signal supply circuit 22 in the form of a differential amplifier circuit for stereo demodulation.

The frequency divider 52 and the phase detector 53 constitute a detection circuit 54 for detecting the presence or absence of a pilot signal. Frequency divider 52 is 38K on output line l ₁
Divide the Hz output signal and send the 19KHz signal to phase detector 5
Supply to 3. Therefore, the phase detector 53 detects the signal level of the 19 KHz pilot signal included in the stereo composite signal obtained from the output of the preamplifier 44, and does not substantially respond to noise components. The detection output signal of the phase detector 53 is transmitted to a lamp drive circuit 57 via a low-pass filter 55 and a DC amplifier 56. The lamp drive circuit 57 has a threshold in the input characteristics for the output signal of the DC amplifier 56, and lights up the stereo indicator lamp 58 connected to the No. 6 terminal when the output signal of the DC amplifier 56 exceeds this threshold value. urge Lighting of the stereo indicator lamp 58 indicates that the FM receiver is receiving a stereo broadcast signal, and conversely, a non-lighting of the stereo indicator lamp 58 indicates a receiving state of monaural broadcast reception.

A semiconductor integrated circuit for PLL type stereo demodulation equipped with such a lamp drive circuit was reported in Electronics pp.62-66 published in November 1971.

On the other hand, the signal supply circuit 22 is composed of transistors Q ₇ , Q ₈ , Q ₉ and resistors R ₁₀ , R ₁₁ , R ₁₂ as in the example shown in FIG. Stereo demodulator 20, 2
1 is composed of transistors Q ₁ to Q ₆ and resistors R ₁ to R ₇ in the same manner as the embodiment shown in FIG. 1, except that the load means is composed of current mirror circuits 59 and 60. ing. Further, the resistor R ₃ is connected to a separation adjustment variable resistor R ₃ ' via the No. 5 terminal. By adjusting the resistance value of this resistor R ₃ ', the separation between the demodulated output signals L _OUT and R _OUT of the left and right channels can be adjusted.

In this embodiment, the above-described semiconductor integrated circuit 100
The stereo composite signal at the No. 6 terminal of the semiconductor integrated circuit 200 is applied to a variable low-pass filter composed of a resistor R ₃₆ , a capacitor C ₂₄ , and a variable impedance circuit 62 connected through the No. 3 terminal of the semiconductor integrated circuit 200 . The output is transmitted to the preamplifier 44b of the semiconductor integrated circuit 200 via the capacitor _C25 .

The variable impedance circuit 62 includes transistors Q ₂₂ and Q ₂₃ and resistors R ₃₂ and R ₃₃ . An impedance control circuit 64 for controlling the impedance of this variable impedance circuit 62 is arranged. The impedance control circuit 64 includes a signal inverter 64 and transistors _Q24 to
It consists of Q ₂₆ and resistors R ₃₄ to R ₃₆ .

The tuning meter drive voltage V _C (V ₁₃ ) is connected to the input of the signal inverter 63 (terminal 11) through the resistor R _{25 .}
When the tuning meter drive voltage falls below a predetermined level, the impedance of the variable impedance circuit 62 is reduced to gradually lower the cutoff frequency of the variable low-pass filter.

The cutoff frequency of this variable low-pass filter is set so that it does not affect the frequency characteristics of the stereo composite signal when the tuning meter drive voltage V _C is above the predetermined level.
It is set higher than the upper limit frequency of the subcarrier, 53KHz, and is set to about 55KHz, although it is not particularly limited.

The composite signal passed through the variable low-pass filter is transferred to the semiconductor integrated circuit 20 via the capacitor _C25 .
0 preamplifier 44b.

A constant DC bias voltage V _B1 is applied to the output line _l5 of this preamplifier 44b, and a stereo composite signal is applied to the other output line _l6 .
The right channel demodulation circuit current i _R flows through the output line l ₇ of the stereo demodulators 20 and 21 as the input current of the current mirror circuit 60, and the left channel demodulation signal current i _L flows through the other output line l ₈ as the current mirror circuit. 59 input current. Current mirror circuit 59, 60
By setting the resistance values of the resistors R ₁₃ , R ₁₄ , R ₁₅ , and R ₁₆ to be equal to each other, the current values of the output currents i _R ′, i _L ′ can be made equal to the current values of the input currents i _R , i _L . Can be done. By applying a constant bias voltage V _B2 to the bases of transistors Q ₁₆ and Q ₁₇ , these transistors operate as constant power transistors.

The tuning meter drive voltage obtained at the 13th terminal of the semiconductor integrated circuit 100 is applied to the 10th and 11th terminals of the semiconductor integrated circuit 200 as a control voltage V _C .

Next, the operation of the FM receiver of the present invention with respect to level fluctuations of the antenna input voltage V _ANTT at the antenna 24 will be described below.

As shown in FIG. 5, when the antenna input voltage V _ANTT is greater than or equal to the predetermined value V _ANNT1 , the semiconductor integrated circuit 10
Automatic gain control (AGC) obtained at pin 15 of 0
The voltage V ₁₅ is the voltage gain of the radio frequency amplifier 25,
The value is controlled to be between the minimum value G _vnio and the maximum value G _vnax . In this case, it is obtained from the filter 28.
The level of the FM intermediate frequency input signal V _IFIN remains constant.

Furthermore, as shown in Fig. 5, the antenna input voltage V
When _ANTT becomes less than the predetermined value V _ANNT1 , the voltage gain of the radio frequency amplifier 25 will not increase beyond its maximum value G _vnax . Therefore, in this case, when the level of antenna input voltage V _ANTT decreases, FM
The level of the intermediate frequency input signal V _IFIN decreases. This decrease does not reach the zero level as shown by the line l _T in FIG. 5 due to noise components.

FIG. 6 shows how the semiconductor integrated circuit 100 responds to changes in the level of the FM intermediate frequency input signal V _IFIN .
Terminal voltage of terminal No. 1, No. 13, and No. 15 terminal V ₁₂ ,
It shows changes in V ₁₃ and V ₁₅ . In particular, when the FM intermediate frequency input signal V _IFIN becomes less than the first predetermined value V _IFIN1 , the S/N ratio becomes extremely poor, so the mute voltage V ₁₂ at terminal 12 rises to 1.4 volts or more and the resistance R ₂₃ becomes low. , R ₂₄ and the fifth terminal, the signal is transmitted to the audio amplifier 41 via the audio output control amplifier 43. In this way, when the FM intermediate frequency input signal becomes less than the first predetermined value, the voltage gain of the audio amplifier 41 becomes zero, and no stereo composite signal appears at the No. 6 terminal, achieving audio omiute operation. .

As shown in Figure 6, the FM intermediate frequency input signal V _IF
The level V _I at which _{the IN} level approximates the value of 80 dBμ
When _FIN2 or less, the decrease in the S/N ratio during stereo demodulation cannot be ignored. In this embodiment, when the FM intermediate frequency input signal V _IFIN is 100 dBμ or more, the tuning meter drive voltage V ₁₃ (V
_C ) is constant, so the resistance _R27 at terminal 10
~R ₂₉ A constant control current I _C corresponding to this constant meter drive voltage V ₁₃ flows through the DC path of the diode-connected transistor Q ₁₈ . In this case, since the voltage gain of the differential amplifier circuit as the signal supply circuit 22 is controlled to a high value, a high level 38 KHz switching subcarrier signal is transmitted from the signal supply circuit 22 to the demodulation circuits 20 and 21. Thus, in this case, the demodulation circuits 20 and 21 perform a reproduction operation of stereo demodulation.

On the other hand, the level of the FM intermediate frequency input signal V _IFIN is
When the voltage drops below 100 dBμ, the current value of the control current I _C decreases as the level of V _IFIN decreases.
Therefore, the voltage gain of the signal supply circuit 22 decreases, and the level of the 38KHz switching signal transmitted to the demodulation circuits 20 and 21 decreases. Thus,
Stereo separation in demodulation circuits 20 and 21 gradually decreases.

As the tuning meter drive voltage V _C continues to decrease, the diode-connected transistor Q ₁₈ becomes non-conductive and the current value of the control current I _C becomes substantially zero. Then, the transistor of the signal supply circuit 22
Q ₉ becomes non-conductive, and transmission of the 38KHz switching signal from the signal supply circuit 22 to the demodulation circuits 20 and 21 is prohibited. In this way, the demodulation circuits 20 and 21 perform a monaural reproduction operation.

Therefore, as shown in Figure 7, when the FM intermediate frequency input signal V _IFIN drops below 100 dBμ, the S/N ratio changes from S/N ratio L ₁ during stereo playback to S during monaural playback along the path of line S'. /N ratio _L2 . Along with this, the stereo separation _Sep gradually decreases as shown by the line _L3 .

And the FM intermediate frequency input signal V _IFIN is about 50dB
When the tuning meter drive voltage V _C (V ₁₅ ) applied to the input of the signal inverter 63 decreases below μ
The base voltage V _B3 of the transistor Q ₂₄ constituting the impedance control circuit 64 increases due to the decrease in the impedance control circuit 64 . Therefore, the FM intermediate frequency input signal V _IFIN
As the level of Q ₂₄ decreases, the collector current of transistor Q ₂₄ increases, and _the base-emitter forward voltage and
As the voltage drop across R ₃₆ increases, the conductivity of transistors Q ₂₂ and Q ₂₃ in the variable impedance 62 increases, so the emitter input resistance of transistors Q ₂₂ and Q ₂₃ decreases, and the cutoff frequency of the variable low-pass filter increases. decrease.

Therefore, if the level of the FM intermediate frequency input signal V _IFIN decreases significantly, the high frequency noise component included in the composite signal is removed by the capacitor C ₂₄ and the low impedance variable impedance 62. Since the transmission is inhibited by flowing the signal to the ground point through the signal line, the S/N ratio can be further improved as shown by the line L ₂ ' in FIG.

That is, in FIG. 7, when the FM intermediate frequency input signal V _IFIN is around 50 dBμ, the S/N ratio changes from point P' to point P due to the monaural reproduction operation by prohibiting the transmission of the 38 KHz switching signal. The FM intermediate frequency input signal V _IFIN has been improved as follows.
Immediately before an audio mimic of around 35 dBμ is applied, a point indicating the S/N ratio in monaural playback is determined by the operation of a variable low-pass filter.
It is something that is improved from point R' to point R.

Further, since the variable low-pass filter is provided on the input side of the stereo demodulation circuit, it can be configured with one variable low-pass filter.

For example, by providing a variable low-pass filter on the output side of the stereo demodulation circuit, it is possible to improve the S/N ratio in the same way as described above, but variable low-pass filters must be provided on the outputs of both the left and right channels. However, the disadvantage is that the circuit becomes complicated.

Furthermore, providing the variable low-pass filter in this embodiment on the input side of the stereo demodulation circuit not only simplifies the circuit configuration, but also
It also has the following advantages:

For example, if the FM intermediate frequency input signal V _IFIN is 100dB
When the level is higher than μ, due to primary interference between two broadcasting stations whose broadcasting frequencies are extremely similar.
Beat components in the high frequency band from 150KHz to 450KHz
Appears in the output of the FM detector.

In conventional FM receivers, the beat signal in the audible frequency band is stereo demodulated due to secondary signal interference between the beat component in the high frequency band and the odd harmonic components (114KHz, 190KHz...) of the 38KHz switching signal. There was a problem arising from the output of the circuit.

In this embodiment, a variable low-pass filter is provided on the input side of the stereo demodulation circuit, and the FM intermediate frequency input signal V _IFIN is
Even when it is 100 dBμ or more, the cutoff frequency is set to about 55 KHz, which prevents the transmission of beat signals in the high frequency band to the stereo demodulation circuit, thereby preventing the generation of the above-mentioned harsh beat signals in the audio frequency band. can be reduced.

Note that when a variable low-pass filter is provided on the output side of the stereo demodulation circuit, beat components below its cutoff frequency cannot be reduced.

Furthermore, in this embodiment, the high-frequency noise reduction operation by the variable low-pass filter is performed after the stereo demodulation circuit shifts to monaural reproduction operation, so there is no problem in attenuating the subcarrier band signal. There isn't.

In other words, when the stereo demodulation circuit is performing stereo demodulation operation, if the subcarrier band signal is attenuated, the signal will be synchronized with the pilot signal.
This is because a problem arises in that a phase shift occurs between the 38KHz switching signal and the subcarrier band signal, making it impossible to perform accurate stereo demodulation.

Furthermore, in this embodiment, since the PLL circuit operates with a composite signal that does not pass through a variable low-pass filter, the pilot signal detection operation can be continued even when switching to monaural.

Therefore, it is possible to receive stereo broadcasts even after setting the threshold in the input characteristics of the DC amplifier circuit 56 low and switching from stereo playback to monaural playback to improve the S/N ratio as described above. A lamp display can be displayed to indicate the following.

As a result, it is possible to prevent the unsightly phenomenon of the lamp blinking, which occurs when a stereo broadcast is forcibly switched to monaural when a weak input electric field is applied, as in the prior art.

According to another preferred embodiment of the invention, a transistor Q ₁₉ for forced stereo-monaural switching is connected to the base of the transistor Q ₉ of the signal supply circuit 22.

At the location where the FM receiver is receiving the monaural broadcast signal, the 19KHz pilot signal is no longer included in the composite signal of the preamplifier 44, so the pilot signal detection circuit 54 sends a low level output signal to the No. 8 terminal. I come to do it. The output of the DC amplifier 56 becomes low level, and this low level output signal has a value below the input threshold of the lamp drive circuit 57, so the lamp drive circuit 57 controls the stereo indicator lamp 58 to a non-lighting state. This indicates the reception status of a monaural broadcast signal. At the same time, the lamp drive circuit 57 sends a high-level output signal to the output line _l4 to turn on the switching transistor _Q19 .

Therefore, irrespective of the level of the meter drive voltage _V13 (the level of the FM intermediate frequency signal V _IFIN ) supplied to terminal No. 10, the transistor _Q9 is forcibly turned off by turning on the switching transistor _Q19 . I am made to do so. In this way, the 38KHz switching signal is no longer transmitted to the demodulation circuits 20 and 21, so the demodulation circuits 20 and 21 perform a monaural reproduction operation and the S/N ratio changes from line _L1 to line _L2 as shown in FIG. Forced to switch.

Similarly to the above, when the FM intermediate frequency input signal V _IFIN becomes approximately 50 dBμ or less, the S/N ratio is improved by lowering the cutoff frequency of the variable low-pass filter.

The present invention is not limited to the embodiments described above, and the FM detection output signal may be supplied to a variable low-pass filter and a PLL circuit through a well-known noise suppressor. Furthermore, the variable low-pass filter may be provided on the input side of the stereo demodulation circuit. In this case, only one preamplifier can be used.

Further, the variable low-pass filter may use a variable capacitance element (for example, a paractor) or may be combined with a variable resistance circuit.

Furthermore, the variable impedance circuit can be modified in various ways, for example, as shown in FIG.
The output of Q ₄₃ and the output of a common emitter amplification transistor Q ₄₀ that amplifies the input signal passed through a low-pass filter consisting of a resistor R ₄₀ and a capacitor C ₄₀ are connected to differential transistors Q ₄₁ , Q ₄₂ and Q ₄₄ , Q ₄₅ may be synthesized. In this circuit, as the control voltage V ₁₃ decreases, the conductivity of the transistor Q ₄₂ increases, so the signal component passing through the low-pass filter increases and the effective cutoff frequency decreases.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram proposed in Japanese Patent Application No. 54-8237, which is related to the earlier application, Figure 2 is an FM triangular noise characteristic diagram, and Figure 3 explains the earlier application shown in Figure 1. Figure 4 is a circuit diagram showing an embodiment of the present invention; Figure 5 is a characteristic diagram showing antenna input voltage vs. FM intermediate frequency input signal characteristics; Figure 6 is a characteristic diagram showing antenna input voltage vs. FM intermediate frequency input signal characteristics. A characteristic diagram showing changes in each terminal voltage in the circuit of Fig. 4 due to level changes of the FM intermediate frequency input signal, Fig. 7 a characteristic diagram showing the technical effects of the embodiment of Fig. 4, and Fig. 8 a variable FIG. 3 is a circuit diagram showing another embodiment of a low-pass filter. 20, 21... demodulation circuit, 22... signal supply circuit,
34, 35, 36...Detection circuit, 54...Pilot signal detection circuit, 57...Indicator drive circuit, 5
8...Stereo indicator.

Claims (1)

[Claims] 1. An FM intermediate frequency amplifier to which an FM intermediate frequency signal is applied, and an FM intermediate frequency amplifier to which an FM intermediate frequency signal is applied;
An FM receiver including an FM detector for performing FM detection, means for generating a 38KHz switching signal, and a stereo demodulation circuit to which the detection output of the FM detector and the switching signal are applied and output a stereo demodulation signal to the output. In the apparatus, a level detection means for detecting the level of the FM intermediate frequency amplified signal, a noise removal means for removing high-frequency noise in a signal transmission path including the FM detector and the stereo demodulation circuit, and It comprises a switching signal supply means connected between means for generating a switching signal and the stereo demodulation circuit, and the switching signal supply means detects the switching signal when the level of the level detection means is below a first level. An FM receiving device that starts a gain reduction operation, and the noise removal means starts the operation when the level of the level detection means is equal to or lower than a second level that is lower than the first level. . 2. The FM receiving device according to claim 1, wherein the noise removing means is a variable low-pass filter. 3. In the FM receiving device according to claim 1, the switching signal supply means is constituted by a differential amplifier having a variable constant current source, and the variable constant current source is controlled by the level detection means. An FM receiving device characterized by: