GB2040145A - Improvements in F.M. receivers - Google Patents

Abstract

Stereophonic composite signals and switching signals (of 38 KHz) are applied to a stereophonic demodulator circuit (having a main switching circuit (20) and a sub-switching circuit (21)), and left-channel and right-channel demodulated outputs are obtained from terminals (OUT1 and OUT2). As the output signals of an IF detector (23) are applied to the switching signal feeding circuit (22), the voltage gain of the signal feeding circuit is controlled so that as the IF level is decreased, the level of the switching signals is gradually decreased and the separation between the left-channel and right-channel demodulated outputs of the stereophonic demodulator circuit (20, 21) is gradually decreased, such that the S/N ratio is increased. <IMAGE>

Description

SPECIFICATION Improvements in F.M. receivers The present invention relates to an F.M. receiver having an F.M. multiplex demodulator circuit of the switching system.

In an F.M. radio receiver, the small level of carrier wave may become equal to the noise level gener ated in the receiver. The inputs containing much noise will then be fed to a mixer circuit of the receiver so that the frequency of the noise is mod ulated. In this case, it has been known that the noise components tend to become great in the highfrequency regions.

Hence, if the intermediate-frequency signals which are the outputs of the mixer are demodulated by an F.M. detector, the resulting outputs contain large noise components in the high-frequency regions.

This is usually called triangular noise with its level increasing with an increase in the range of frequency as is shown in Fig. 2 of the accompanying drawings.

During monaural reception, the range of audible frequencies needs to be taken into consideration.

Therefore, zones a of Fig. 2 in the form of small triangles extending from zero up to 15 KHz represent the magnitude of the F.M. noise.

In the case of F.M. stereophonic reproduction, on the other hand, subcarrier bands of from 23 to 53 KHz are also used, whereby the noise contained in zones b in the subcarrier bands is transferred into the range of audible frequencies due to multiplication during the stereophonic reproduction. As a result, the magnitude of the noise is greatly increased.

Therefore, as the intensity of the input electric field decreases, the S/N ratio (signal-to-noise ratio) during the stereophonic reproduction deteriorates by about 20 dB as compared with the S/N ratio during monaural reproduction, as shown in Fig. 3 of the accompanying drawings.

With regard to FM radio receivers, therefore, it has been proposed to employ a system which automatically switches the reception into either stereophonic reception or monaural reception by setting a predetermined threshold value with respect to the intensity of the input electric field.

With such a system, however, when the input level changes in the vicinity of the threshold value, the receiver is frequently switched between sterephonic reception and monaural reception, causing undesirable effects. In particular, with regard to car radios which are subjected to a great change in the intensity of the input electric field, the switching between stereophonic reception and monaural reception results in great change in the magnitude of the noise as well as a great change in the perception of the quality of the sound even though a reasonable amount of backlash may be provided in the threshold switching system.

In order to overcome the above referred to problems, it is an object of the present invention to provide an FM receiver which can be made up of integrated circuits by reducing the change in the noise quantity and reducing the change in the quality of the sound with respect to the strength of the input electric field.

According to the present invention there is pro vided an FM receiver including; a demodulator cir cuit for reproducing left-channel demodulated out puts and right-channel demodulated outputs from stereophonic composite signals and switching sign als of a first given frequency; a signal feeding circuit for feeding said switching signals of said first given frequency to said demodulator circuit; and a detector circuit for obtaining detection signals corres ponding to a level of the FM intermediate-frequency signals; wherein said detection signals are fed to said signal feeding circuit in order to control the gain of said signal feeding circuit, and the level of the switching signals in said first given frequency fed from said signals ci rcuit to said demodulator circuit is gradually decreased with the decrease in the level of said FM intermediate-frequency signals.

The present invention will now be described in greater detail by way of example with reference to the accompanying drawings, wherein: Fig. 1 is a circuit diagram illustrating a preferred embodiment of an FM receiver; Fig. 2 is a graph illustrating FM triangular noise; Fig. 3 is a graph illustrating the strength of the input electric field versus S/N ratios to demonstrate the effects of the present invention; Fig. 4A and Fig. 4B are detailed circuit diagrams illustrating the embodiment shown in Fig. 1 as applied to an FM multiplex demodulator circuit; Fig. 5 is a graph showing antenna input voltage versus FM intermediate-frequency input signals; Fig. 6 is a graph showing the change in voltage at the terminals responsive to the change in the level of the FM intermediate-frequency input signals; and Fig. 7 is a graph demonstrating the technical effects of the embodiment shown in Fig. 4.

Referring to Fig. 1, a main switching circuit 20 consists of a transistor Q, a stereophonic composite signal Vcomp being applied to the base electrode thereof, and differential switching transistors Q2 and Q3 which are connected to the collector electrode of the transistor Q1. The composit signal is multiplied by a switching signals of 38 KHz to obtain stereophonic demodulated outputs OUT1 and OUT2 of the left and right channels.

In order to improve the crosstalk in the main switching circuit 20, a sub-switching circuit 21 is formed by a transistor Q4 the composite signal of reversed phase after its level is adjusted by separation-adjusting resistors R1 to R2 being applied to the emitter electrode thereof, and differential switching transistors Q5 and Q6 connected to the collector electrode of the transistor Q4.The output obtained by multiplying the reverse-phase composite signal having a predetermined level formed by the transistor Q4 of the sub-switching circuit 21 by the switching signal of 38 KHz, is synthesized together with the multiplied output of the main switching circuit 20, so that the crosstalk compo- nents in the main switching circuit 20 are cancelled.

An FM multiplex demodulator circuit having the above described main switching and sub-switching circuit has been disclosed in the IEEE TRANSAC TIONS ON BROADCASTANDTELEVISION RECEIV ERS, VOLUME BTR-14, NUMBER 3, pp. 58-73, issued October 1968.

The above sub-switching circuit 21 may be omitted when there is no need of extremely enhancing the separation of stereophonic demodulated outputs between the left and right channels.

In particular, in order to improve the S/N ratio when weak electric signals are being received according to the present invention, the switching signals of 38 KHz are fed to the multiplex demodulator circuit via a signal feeding circuit 22 being a type of differential amplifier circuit. The signal feeding circuit 22 consists of differential transistorx Q7 and Qa to which are applied switching signals of 38 KHz, collector load resistors R1, and R11, a transistor Og a control voltage being applied to the base electrode thereof and an emitter resistor R12.

A detector circuit 23 produces a D.C. output whose level changes in response to the level of the FM intermediate frequency signals IF. The D.C. output is applied as the control voltage Vc to the base electrode of the transistor Og.

The switching signals of 38 KHz can be obtained by a tuning system which directly amplifies and multiplies synchronizing signals (pilot signals) of 19 KHz or by a phase-locked loop system (PLL circuit) which synchronizes an oscillation circuit of 38 KHz or76 KHz relying upon the pilot signals.

The gain of the differential amplifier circuit constructed as the signal feeding circuit 22 varies in response to the emitter current of the transistor Qg.

Therefore, even when the switching signals of 38 KHz applied to the base electrodes of the transistors Q, and Q8 are of the constant level, the level of the switching signals of 38 KHz applied to the demodulator circuits 20 and 21 can be decreased by reduc ng the gain of the differential amplifier circuit in response to the decrease of the input level (level of the intermediate-frequency signals).

As the level of the switching signals of 38 KHz decreases in the demodulator circuits 20 and 21, the differential switching transistors Q2, 03, Og and Q6 operate in their linear regions. In other words, the crosstalk components increase with the decrease in the switching level of 38 KHz whereby the degree of stereophonic separation is gradually decreased, and the demodulator circuits 20 and 21 are gradually changed from the operation of stereophonic reproduction to the operation of monaural reproduction due to the decrease in the level of the switching subcarrier wave signals of 38 KHx.

Therefore, the noise level in the subcarrier band can be reduced by gradually decreasing the level of switching signals of 38 KHz responsive to the decrease in the input level which is smaller than an inpul electric field level Vi below which the noise level of the stereophonic demodulation becomes offensive. Thus, the S/N ratio can be prevented from deteriorating as indicated by a line S' shown in Fig.

3.

Accordingly, a sudden change in the noise level which becomes offensive to the ear and a sudden change in the quality of the sound can be prevented even when the magnitude of the input electric signals vary greatly as will be often encountered with car radios, thus making it possible to realize an ideal receiving operation maintaining high quality.

Referring now to the detailed circuit diagram of Figs. 4A and 4B relating to an FM receiver employing an FM multiplex demodulator circuit, the FM radiofrequency signals VANTT received by an antenna 24 are amplified by a radio-frequency amplifier 25 and are applied to a mixer 26 to which have been applied local oscillation signals generated by a local oscillator 27. Thus, F.M. intermediate-frequency signals VIFIN are obtained from the output terminals of the mixer 26 and are fed to a filter 28.

A broken line IC1 represents a semiconductor integrated circuit 100 for processing F.M.

intermediate-frequency signals, in which a first terminal receives the F.M. intermediate-frequency signals V,,,, from the filter 28. The F.M.

intermediate-frequency signals applied to the first terminal which is the input terminal are amplified by means of a first intermediate-frequency amplifier 29, a second intermediate-frequency amplifier 30 and a third intermediate-frequency amplifier 31 which are connected in cascade. The first, second and third intermediate-frequency amplifiers 29, 30 and 31 which are connected in cascade, operate as an F.M.

limiter which removes undesired A.M. signal components from the F.M. input signals.

An F.M. detector consists of a phase shifting circuit 32 comprising inductors L, and L2, a capacitor C and a resistor R21 which are connected to eighth, ninth and tenth terminals of the semiconductor integrated circuit 100, and a gate detector 33. An F.M.

detector of this type has been disclosed in IEEE TRANSACTIONS ON BROADCAST AND TELEVISION RECEIVERS, VOLUME BTR-13, NUMBER 3, pp. 60-65 issued November, 1967.

To the first, second and third intermediatefrequency amplifiers 29,30, 31 and to the ninth terminal are connected first, second, third and fourth level detectors 34,35,36 and 37 which detect peak values of the F.M. intermediate-frequency signals at each of the sections. The output signals of the peak detectors 34 to 37 are applied to a tuning meter drive circuit 38 which produces an output signal that will be applied to a tuning meter 39 via a thirteenth terminal and a resistor R22 (Fig. 4B). The peak detectors 34 to 37 and the tuning meter drive circuit 38 have been disclosed in U.S. Patent Nos. 3,673,499 and 3,701,022.

Another output of the first level detector 34 is applied as an automatic gain control voltage to the radio-frequency amplifier 25 via a fifteenth terminal in order to control the amplification gain of the amplifier 25.

A first output signal of the gate detector 33 is applied to an automatic frequency control amplifier 40 which produces an output signal that will be applied to the local oscillator 27 via a seventh terminal. Thus, the frequency of local oscillation signals from the local oscillator 27 are controlled, so that the F.M. receiver stably carries out the tuning operation without being detuned from the predetermined radio-frequency signals.

A second output signal from the gate detector 33 is a stereophonic composite signal which is applied to a sixth terminal via an audio amplifier 41.

Another output signal of the fourth level detector 37 is applied to a mute drive circuit 42 which pro duces an output signal that is applied to a twelfth terminal. The output signal of the twelfth terminal is applied to an audio mute control amplifier 43 via resistor R22 and R24 and a fifth terminal. The output signal of the audio mute control amplifier 43 is fed to the audio amplifier 41.

The above-described semiconductor integrated circuit 100 for processing F.M. intermediatefrequency signals, can be constituted by an inte grated circuit CA 3089 sold by the RCA corporation of the United States of America, or an integrated circuit HA 1137W made by Hitachi, Limited.

A broken line IC2 represents a semiconductor integrated circuit 200 for F.M. stereophonic demod ulation. The stereophonic composite signal at the sixth terminal of the semiconductor integrated circuit 100 is applied to a preamplifier 44 of the semiconductor integrated circuit 200 via a capacitor C23.

A phase-locked loop (PLL) circuit 51 is constituted by a phase detector 45, a low-pass filter 46, a D.C. amp lifier47, a voltage-controlled oscillator 48, and frequency dividers 49 and 50.

The voltage-controlled oscillator 48 generates oscillation signals of a frequency (for example, 76 KHz) which is an integer times as great as the frequency, i.e. 19 KHz of the pilot signals contained in the stereophonic composite signals. The frequency divider 49 divides the frequency of the oscillation signals of 76 KHz. Hence two output signals of 38 KHz of opposite phases but of an equal amplitude are applied to output lineszl andz2. Further, the frequency divider 50 divides the frequency of a signal of 38 KHz on the output linez2. Hence, an output signal of 19 KHz is sent onto an output linez3.

The phase detector 45 detects the difference between the phase of the pilot signal of 19 KHz in the stereophonic composite signals obtained from the preamplifier 44 and the phase of the output signal of 19 KHz obtained from the frequency divider 50. Since the output signal of the phase detector45 is applied to the voltage-controlled oscillator 48 via the lowpass filter 46 and the D.C. amplifier 47, the signal of 38 KHz from the frequency divider 49 is substantially in perfect synchronism with the pilot signal having a precise frequency of 19 KHz in the stereophonic composite signals. Therefore, the signals of 38 KHz obtained from the frequency divider 49 is applied to the signal feeding circuit 22 which is in the form of a differential amplifier as mentioned above.

A detector circuit 54 for detecting the presence or absence of pilot signals, consists of a frequency divider 52 and a phase detector 53. The frequency divider 52 divides the frequency of the output signal of 38 KHz on the output linezl and feeds a signal of 19 KHz to the phase detector 53. The phase detector 53 thus detects the signal level of pilot signal of 19 KHz contained in the stereophonic composite signals obtained from the preamplifier 44, and does not substantially respond to any noise components. The detection output signal of the phase detector 53 is transmitted to a lamp drive circuit 57 via a low-pass filter 55 and a D.C. amplifier 56.The lamp drive cir cuit 57 has a threshold value in the input characteris tics for the output signals from the D.C. amplifier 56, and causes a stereophonic indicator lamp 58 con nected to a sixth terminal to be illuminated when the output signal of the D.C. amplifier 56 is greater than the threshold value. The stereophonic indicator lamp 58 when illuminated, indicates that the F.M. receiver is receiving stereophonic broadcast signals. When the indicator lamp 58 is not illuminated, it indicates that monaural broadcast signals are being received.

The semiconductor integrated circuit of the Pll type for demodulating the stereophonic signals equipped with such a lamp drive circuit, has been disclosed in Electronics, pp. 62-66 issued November 22,1971.

The signal feeding circuit 22 is identical with that shown in Fig. 1 and consists oftransistors Q7, 0, and 09, and resistors R10, R" and R,2. Stereophonic demodulators 20 and 21 consist of transistors Q, to Q6 and resistors R, to R7 as disclosed in the circuit of Fig. 1 except that the load means are constituted by current mirror circuits 59 and 60. A resistor R2 is con nected via a fifth terminal to a variable resistor R3', for adjusting the separation. By adjusting the value of resistance of the resistor R2,, the separation bet ween the demodulated output signals LOUT and ROUT of the left and right channels can be adjusted.

A predetermined D.C. biasing voltage B8 is applied to an output linez5 of the preamplifier, and stereophonic composite signals are fed to the other output linez6. A demodulated signal current iR of the right channel flows to an output linez7 of the stereophonic demodulators 20 and 21 as an input current of a current mirror circuit 60, and a demod ulated signal current iL of the left channel flows to the other output linez8 as an input current of a cur rent mirror circuit 59. By selecting the values of resistance of the resistors R12, R14, R19 and R16 of the cur rent mirror circuits 59 and 60 to be equal to each other, output currents iR' and iL' can be selected to be equal to the input currents iR and iL.Transistors Q16 and Q17 operate as constant current source transistors, their base electrodes being applied with a constant biassing voltage V82.

A tuning meter drive voltage produced at a thirteenth terminal of the semiconductor integrated circuit 100 is applied as a control voltage Vc to tenth and eleventh terminals of the semiconductor integrated circuit 200.

The operation of the F.M. receiver in response to the change in the level of antenna input voltage VANTT induced in the antenna 24 will now be described in greater detail.

When the antenna input voltage VANTT is greater than a predetermined value VANTT1 as illustrated in Fig. 5, an automatic gain control (AGC) voltage V18 produced at the fifteenth terminal of the semicon ductor integrated circuit 100 controls the voltage gain of the radio-frequency amplifier 25 to lie between a minimum value Gvmin and a maximum value Gvmax. In this case, the level of the F.M.

intermediate-frequency input signals VIFIN obtained from the filter 28 remains constant.

Furthermore, when the antenna input voltage VANNT iS decreased below the predetermined value VANTTl as shown in Fig. 5, the voltage gain of the radio-frequency amplifier 25 does not increase beyond the maximum value Gvmax. Accordingly, when the level of the antenna input voltage VANTT iS decreased, the level of the F.M. intermediatefrequency input signals VIFIN is also decreased. However, due to the noise components, the level never decreases to zero as indicated by a linezT in Fig. 5.

Fig. 6 shows changes of voltages V,2,V,3 and Vrs at the twelfth, thirteenth and fifteenth terminals of the semiconductor integrated circuit 100 in response to the change in the level of the F.M. intermediatefrequency input signals VIFIN. In particular, the S/N ratio decreases drastically if the F.M. intermediatefrequency input signal VIFIN becomes smaller than the first predetermined value VIFIN1. Therefore, the mute voltage V,2 of the twelfth terminal which has exceeded 1.4 volts is fed to the audio amplifier 41 via resistors R22 and R24, the fifth terminal and audio mute control amplifier 43.Thus, as the level of the F.M. intermediate-frequency input signals decrease below the first predetermined value VIFIN1, the voltage gain of the audio amplifier 41 becomes zero, and no stereophonic composite signal appears at the sixth terminal, so that audio mute operation is effected.

On the other hand, when the level of the F.M.

intermediate-frequency input signals VIFIN iS decreased below the level VIFIN2 which is approxi mately 80 db,a the decrease in the S/N ratio during the stereophonic demodulation no longer becomes negligible. Accordingly, when the level of the F.M.

intermediate-frequency input signals VIFIN is greater than 100 db,m, a tuning meter drive voltage Vc(V13) at the thirteenth terminal remains constant. There fore, a control current Ic corresponding to the con stant meter drive voltage V,3 flows along a D.C. path consisting of resistors R27 to R26 and a transistor Q.8 having its base and collector electrodes intermediated to act as a diode, which are located at the tenth terminal of the semiconductor integrated circuit 200.

In this case, the voltage gain of the differential amplifier circuit which is the signal feeding circuit 22 is controlled to acquire a large value. Hence, switching subcarrier wave signals of 38 KHz of a high level are fed from the signal feeding circuit 22 to the demodulator circuits 20 and 21. The demodulator circuits 20 and 21 operate to reproduce the stereophonic demodulated signals.

On the other hand, when the level of the F.M.

intermediate-frequency input signals VIFIN iS decreased below 100 db,a, the control current Ic decreases with a decrease in the level of the signals VIFIN. Accordingly, the voltage gain of the signal feeding circuit 22 is decreased, so that the level of the switching signals of 38 KHz transmitted to demodulator circuits 20 and 21 is decreased. Thus, the stereophonic separation in the demodulator circuits 20 and 21 is gradually decreased.

As the tuning meter drive voltage Vc further decreases, the transistor Q.8 which is connected in diode configuration is rendered non-conductive, whereby the control current Ic becomes substantially zero. The transistor Q, of the signal feeding circuit 22 is then rendered non-conductive, and the switching signals of 38 KHz are prevented from being sent from the signal feeding circuit 22 to the demodulator circuits 20 and 21. Thus, the demodulator circuits 20 and 21 reproduce the monaural signals.

Accordingly, as the level of the F.M. intermediatefrequency input signals VIFIN decreases below 100 dB,a, the S/N ratio gradually shifts from the S/N ratio L, of the stereophonic reproduction to the S/N ratio L2 of the monaural reproduction along a line S' as illustrated in Fig. 7. Accompanying this shift, the stereophonic separation Sep gradually decreases as indicated by a line L3.

According to the preferred embodiment of the F.M. receiver, the fourteenth and fifteenth terminals of the semiconductor integrated circuit 200 are connected to the fourth and third terminals, respectively, via capacito C24 and C26, and the third and fourth terminals are connected to a first variable impedance circuit 61 and to a second variable impedance circuit 62, respectively.

The first variable impedance circuit 61 consists of transistors Q20 and Q2r, and resistors R20 and R21, and the second variable impedance circuit 62 consists of transistors Q22 and Q23, and resistors R22 and R22.

An impedance control circuit 64 is provided to control the impedances of the first variable impedance circuit 61 and the second variable impedance circuit 62. The impedance control circuit 61 consists of a signal inverter 63, transistors 024, Q25 and 026, and resistors R24, R25 and R26. The tuning meter drive voltage Ve (V,3) has been applied to the input terminal (eleventh terminal) of the signal inverter 63, so that the base electrode of the transistor Q24 is fed with a control voltage V82 of which the level rises with the decrease in the level of the F.M. intermediatefrequency input signals VIFIN.

Therefore, as the level of the F.M. intermediatefrequency input signals VIFIN drastically decreases, the collector current of the transistor Q24 increases so that the forward voltage V8, across the base and emitter electrodes of the transistors Q2s and Q26 which are connected in diode configuration is increased. This causes an increase in the conductivity of the transistors Q20 and Q2r in the first variable impedance circuit and the transistors 022 and Q23 in the second variable impedance circuit 62, so that input resistances of the emitters ofthe transistors are decreased.

Hence, owing to the employment of the first and second variable impedance circuits 61 and 62, when the level of the F.M. intermediate-frequency input signals VIFIN is greatly decreased, high-frequency noise components in the output signals at the fourteenth and fifteenth terminals flow into the earth point via capacitors C24 and C25, and first and second variable impedance circuits 61 and 62 of small impedances, such that the S/N ratios are further increased, as indicated by lines L,' and L2, in Fig. 7.

According to another preferred embodiment, a transistor Qxg for forcibly switching the stereophonic-monaural function is connected to the base electrode of the transistor 0, of the signal feeding circuit 22.

When the F.M. receiver is receiving monaural broadcast signals, pilot signals of 19 KHz are no longer contained in the composite signals of the preamplifier 44. A pilot signal detector circuit 54 produces an output signal of a small level to the eighth terminal. Then, the level of the output of the D.C. amplifier 56 is decreased to a value smaller than an input threshold value of the lamp drive circuit 57.

Hence, the lamp drive circuit 57 turns off the stero indicator lamp 58 thereby indicating that monarual broadcast signals are being received. At the same time, the lamp drive circuit 57 produces an output signal at a high level onto the output linez4 in order to render the switching transistor 0,, conductive.

Therefore, irrespective of the level of the meter drive voltage V12 (or level of the F.M. intermediatefrequency signals VIFIN) fed to the tenth terminal, the switching transistor Q,g which is turned on causes the transistor 0, to be forcibly turned off. Thus, the switching signals of 38 KHz are no longer transmitted to the demodulator circuits 20, 21 so that the demodulator circuits 20 and 21 execute the operation for reproducing monaural signals, whereby the S/N ratio is forcibly changed from the line L, to line L2 as shown in Fig. 7. When the F.M. receiver is receiving monaural broadcast signals, the demodulator circuits 20 and 21 reproduce monaural signals irrepespective of the level of the F.M. intermediatefrequency signals, enabling the S/N ratio to be further increased.

Claims (9)

1. An F.M. receiver including: a demodulator circuit for reproducing left-channel demodulated outputs and right-channel demodulated outputs from stereophonic composite signals and switching signals of a first given frequency; a signal feeding circuit for feeding said switching signals of said first given frequency to said demodulator circuit; and a detector circuit for obtaining detection signals corresponding to a level of the F.M. intermediatefrequency signals; wherein said detection signals are fed to said signal feeding circuit in order to control the gain of said signal feeding circuit, and the level of the switching signals of said first given frequency fed from said signal feeding circuit to said demodulator circuit is gradually decreased with the decrease in the level of said F.M. intermediatefrequency signals.

2. An F.M. receiver according to claim 1, wherein said demodulator circuit includes a main switching circuit, a sub-switching circuit and a separation adjusting circuit.

3. An F.M. receiver according to claim 2, further including a subcarrierwave generator for generating said switching signals of said first given frequency which are substantially in synchronism with pilot signals of a second given frequency contained in the stereophonic composite signals, wherein said switching signals of said first given frequency are fed from said subcarrierwave generator to said demodulator circuit via said signal feeding circuit.

4. An F.M. receiver according to claim 3, further including a meter drive circuit which receives output signals of said detector circuit and which generates a tuning meter drive voltage, wherein said tuning meter drive voltage is applied to a tuning meter, and is further applied to said signal feeding circuit to control the gain of said signal feeding circuit.

5. An F.M. receiver according to claim 3 or4, further including a first variable impedance circuit and a second variable impedance circuit which are respectively connected to a first output terminal and a second output terminal to which can be applied said left-channel demodulated outputs and rightchannel demodulated outputs, and an impedance control circuit which operates so as to decrease the impedances of said first and second variable impedance circuits in response to the decrease in the level of the F.M. intermediate-frequency signals.

6. An F.M. receiver according to any one of the preceding claims, further including: a pilot signal detector circuit for detecting the level of pilot signals of said second given frequency contained in the stereophonic composite signals; and an indicator drive circuit which has a threshold level in the input characteristics, which causes the stereo indicator to be turned off when the output level of said pilot signal detector circuit is smaller than said threshold level, and which at the same time causes the gain of said signal feeding circuit to be decreased so that the switching signals of said first given frequency are prevented from being transmitted to said demodulator circuit.

7. An F.M. receiver according to any one of the preceding claims, wherein said first given frequency is 38 KHz.

8. An F.M. receiver according to any one the preceding claims 3 to 5, wherein said second given frequency is 19KHz.

9. An F.M. receiver constructed and arranged to operate substantially as herein described with reference to and as illustrated in the accompanying drawings.