JPH0355057B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an FM receiver having a switching type FM multiplex demodulation circuit.

In an FM radio receiver, the carrier wave level is small enough to be equivalent to the nozzle generated in the receiver. When such noisy input is input to the mixer circuit of the receiver, the mixer circuit modulates the nozzle with FM. In this case, it is known that the high-frequency nozzle component becomes large.

Therefore, when the intermediate frequency signal that is the output of the mixer is demodulated with an FM detector, the output will have a large high-frequency noise component. This is generally called triangular noise, and its level increases as the frequency range widens, as shown in FIG.

When receiving monaural signals, all you need to consider is the audible frequency range, so the area (a) surrounded by a small triangle up to 15KHz in Figure 2 is the amount of FM noise.

On the other hand, in the case of FM stereo playback, 23
A subcarrier band of ~53KHz is also used, and the noise (b) included in this subcarrier band is included in the audible frequency range due to multiplication during stereo reproduction. As a result, the amount of noise increases significantly.

Therefore, as shown in Figure 3, as the input electric field strength decreases, the S/
N (signal S to noise N ratio) is S/ during monaural playback.
It becomes significantly worse by about 20 dB for N.

Therefore, in FM radio receivers, it has been considered that a predetermined threshold is set for the input electric field strength to automatically switch between stereo and monaural.

However, in this system, when the input level changes around the threshold, stereo-monaural switching is always performed, making it difficult to hear. In particular, for devices such as car radios where the input electric field strength changes greatly, even if the threshold level has some hysteresis, the change in the amount of noise due to the stereo/monaural switching, The sense of place changes greatly, making it extremely difficult to hear.

FIG. 1 is a circuit diagram shown in Japanese Patent Application No. 54-8237 entitled ``FM Multiplex Demodulation Circuit'' prior to the present invention.

A transistor Q ₁ to which the stereo composite signal X _CPNP is applied to its base, and differential switching transistors Q ₂ and Q ₃ provided to its collector.
constitutes the main switching circuit 20, which multiplies the composite signal and the 38 KHz switching signal to obtain stereo demodulated outputs OUT ₁ and OUT ₂ of the left channel and right channel.

In order to improve crosstalk in the main switching circuit 20, a transistor _Q4 has a negative phase composite signal whose level is adjusted by separation adjustment resistors _R1 to _R3 and applied to the emitter.
A sub-switching circuit 21 constituted by differential switching transistors Q ₅ and Q ₆ provided at the collector thereof is arranged. That is, the multiplication output of the 38KHz switching signal of the composite signal of the opposite phase having a predetermined level formed by the transistor _Q4 of this sub-switching circuit 21 is as follows.
As a result of being combined with the multiplication output of the main switching circuit 20, the crosstalk component in the main switching circuit 20 is canceled.

The FM multiplex demodulation circuit having the above-mentioned main switching circuit and sub-switching circuit is
IEEE TRANSACTIONS ON, published October 1968
BROADCAST AND TELEVISION
RECEIVERS VOLUME BTR−14 NUMBER
3. Reported on pp58-73. If there is no need to significantly increase the separation between the stereo demodulated outputs of the left and right channels, the sub-switching circuit 21 described above can be omitted.

According to the above-mentioned Japanese Patent Application No. 54-8237, in order to improve the S/N ratio when receiving a weak input electric field, a 38KHz switching signal is transmitted through a signal supply circuit 22 in the form of a differential amplifier circuit as shown below. This signal is supplied to the multiplex demodulation circuit.

That is, this signal supply circuit 22 is a differential transistor to which a 38KHz switching signal is applied.
Q ₇ , Q ₈ , collector load resistances R ₁₀ , R ₁₁ , a transistor Q ₉ to whose base a control voltage V _C is applied, and an emitter resistance R ₁₂ .

The detection circuit 23 generates a DC output whose level changes depending on the FM intermediate frequency signal (IF) level, and this DC output is applied to the base of the transistor _Q9 as the control voltage V _C .

In addition, the above 38KHz switching signal is 19K
Tuning method that directly amplifies and multiplies the Hz synchronization signal (pilot signal), or 38KHz or 76K
It can be formed using a phase locked loop method (PLL circuit, etc.) in which a Hz oscillation circuit is synchronized with a pilot signal.

According to the circuit of this prior application described above, the gain of the differential amplifier circuit configured as the signal supply circuit 22 changes depending on the emitter current of the transistor Q ₉ , and therefore the gain of the differential amplifier circuit configured as the signal supply circuit 22 changes depending on the emitter current of the transistor Q ₉ ,
Even if the 38KHz switching signal applied to the base of _Q8 is at a constant level, the gain of the differential amplifier circuit described above is reduced in accordance with the decrease in the input level (intermediate frequency signal level), so that the demodulation circuit 2 described above
The level of the 38KHz switching signal applied to 0, 21 can be lowered.

When the level of the 38KHz switching signal in the demodulation circuits 20 and 21 becomes small, the differential switching transistors Q ₂ , Q ₃ , Q ₅ and Q ₆ operate in a linear region. Therefore, as the input level decreases, in other words, as the 38KHz switching level decreases, the crosstalk increases, the stereo separation gradually decreases, and the demodulation circuits 20, 2
1 gradually switches from stereo reproduction operation to monaural reproduction operation due to the decrease in the level of this 38KHz switching subcarrier signal.

Therefore, the differential amplifier circuit described above can withstand a decrease in input level of 38K below the input electric field level V _i just before the noise during stereo demodulation becomes unpleasant.
By gradually reducing the Hz switching signal level, the noise level in the subcarrier band can be reduced, and the deterioration of the S/N ratio as shown by line S' in FIG. 3 can be prevented.

Therefore, according to the circuit of the above-mentioned prior application, even when the input electric field strength changes significantly as in the case of a car radio, sudden changes in the noise level and sound field sensation that cause harshness can be prevented. High-quality and rational reception operations can be achieved.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an FM receiver that is improved over the FM receiver according to the earlier Japanese Patent Application No. 8237/1983.

FIG. 4 shows a circuit diagram of an FM receiver using an FM multiplex demodulation circuit according to a specific embodiment of the present invention.

FM radio frequency signal received by antenna 24
V _ANTT is amplified by a radio frequency amplifier 25,
is applied to the mixer 26. Mixer 26 has
A local oscillation signal generated by local oscillator 27 is applied. In this way, the FM intermediate frequency signal V _IFIN is obtained from the output terminal of the mixer 26, and this FM
The intermediate frequency signal is applied to filter 28.

A broken line IC1 indicates a semiconductor integrated circuit 100 for FM intermediate frequency signal processing, and its No. 1 terminal serves as an input terminal to which the FM intermediate frequency signal V _IFIN from the filter 28 is applied. The FM intermediate frequency signal applied to the first terminal as an input terminal is amplified by a first intermediate frequency amplifier 29, a second intermediate frequency amplifier 30, and a third intermediate frequency amplifier 31 connected in multiple stages. Since the first, second, and third intermediate frequency amplifiers 29, 30, and 31 connected in multiple stages operate as an FM limiter, undesired AM signal components in the FM input signal are removed by the FM limiter. be able to.

Nos. 8, 9, and 10 of the semiconductor integrated circuit 100 are composed of inductors L ₁ , L ₂ , capacitor C ₂₁ , and resistor R ₂₁ .
The phase shift circuit 32 and gate detector 33 connected to the number terminal constitute an FM detector. this kind of
The FM detector was published in November 1967 by the IEEE
TRANSACTIONS ON BROADCAST AND
TELEVISION RECEIVERS VOLUME BTR
-13 NUMBER 3 Reported on pp60-65.

The first, second and third intermediate frequency amplifiers 29, 3
0, 31 and the above-mentioned No. 9 terminals have the first and second terminals, respectively.
2nd, 3rd, and 4th level detectors 34, 35, 3
6 and 37 are connected, and these detectors 34 to 37
detects the peak value of the FM intermediate frequency signal at each part. The output signals of these peak detectors 34 to 37 are applied to a tuning meter drive circuit 38.
The output signal No. 8 is applied to the tuning meter 39 via the No. 13 terminal and the resistor R ₂₂ . These peak detectors 34-37 and tuning meter drive circuit 38 are reported in US Pat. Nos. 3,673,499 and 3,701,022.

The other output of the first level detector 34 is applied as an automatic gain control voltage to the radio frequency amplifier 25 via the 15th terminal, and the amplification gain of this amplifier is controlled.

The first output signal of the gate detector 33 is applied to an automatic frequency control amplifier 40, and the output signal of the amplifier 40 is applied to the local oscillator 27 via the No. 7 terminal. Since the frequency of the local oscillation signal obtained from the local oscillator 27 is thus controlled, the FM receiver can perform a stabilized tuning operation without being detuned from a predetermined radio frequency signal.

The second output signal of the gate detector 33 is a stereo composite signal,
1 to terminal 6.

The other output signal of the fourth level detector 37 is applied to the mute drive circuit 42.
The output signal of 2 is sent to the 12th terminal. The output signal of the 12th terminal is applied to the audio output control amplifier 43 via resistors R ₂₃ and R ₂₄ and the 5th terminal. This audio miute control amplifier 4
The output signal of No. 3 is applied to an audio amplifier 41.

As the semiconductor integrated circuit 100 for FM intermediate frequency signal processing described above, it is possible to use an integrated circuit type CA3089 sold by RCA Corporation in the United States or an integrated circuit type HA1137W sold by Hitachi.

A broken line IC2 is a semiconductor integrated circuit 200 for FM stereo demodulation according to the present invention. The stereo composite signal at the sixth terminal of the semiconductor integrated circuit 100 described above is applied to the preamplifier 44 of the semiconductor integrated circuit 200 via the capacitor _C23 . Phase detector 45, low pass filter 46, DC amplifier 4
7, voltage controlled oscillator 48, frequency divider 49,
50 is a phase lock loop (PLL) circuit 51
Configure.

The voltage controlled oscillator 48 generates an oscillation signal having a frequency (for example, 76 KHz) that is an integral multiple of the 19 KHz pilot signal included in the stereo composite signal. Since the frequency divider 49 divides the frequency of the 76 KHz oscillation signal, two 38 KHz output signals having opposite phases and equal amplitude values are sent out on the output lines l ₁ and l ₂ . Furthermore, the frequency divider 50
divides the 38KHz signal on output line _l2 , so a 19KHz output signal is sent on output line _l3 . The phase detector 45 detects the difference between the phase of the 19KHz pilot signal in the stereo composite signal obtained from the output of the preamplifier 44 and the phase of the 19KHz output signal obtained from the frequency divider 50. The output signal of the phase detector 45 is passed through a low pass filter 46.
and a voltage controlled oscillator 48 via a DC amplifier 47
, so that the 38 KHz signal obtained by frequency divider 49 will be substantially perfectly synchronized with the exact 19 KHz pilot signal in the stereo composite signal. The 38 KHz signal obtained by the frequency divider 49 is therefore applied to the signal supply circuit 22 in the form of a differential amplifier circuit for stereo demodulation.

The frequency divider 52 and the phase detector 53 constitute a detection circuit 54 for detecting the presence or absence of a pilot signal. Frequency divider 52 is 38K on output line l ₁
Divide the Hz output signal and send the 19KHz signal to phase detector 5
Supply to 3. Therefore, the phase detector 53 detects the signal level of the 19KHz pilot signal included in the stereo composite signal obtained from the output of the preamplifier 44, and does not substantially respond to noise components. The detection output signal of the phase detector 53 is transmitted to a lamp drive circuit 57 via a low-pass filter 55 and a DC amplifier 56. The lamp drive circuit 57 has a threshold in the input characteristics for the output signal of the DC amplifier 56, and lights up the stereo indicator lamp 58 connected to the No. 6 terminal when the output signal of the DC amplifier 56 exceeds this threshold value. urge Lighting of the stereo indicator lamp 58 indicates that the FM receiver is receiving a stereo broadcast signal, and conversely, a non-lighting of the stereo indicator lamp 58 indicates a receiving state of monaural broadcast reception.

A semiconductor integrated circuit for PLL type stereo demodulation equipped with such a lamp drive circuit was reported in Electronics pp. 62-66 published in November 1971.

On the other hand, the signal supply circuit 22 includes transistors Q ₇ , Q ₈ , Q ₉ , resistors R ₁₀ , R ₁₁ ,
Consists of R ₁₂ . Stereo demodulator 2
0, 21, the load means are current mirror circuits 59, 60
Transistors Q ₁ to Q ₆ and resistors R ₁ to _{R 7} in the same manner as in the embodiment of FIG. 1 except that
It is composed of. Further, the resistor R ₃ is connected to a separation adjustment variable resistor R ₃ ' via the No. 5 terminal. By adjusting the resistance value of this resistor R ₃ ', the separation between the demodulated output signals L _OUT and R _OUT of the left and right channels can be adjusted.

A constant DC bias voltage V _B1 is applied to the output line _l5 of the preamplifier 44, and a stereo composite signal is applied to the other output line _l8 . The right channel demodulation signal current _iR flows through the output line _l7 of the stereo demodulators 20 and 21 as the input current of the current mirror circuit 60, and the left channel demodulation signal current _iL flows through the other output line _l8 as a current mirror circuit. 59 input current. Resistance of current mirror circuit 59, 60
By setting the resistance values of R ₁₃ , R ₁₄ , R ₁₅ R ₁₆ to be equal to each other, the current values of the output currents i _R ′, i _L ′ can be made equal to the current values of the input currents i _R , i _L .
By applying a constant bias voltage V _B2 to the bases of the transistors Q ₁₆ and Q ₁₇ , these transistors operate as constant power transistors.

The tuning meter drive voltage obtained at the 13th terminal of the semiconductor integrated circuit 100 is applied to the 10th and 11th terminals of the semiconductor integrated circuit 200 as a control voltage V _C .

Next, the antenna input voltage at the antenna 24 is
The operation of the FM receiver of the present invention with respect to level fluctuations of V _ANTT will be explained below.

As shown in FIG. 5, when the antenna input voltage V _ANTT is greater than the predetermined value V _ANNT1 , the semiconductor integrated circuit 100
The automatic gain control (AGC) voltage V ₁₅ obtained at terminal 15 of the radio frequency amplifier 25 controls the voltage gain of the radio frequency amplifier 25 to a value between its minimum value G _vnio and maximum value G _vnax . In this case, the FM obtained from filter 28
The level of intermediate frequency input signal V _IFIN remains constant.

Furthermore, as shown in Figure 5, the antenna input voltage
When V _ANTT becomes less than the predetermined value V _ANNT1 , the voltage gain of the radio frequency amplifier 25 will not increase beyond its maximum value G _vnax . Therefore, in this case, when the level of the antenna input voltage V _ANTT decreases, the FM
The level of intermediate frequency input signal V _IFIN decreases. This decrease does not reach the zero level as shown by the line l _T in FIG. 5 due to noise components.

FIG. 6 shows the terminal _voltages V ₁₂ , V ₁₃ ,
Showing changes in V ₁₅ . In particular, when the FM intermediate frequency input signal V _IFIN becomes less than the first predetermined value V _IFIN1 , the S/
Since the N ratio becomes extremely bad, the mute voltage _V12 at terminal 12 rises to 1.4 volts or more and the resistance increases.
It is transmitted to the audio amplifier 41 via R ₂₃ , R ₂₄ , the fifth terminal, and the audio output control amplifier 43 . Thus, when the FM intermediate frequency input signal becomes equal to or less than the first predetermined value, the audio amplifier 41
The voltage gain of becomes zero, and no stereo composite signal appears at the No. 6 terminal, so that audio mimic operation is achieved.

−(16), as shown in Figure 6, when the level of the FM intermediate frequency input signal V _IFIN is below the level V _IfIN2 which approximates the value of 80 dBμ, the S/N during stereo demodulation is
The decrease in the ratio cannot be ignored. In this example, FM
If the intermediate frequency input signal V _IFIN is 100dBμ or more,
Tuning meter drive voltage at terminal 13 V ₁₃
(V _C ) is constant, so the resistance at terminal 10 is
A constant control current I _C corresponding to this constant meter drive voltage V ₁₃ flows through the DC path of the R ₂₇ to R ₂₉ diode-connected transistor Q ₁₈ . In this case, the voltage gain of the differential amplifier circuit as the signal supply circuit 22 is controlled to a high value, so a high level 38 KHz switching subcarrier signal is transmitted from the signal supply circuit 22 to the demodulation circuits 20 and 21. Thus, in this case, the demodulation circuits 20 and 21 perform a reproduction operation of stereo demodulation.

On the other hand, the level of the FM intermediate frequency input signal V _IFIN is
When the control current I C decreases to 100 dBμ or less, the current value of the control current I _C decreases as the level of V _IFIN decreases. Therefore, since the voltage gain of the signal supply circuit 22 is reduced, the level of the 38KHz switching signal transmitted to the demodulation circuits 20 and 21 is reduced. Thus, the stereo separation in demodulation circuits 20 and 21 gradually decreases.

As the tuning meter drive voltage V _C continues to decrease, the diode-connected transistor Q ₁₈ becomes non-conductive and the current value of the control current I _C becomes substantially zero. Then, the transistor of the signal supply circuit 22
Q ₉ becomes non-conductive, and the signal supply circuit 22 prohibits transmission of the 38KHz switching signal to the demodulation circuits 20 and 21. Thus, the demodulation circuits 20, 21
performs monaural playback operation.

Therefore, as shown in Fig. 7, when the FM intermediate frequency input signal V _IFIN drops to 100 dBμ, the S/N ratio changes from the S/N ratio L ₁ during stereo playback to the S/N ratio during monaural playback along the path of line S'. The N ratio will gradually change to _L2 , and along with this, the stereo separation _Sep will gradually decrease as shown by the line _L3 .

According to a preferred embodiment of the present invention, the 14th and 15th terminals of the semiconductor integrated circuit 200 each have a capacitance.
It is connected to the 4th terminal and the 3rd terminal via C ₂₄ and C ₂₅ , and the 3rd terminal and the 4th terminal are connected to the first variable impedance circuit 61 and the second variable impedance circuit 62, respectively. .

The first variable impedance circuit 61 includes transistors Q ₂₀ and Q ₂₁ and resistors R ₃₀ and R ₃₁ , and the second variable impedance circuit 62 includes transistors Q 20 and Q 21 and resistors R 30 and R 31.
It is composed of Q ₂₂ , Q ₂₃ and resistors R ₃₂ and R ₃₃ .

An impedance control circuit 64 for controlling each impedance of the first variable impedance circuit 61 and the second variable impedance circuit 62 is arranged. The impedance control circuit 61 includes a signal inverter 63, transistors Q ₂₄ , Q ₂₅ , Q ₂₆ , and resistors.
It is composed of R ₃₄ , R ₃₅ , and R ₃₆ . Since the tuning meter drive voltage V _C (V ₁₃ ) is applied to the input (terminal 11) of the signal inverter 63, the level of the FM intermediate frequency signal V _IFIN is reduced at the base of the transistor Q ₂₄ . A control voltage V _B3 is applied whose level is increased by .

Therefore, when the level of the FM intermediate frequency input signal V _IFIC decreases significantly, the collector current of the transistor Q ₂₄ increases, and the diode-connected transistors Q ₂₅ ,
The base-emitter forward voltage V _BE of Q ₂₆ increases. Then, the conductivity of transistors Q ₂₀ and Q ₂₁ in the first variable impedance circuit and transistors Q ₂₂ and Q ₂₃ in the second variable impedance circuit 62 increases, so that the emitter input resistance of each transistor decreases.

Therefore, if the level of the FM intermediate frequency input V _IFIN is significantly reduced by employing the first and second variable impedance circuits 61 and 62 as shown by the lines L ₁ ′ and L ₂ ′ in FIG. , the high frequency noise components in the output signals of the 14th and 15th terminals are flowed to the grounding point via the capacitors C ₂₄ and C ₂₅ and the low impedance first and second variable impedance circuits 61 and 62. The S/N ratio can be further improved.

According to another preferred embodiment of the present invention, a transistor Q ₁₉ for forced stereo-monaural switching is connected to the base of the transistor Q ₉ of the signal supply circuit 22.

Since the 19KHz pilot signal is no longer included in the composite signal of the preamplifier 44 where the FM receiver is receiving the monaural broadcast signal, the pilot signal detection circuit 54 sends a low level output signal to terminal 8. I come to do it. The output of the DC amplifier 56 becomes low level, and this low level output signal has a value below the input threshold of the lamp drive circuit 57, so the lamp drive circuit 57 controls the stereo indicator lamp 58 to a non-lighting state. This indicates the reception status of a monaural broadcast signal. At the same time, the lamp drive circuit 57 sends a high-level output signal to the output line _l4 to turn on the switching transistor _Q19 .

Therefore, the meter drive voltage supplied to terminal 10
Level of V ₁₃ (Level of FM intermediate frequency signal V _IFIN )
Regardless of the switching transistor _Q19 being turned on, the transistor _Q9 is forced to be turned off. In this way, the 38KHz switching signal is no longer transmitted to the demodulation circuits 20 and 21, so the demodulation circuits 20 and 21 perform a monaural reproduction operation and the S/N ratio changes from line _L1 to line _L2 as shown in FIG.
is forcibly switched to. Thus, if the FM receiver is receiving a mono broadcast signal, the FM
demodulation circuit 20, regardless of the level of the intermediate frequency signal;
21 is forced to perform a monaural reproduction operation, so that its S/N ratio can be further improved.

[Brief explanation of drawings]

Figure 1 is a circuit diagram proposed in Japanese Patent Application No. 54-8237 related to the earlier application, Figure 2 is an FM triangular noise characteristic diagram, and Figure 3 explains the earlier application shown in Figure 1. Fig. 4 is a circuit diagram showing an embodiment of the present invention, Fig. 5 is a characteristic diagram showing antenna input voltage - FM intermediate frequency input signal characteristics,
FIG. 6 is a characteristic diagram showing changes in each terminal voltage in the circuit of FIG. 4 due to level changes of the FM intermediate frequency input signal, and FIG. 7 is a characteristic diagram showing the technical effects of the embodiment of FIG. 4. . 20, 21... Demodulation circuit, 22... Signal supply circuit, 34, 35, 36... Detection circuit, 54... Pilot signal detection circuit, 57... Indicator drive circuit, 58... Stereo indicator.

Claims (1)

[Claims] 1 Demodulation circuit for reproducing left channel demodulation output and right channel demodulation output from a stereo composite signal and a 38KHz switching signal, as described above.
A signal supply circuit for transmitting the 38KHz switching signal to the demodulation circuit, a detection circuit for obtaining a detection signal corresponding to the level of the FM intermediate frequency signal, and a pilot signal detection circuit for detecting the level in the stereo composite signal. an indicator drive circuit to which an output signal of the upper pilot signal detection circuit is applied to drive a stereo indicator; a meter drive circuit to generate a tuning meter drive voltage; and a tuning meter to which the meter drive voltage is applied. and,
controlling the gain of the signal supply circuit by transmitting the detection signal to the signal supply circuit;
The level of the above 38KHz switching signal transmitted from the above signal supply circuit to the above demodulation circuit is the above FM.
The level of the intermediate frequency signal is gradually lowered by lowering the level of the intermediate frequency signal, and the detection signal is applied to the tuning meter drive circuit.
The tuning meter drive voltage is generated in accordance with the level of the FM intermediate frequency signal, and the indicator drive circuit has a threshold in its input characteristics, and the output level of the pilot signal detection circuit is controlled by the threshold. In the following cases, the stereo indicator is turned off and at the same time the gain of the signal supply circuit is reduced.
An FM receiver characterized in that a 38KHz switching signal is prohibited from being transmitted to the demodulation circuit.