JPS6255737B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a serial-parallel signal conversion circuit that converts a high-speed serial signal into a low-speed parallel signal.

The above-mentioned serial-to-parallel signal conversion circuit is required when separating a channel signal from a high-speed serial signal on a data highway, or when transmitting information to a low-speed terminal in units of words.

FIG. 1 shows the configuration of a conventional serial-parallel signal conversion circuit. In this figure, 1 is a shift register, 2 is a latch circuit, 3 is a clock supply circuit, F ₁ to F ₈ , f ₁
~ _f8 is a flip-flop, and CLK1 and CLK2 are clock signals. Note that this figure is an example of converting 8-bit serial data to 8-bit parallel data.
FIG. 2 is a time chart of the clock signal in FIG. In this figure, CLK1 and CLK2 correspond to CLK1 and CLK2 in FIG.

The phase relationship between clock signals CLK1 and CLK2 is as shown in Figure 2. High-speed serial data is serially written into shift register 1 one after another by clock signal CLK1, and when eight pieces of data are written, the clock signal The contents of each flip-flop _F1 to _F8 in the shift register 1 are read out to the latch circuit 2 by CLK2. By repeating the above operations, the input serial data is converted to 8-bit parallel data at 1/8 the speed.

The above is the operation of a conventional serial-to-parallel signal conversion circuit.In such a system, as the speed of the input serial signal increases, the implementation technology for supplying the clock signal CLK1 to the multi-stage shift register becomes
This becomes rapidly difficult due to pulse reflections, crosstalk between wires, etc. In addition, it is necessary to read the data in the shift register 1, which changes at high speed, into the latch circuit 2 accurately within one bit time of the high-speed serial signal, so the flip-flop f ₁ in the latch circuit 2 is
~ _F8 high speed operation is required. Furthermore, as the operation speed increases, the power consumption of the circuit used also increases, resulting in restrictions on the mounting of circuit elements.

An object of the present invention is to eliminate the above-mentioned drawbacks and provide a serial-to-parallel converter circuit that can be configured with low-speed operating circuit elements. n flip-flops are provided for each of the n flip-flops, and the outputs of the flip-flops are read out of phase with n clocks having different phases from each other at a speed of A flip-flop group consisting of k series-connected flip-flops in m columns read by m different clocks, and each output of the series-connected flip-flops is read at a speed 1/k times that of the clock of the series-connected flip-flops. and a latch circuit that latches with the same clock.

The present invention will be explained in detail below using the figures. FIG. 3 shows an embodiment of the present invention. In this figure, 4
is a clock supply circuit, 5 is a flip-flop group,
6 is a latch circuit, CL11 to CL122, CL is a clock signal, _d1 to _d8 are data, Fa, Fb, _F'1 to
F′ ₈ , f′ ₁ to f′ ₈ are flip-flops. Note that the same numbers as in FIG. 1 indicate the same parts. FIG. 4 is an operation time chart of one embodiment of the present invention. In this figure, SIG corresponds to input serial data, and a to f correspond to points a to f in FIG. 3. Note that this embodiment is an example in which an 8-bit serial signal is converted into an 8-bit parallel signal.

In this embodiment, n=2, m=2, k=2, and the high-speed serial signals input to the series-parallel circuit are mutually connected at half the speed of the clock signal CLK1.
Clock signals CL11 and CL2 with 180° different phases
2, it is read into flip-flops Fa and Fb.
Further, the contents of flip-flop Fa are read into flip-flops F' ₅ and F' ₇ by clock signals CL111 and CL112, which are 180 degrees out of phase with each other at half the speed of clock signal CL11, and are read into flip-flops F' ₁ and F' ₃ , respectively. will be forwarded to. Similarly, the contents of flip-flop Fb are also clock signals CL121,
The data is read into flip-flops F' ₆ and F' ₈ by the CL 122 and transferred to flip-flops F' ₂ and F' ₄ , respectively. Furthermore, clock signals CL111, CL
An 8-bit parallel signal is obtained by latching the contents of flip-flops F' ₁ -F' ₈ in the latch circuit 6 using a clock signal CL having a speed of 1/2 of 112.

By configuring the serial-parallel signal conversion circuit as described above, the flip-flops F 1 to F ₁ that constitute the shift register 1 in the conventional example shown in FIG.
For an operating speed of F ₈ , the flip-flop Fa,
The operating speed of Fb may be 1/2, and the flip-flops F' ₁ to F' ₈ may be of 1/4 operating speed. Also, the clock signal supplied to the latch circuit 6
The speed of CL is the same as that of the clock signal CLK2, but since the 1-bit time of data is four times that of the conventional one, the flip-flop composing the latch circuit 6 is
The resolution of F′ ₁ to F′ ₈ may be 1/4 that of the conventional method.

In this way, in the serial-to-parallel converter circuit according to the present invention, the clock frequency supplied to the flip-flop can be 1/2 to 1/4 of that of the conventional circuit, so it can be easily implemented. In addition, since low-speed operation ICs can be used, for example, conventional serial-to-parallel signal conversion circuits that input a 40MHz clock serial signal required the use of CML-ICs for all ICs. With this configuration, it is possible to use a Jotsky IC, and power consumption can be significantly reduced.

Although this embodiment converts an 8-bit serial signal into an 8-bit parallel signal, a configuration as shown in FIGS. 5 and 6 may be adopted as required. Fifth,
FIG. 6 shows another embodiment. 7,10 in both figures
is a flip-flop group, 8 and 11 are latch circuits,
9 and 12 are clock supply circuits. The expansion from series to parallel in the serial-to-parallel conversion circuit according to the present invention may be carried out up to an appropriate stage as shown in FIG. You can do it like this.

As described above, according to the present invention, it is possible to use a low-speed, highly integrated IC, and therefore it is possible to achieve a significant reduction in power consumption and ease of implementation.

[Brief explanation of the drawing]

Fig. 1 shows the configuration of a conventional serial-parallel signal conversion circuit, Fig. 2 shows a time chart of the clock signal in Fig. 1, Fig. 3 shows an embodiment of the present invention, and Fig. 4 shows an embodiment of the present invention. The time charts in FIGS. 5 and 6 show other embodiments of the present invention. 4...Clock supply circuit, 5...Flip-flop group, 6...Latch circuit, CL11 to CL12
2. CL...clock signal, _d1 to _d8 ...data,
Fa, Fb, F′ ₁ ~ F′ ₈ , f′ ₁ ~ f′ ₈ ... flip-flop.

Claims (1)

[Scope of Claims] 1. n flip-flops Fa, Fb that read an input signal with n clocks having mutually different phases at a speed of 1/n times the clock of the input signal, and for each of the n flip-flops. K flip-flops in m columns connected in series read the output of the flip-flop with m clocks having mutually different phases at a speed of 1/m times the _clock of the flip- _flop ;
F′ ₇ , F′ ₃ :Flip-flop groups 5, 7, 10 consisting of F′ ₆ , F′ ₂ , F′ ₈ , F′ ₄ and each output of the series-connected flip-flops connected in series. A serial-to-parallel signal conversion circuit comprising latch circuits 6, 8, and 11 which latch with the same clock having a speed 1/k times that of the flip-flop clock.