JPS6253071A - Facsimile equipment - Google Patents

Facsimile equipment

Info

Publication number
JPS6253071A
JPS6253071A JP60192752A JP19275285A JPS6253071A JP S6253071 A JPS6253071 A JP S6253071A JP 60192752 A JP60192752 A JP 60192752A JP 19275285 A JP19275285 A JP 19275285A JP S6253071 A JPS6253071 A JP S6253071A
Authority
JP
Japan
Prior art keywords
signal
generator
phase
phase matching
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60192752A
Other languages
Japanese (ja)
Inventor
Yukihiro Matsuda
行弘 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60192752A priority Critical patent/JPS6253071A/en
Publication of JPS6253071A publication Critical patent/JPS6253071A/en
Pending legal-status Critical Current

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  • Facsimile Transmission Control (AREA)
  • Facsimile Image Signal Circuits (AREA)

Abstract

PURPOSE:To decrease the number of programable signal generators by holding a phase matching point while transmitting a CFR signal, and switching a programmable signal generator to generate a tonal signal or a clock synchronized with a picture element signal by means of time dividing. CONSTITUTION:A CPU 11 controls the programmable signal generator 13, a switcher 14, and a 1-line picture signal-section synchronizing-signal generator 16. To the CPU 11, a picture signal synchronizing pulse P of optional bits outputted from a picture element signal synchronizing pulse generator 15 is inputted. And also, the CPU 11 detects a phase signal PHS transmitted from a transmitter, and executes the phase matching. After detecting the cutting of the phase signal PHS from the transmitter, the receiver makes the output from the generator 13 to be in input to a tonal signal generator 12 by its switcher 14, and transmits a reception confirmation signal CFR by controlling the generator 13 through the CPU 11. Consequently, the synchronizing pulse generator 15 generates picture element synchronizing pulse P after receiving the signal from the programmable signal generator 13.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、7アクシミ’)装置に関し、特に、位相整合
点を保持する手段を内蔵する7アクシイリ装置に関する
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a 7-axis device, and more particularly to a 7-axis device incorporating means for maintaining a phase matching point.

従来の技術 従来、7アクシミ’)通信にて送信機から送られてくる
位相信号を検出後に位相整合を行いCFR,信号(受信
1a誌信号)を送出する7アクシンり装置は、CFR信
号退出時に画信号に同期したクロックを自走させ、位相
整合点をその後に送信機がら送られてぐる画信号を検出
するまで保持している。
Conventional technology Conventionally, a 7-axis device that detects a phase signal sent from a transmitter through 7-axis communication and then performs phase matching and sends out a CFR signal (reception 1a signal) A clock synchronized with the image signal is run free, and the phase matching point is held until the image signal sent from the transmitter is detected.

そのために、CFR信号を含むトーナル信号の発生及び
画信号に同期したクロックを発生するためのプログラマ
プルナ徊号発生器が2個必要である。
For this purpose, two programmer puller signal generators are required to generate tonal signals including CFR signals and clocks synchronized with image signals.

発明が解決しようとする問題点 上述した従来の7アクシミリ装置は、トーナル信号の発
生及び画信号に同期したクロックを発生させるために、
プログラマブルな信号発生器が2個必要とな〕、更にこ
nらの機能を含む変復調器周辺回路をLSI化する場合
には該LSIが複雑かつ高価になるという欠点があった
Problems to be Solved by the Invention The conventional 7-axis device described above has the following steps in order to generate a tonal signal and a clock synchronized with the image signal.
Two programmable signal generators are required].Furthermore, if the peripheral circuit of the modulator/demodulator including these functions is integrated into an LSI, the LSI becomes complicated and expensive.

問題点を解決するための手段 上記目的を達成する為に、本発明に係るファクシミリ装
置は、トーナル信号の発生あるいは画素信号に同期した
クロック発生のためのプロゲラiプルな単一〇信号発生
器とCFR送出中に位相整合点を保持するための信号発
生器を有している。
Means for Solving the Problems In order to achieve the above object, the facsimile apparatus according to the present invention includes a progera i pull single signal generator for generating a tonal signal or generating a clock synchronized with a pixel signal. It has a signal generator to maintain a phase matching point during CFR transmission.

即ち、具体的には、本発明に係るファクシミリ装置は、
送信機から送出される位相信号に同期しその後に送らn
てくる画信号を記録するファクシンり装置において、ク
ロック信号を発生する単一の信号発生器と、該信号発生
器の出力に基いてトーナル信号を発生ずるトーナル信号
発生器と、前記信号発生器の出力に基いて任意のビット
の画素信号同期パルスを発生する画素信号同期パルス発
生器と、前記信号発生器の出力を前記トーナル信号発生
器又は前記画素信号同期パルス発生器に選択的に切換え
る切換手段と、前記切換手段を制御すると共に、前記画
素信号同期パルスを入力し前記位相信号を検出して位相
整合を行う位相整合手段と、位相整合後の確認信号送出
中に該位相整合手段によジ得らnる位相整合点を保持す
る同期信号を発生する同期信号発生手段とを具備して構
成される。
That is, specifically, the facsimile device according to the present invention:
It is synchronized with the phase signal sent out from the transmitter and then sent n
A facsimile device that records an incoming image signal includes a single signal generator that generates a clock signal, a tonal signal generator that generates a tonal signal based on the output of the signal generator, and a single signal generator that generates a tonal signal based on the output of the signal generator. a pixel signal synchronization pulse generator that generates a pixel signal synchronization pulse of any bit based on the output; and a switching means that selectively switches the output of the signal generator to the tonal signal generator or the pixel signal synchronization pulse generator. a phase matching means that controls the switching means, inputs the pixel signal synchronization pulse, detects the phase signal, and performs phase matching; and synchronization signal generating means for generating a synchronization signal that maintains the obtained n phase matching points.

実施例 次に本発明をその好ましい一実施例について図面を参照
し、CCITT勧告T30のG27アクシξりを例にと
シ具体的に説明する。
Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings, taking the G27 axis ξ of CCITT Recommendation T30 as an example.

第1図は本発明の一実施例を示すブロック構成図、第2
図は本発明を説明するためのタイミングチャートである
。第1図において、参照番号11はCPUを示し、該C
PUIIは、プログラマブル信号発生器13、切換器1
4及びlライン画信号区間同期信号発生器16を制御す
ると共に、画素信号同期パルス発生器15から出力さn
る任意のビット(本実施例においては8ビツト)の画信
号同期パルスPを入力し、送信機から退出さnる位相信
号PH8を検出して位相整合を行う機能を有する。12
は受信確認信号CFR等のトーナル信号を発生するトー
ナル信号発生器、l:H!プログラマブルなりロック信
号を発生するプログラマブル信号発生器、14は切換器
、15は任意のビット(本実施例においてFi8ビット
)の画素信号同期パルスPを発生する画素信号同期パル
ス発生器、16はCPUIIKよって得られた位相整合
点を保持する同期信号PHDt−Q生するlライン画信
号区間同期信号発生器、17はモデムをそれぞれ示す。
FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a timing chart for explaining the present invention. In FIG. 1, reference number 11 indicates a CPU;
PUII is a programmable signal generator 13, a switch 1
4 and l line picture signal section synchronization signal generator 16 is controlled, and pixel signal synchronization pulse generator 15 outputs n
It has a function of inputting an image signal synchronizing pulse P of arbitrary bits (8 bits in this embodiment) and detecting a phase signal PH8 exiting from the transmitter to perform phase matching. 12
is a tonal signal generator that generates tonal signals such as the reception confirmation signal CFR, l:H! A programmable signal generator that generates a programmable lock signal, 14 a switch, 15 a pixel signal synchronization pulse generator that generates a pixel signal synchronization pulse P of arbitrary bits (Fi8 bits in this embodiment), and 16 a CPU IIK A line image signal section synchronization signal generator 17 generates a synchronization signal PHDt-Q that maintains the obtained phase matching point, and 17 represents a modem.

受信機のCPUIIは、送信機から送らnてくる信号P
f(Sを受信する前に、切換器14を制御することによ
シプログラマプル信号弛生器13の出力を画素信号同期
パルス発生器15の入力とする。パルス発生器15は画
素信号の8ビツト毎に画素同期パルスPを発生させる。
The CPU II of the receiver receives the signal P sent from the transmitter.
f(S), the output of the programmable signal relaxer 13 is input to the pixel signal synchronization pulse generator 15 by controlling the switch 14. A pixel synchronization pulse P is generated for each bit.

モデム17から位相信号PH8を受信すると、CPU1
1r!、該8ビツトの画素同期パルス毎にデータを解析
して位相検出及び位相整合を行う。位相整合完了後(第
2図の時刻T I )、CPU11t!lライン画信号
区間同期信号発生器16からのlライン画信号区間同期
信号PHDO発生を位相整合点(第2図の時刻T2)で
スタートさせる。
Upon receiving the phase signal PH8 from the modem 17, the CPU 1
1r! , the data is analyzed for each of the 8-bit pixel synchronization pulses, and phase detection and phase matching are performed. After the phase matching is completed (time T I in FIG. 2), the CPU 11t! Generation of the l-line picture signal section synchronization signal PHDO from the l-line picture signal section synchronization signal generator 16 is started at the phase matching point (time T2 in FIG. 2).

次いで、受信機は送信機からの位相信号PH8の断を検
出後に1切換器14により信号発生器13の出力をトー
ナル信号発生器12の入力とし、CPUIIによυプロ
グラマブル信号発生器13を制御し、受信確認信号CF
Rを退出(112図の時刻′r3)する。
Next, after detecting the disconnection of the phase signal PH8 from the transmitter, the receiver uses the 1 switch 14 to input the output of the signal generator 13 to the tonal signal generator 12, and controls the υ programmable signal generator 13 by the CPU II. , reception confirmation signal CF
Exit R (time 'r3 in Figure 112).

受信確固信号CFRの退出完了後に、切換器14によシ
プログラマブル信号発生器13の出力を画素信号同期パ
ルス発生器15の入力とすることによシ、パルス発生器
15よシ画素同期パルスPが発生(第2図の時刻T4)
する。
After the output of the received reliable signal CFR is completed, the output of the programmable signal generator 13 is inputted to the pixel signal synchronization pulse generator 15 by the switch 14, so that the pixel synchronization pulse P is output from the pulse generator 15. Occurrence (time T4 in Figure 2)
do.

該画素同期パルスPの発生毎に、CPU1lは、lライ
ン画信号区間同期信号発生回路16よシ出力されるlラ
イ/画信号区間同期信号PHDのレベルをチェックし、
同期信号PHDの立下り検出ポイント(第2図の時刻″
r5)を位相整合点とじて、その後送信機から送出され
る画信号FIXの記録を行う。
Each time the pixel synchronization pulse P is generated, the CPU 1l checks the level of the l line/picture signal section synchronization signal PHD output from the l line picture signal section synchronization signal generation circuit 16,
The falling detection point of the synchronization signal PHD (time" in Figure 2)
r5) as a phase matching point, and then records the image signal FIX sent out from the transmitter.

ここでの位相整合点はlラインの画信号の基準点のこと
であり、例えば、lラインの最初の画素が現われるポイ
ントである。
The phase matching point here is the reference point of the image signal of the l line, for example, the point where the first pixel of the l line appears.

第3図は本発明の一動作例を示す70−チャ−トである
FIG. 3 is a 70-chart showing an example of the operation of the present invention.

以上本発明をその良好な一実施例について説明したが、
それは単なる例示的なもので69制限的意味を有するも
のでないことは勿論であり、本実施例以外にも本発明に
ついてtfi稙々の変形が容易に想起される。例えば、
本実施例においては信号発生器13としてプログラマブ
ルな信号発生器が用いられているが、代りに、カウンタ
によりm成することもできるし、また、画素信号同期パ
ルス発生器15から出力される同期パルスは8ビツトを
例にとっているが、16ビツト又は32ビツトも同様に
可能であることは明らかである。
The present invention has been described above with respect to one preferred embodiment thereof, but
Of course, this is merely an example and does not have a restrictive meaning, and various modifications of the present invention other than the present embodiment can easily be imagined. for example,
In this embodiment, a programmable signal generator is used as the signal generator 13, but instead, m can be generated by a counter, or the synchronization pulse output from the pixel signal synchronization pulse generator 15 Although 8 bits are taken as an example, it is clear that 16 or 32 bits are possible as well.

弛明の効果 以上説明したように、本発明によれば、CFR信号送出
中に位相整合点を保持する回路を付加し、トーナル信号
発生おるいは画素信号に同期したクロック兆生のための
プログラマブルな信号発生器を時分割に切換えることに
より、プログラマブルな信号発生器を1個少なくするこ
とができ、トーナル信号発生及び画素信号に同期したク
ロック免生機能を含む変復調器周辺回路のLSI化が容
易となる効果が得られる。
Effect of Relaxation As explained above, according to the present invention, a circuit that maintains a phase matching point during CFR signal transmission is added, and a programmable circuit for tonal signal generation or clock generation synchronized with pixel signals is provided. By switching the signal generator to time division, the number of programmable signal generators can be reduced by one, and it is easy to integrate the modem peripheral circuit, which includes tonal signal generation and clock immunity functions synchronized with pixel signals, into an LSI. The following effect can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロック構成図、第2
図は第1図に示した実施例における動作を説明するため
のタインングチャート、第3図は ゛本発明の動作フロ
ーチャートである。
FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
This figure is a timing chart for explaining the operation of the embodiment shown in FIG. 1, and FIG. 3 is a flowchart of the operation of the present invention.

Claims (1)

【特許請求の範囲】[Claims] 送信機から送出される位相信号に同期しその後に送られ
てくる画信号を記録するファクシミリ装置において、ク
ロック信号を発生する単一の信号発生器と、該信号発生
器の出力に基いてトーナル信号を発生するトーナル信号
発生器と、前記信号発生器の出力に基いて任意のビット
の画素信号同期パルスを発生する画素信号同期パルス発
生器と、前記信号発生器の出力を前記トーナル信号発生
器又は前記画素信号同期パルス発生器に選択的に切換え
る切換手段と、前記切換手段を制御すると共に前記画素
信号同期パルスを入力し前記位相信号を検出して位相整
合を行う手段と、位相整合後の確認信号送出中に該位相
整合手段により得られる位相整合点を保持する同期信号
を発生する同期信号発生手段とを含むことを特徴とする
ファクシミリ装置。
A facsimile machine that synchronizes with a phase signal sent from a transmitter and records an image signal sent thereafter has a single signal generator that generates a clock signal and a tonal signal based on the output of the signal generator. a pixel signal synchronization pulse generator that generates pixel signal synchronization pulses of arbitrary bits based on the output of the signal generator; switching means for selectively switching to the pixel signal synchronization pulse generator; means for controlling the switching means and inputting the pixel signal synchronization pulse to detect the phase signal to perform phase matching; and confirmation after phase matching. A facsimile apparatus comprising synchronization signal generating means for generating a synchronization signal that maintains a phase matching point obtained by the phase matching means during signal transmission.
JP60192752A 1985-08-31 1985-08-31 Facsimile equipment Pending JPS6253071A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60192752A JPS6253071A (en) 1985-08-31 1985-08-31 Facsimile equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60192752A JPS6253071A (en) 1985-08-31 1985-08-31 Facsimile equipment

Publications (1)

Publication Number Publication Date
JPS6253071A true JPS6253071A (en) 1987-03-07

Family

ID=16296458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60192752A Pending JPS6253071A (en) 1985-08-31 1985-08-31 Facsimile equipment

Country Status (1)

Country Link
JP (1) JPS6253071A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034689A (en) * 1988-04-13 1991-07-23 Yamato Scale Company, Limited Detector for detecting foreign matter in an object by detecting electromagnetic parameters of the object
JPH03123284U (en) * 1990-03-27 1991-12-16

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034689A (en) * 1988-04-13 1991-07-23 Yamato Scale Company, Limited Detector for detecting foreign matter in an object by detecting electromagnetic parameters of the object
JPH03123284U (en) * 1990-03-27 1991-12-16

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