JPS6252974A - Non-volatile semiconductor memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a non-volatile semiconductor memory device, which is a non-volatile semiconductor memory device.
OM). [Prior Art] FIGS. 2A, 2B, and 3 are diagrams showing the configuration and equivalent circuit of a conventional nonvolatile semiconductor memory device.
FIG. 28 shows a cross-sectional structure taken along line CC in FIG. 2A, and FIG. 3 shows an equivalent circuit. This nonvolatile semiconductor memory device is, for example, an IEE
Digest of Technical Vapor
DIGEST OF TECHNICAL PAPE
R8), 1984, p. 268. The structure and operation of a conventional nonvolatile semiconductor memory device will be described below with reference to FIGS. 2A, 28, and Section 3. In FIG. 2A, a memory cell of a nonvolatile semiconductor memory device is composed of a memory transistor 19 for storing information and a select transistor 20 for selecting this memory transistor. Next, each arrangement will be explained. The memory cell includes an active region 1.2 formed on a P-type semiconductor substrate 50. In predetermined regions of the activated steel wi1, N" diffusions @4 and 3 are formed, which become the source and drain of the memory transistor 19, respectively. The N+ diffusion layer 3 functions as the source of the select transistor 20.
In the active region 2, there is an N+ expanded pHI! for controlling charge storage and release of the memory transistor 19. A hunt roll gate 5 consisting of I is formed. A floating gate 13 for storing charge is formed using polycrystalline silicon on the active m regions 1 and 2 via an insulating film. 70-ting gate 13 and active region 1
A thin Ml gate oxide film 14 is formed at a predetermined distance *m between the active region 1 (drain 3) and the floating gate 13, and forms an electron tunnel injection region between the active region 1 (drain 3) and the floating gate 13. In particular, the floating gate 13 and the first gate oxide 1
The region wt where $14 overlaps is called a tunnel region or tunnel oxide film. On the other hand, there is also a second thin gate oxide between the active region 2 and the floating gate 13! 1
15 are formed and their overlapping regions form a capacitor. On the active W4 region 2, a control gate (coating 11 is formed of aluminum) is connected to the control gate 5 through contacts 1 to holes 8 in order to apply voltage to the control gate 5. A source line 10 connected to the source 4 via a contact hole 7 is formed of aluminum in order to apply a voltage to the contact hole 6. A bit line 9 made of aluminum is provided on the active region 1 and the contact hole 6 is selector transistor 2
0 drain fEiii! 30. moreover,
”/-sWA 10. HittlA913.):U'
: A word line 12 made of aluminum is provided so as to intersect with the J control gate line 11 via an insulating film,
It serves as a select gate for selecting memory transistor 19 on active region 1 . As seen from the cross-sectional structure in Figure 2B, activity 11.2
A floating gate 13 is formed thereon through thin gate oxide films 14 and 15, and this floating gate 13 is covered with an insulating film and is in an electrically floating state. As seen from the equivalent circuit diagram in FIG. 3, the control gate 5 and floating gate 13 are
5 and are connected via fi. Furthermore, the floating gate 13 extends onto the drain chain of the memory transistor 19, and the drain of the memory transistor 19 and the source of the select i transistor 20 are shared, and the memory transistor 19 and the selector transistor 20 are connected in series. Next, this operation will be explained. Information is stored in this non-electronic semiconductor memory device by injecting charges into the floating gate 13 of the memory transistor 19. Since this floating gate 13 is surrounded by an oxide film and is in an electrically floating state, nonvolatile information storage is realized. The injection of charges into the floating gates 1 and 13 and the discharge are carried out by applying a high electric field of several MV//Cr or more to the tunnel oxide film and injecting electrons into the tunnel oxide film. The storage operation of the memory transistor is as follows. First, the platform for injecting electrons into the floating gate 13 will be explained. At this time, a voltage of 0 is applied to the source 4 and drain 3 of the troll gate. The potential of the floating gate 13 is determined by combining the voltage applied to the control gate 5 with the capacitance between the control gate and the floating gate, the floating gate [--drain IMI'd, and the floating gate-semiconductor base t!
The capacity consists of the 21il capacity and the capacity between the controller and the 2 legade source! It can be obtained by dividing the capacity in the l coupling circuit. By appropriately selecting these capacitances, the high voltage applied to the control gate 5 can be applied to the floating gate 13 without much loss, and a high electric field can be generated between the floating gate and the drain. By applying a high electric field to the gate oxide film (1-Nelate 1HilJI), the probability that electrons will tunnel through the potential barrier of the oxide film increases. This causes a negative charge to accumulate on the floating gate, causing the memory The threshold voltage vth of the transistor 19 shifts in the positive direction.Hereinafter, this state is called an erased state, and the stored information is assumed to be "1".On the contrary, electrons are extracted from the 70-ting gate 13 (in case , OV is applied to the control gate 5, a high voltage of approximately 20V is applied to the drain 3, and 5V is applied to the source 4.As a result, the floating gate 1
A high electric field is generated between the floating gate 13 and the drain 3, and electrons are extracted from the floating gate 13 to the drain 4. In this way, positive charges are accumulated in the floating gate 13, and the threshold voltage vth of the memory transistor 19 is shifted in the negative direction. Hereinafter, this state will be referred to as a write state, and it is assumed that information "0" is stored.The information held in the memory transistor 19 is transmitted to the control gate 5 and the source 4 via the control gate line 11 and the source 110, respectively. give an OV to
This is done by applying a low potential of about several volts to the drain 3. At this time, the memory transistor 19 is turned on or off depending on the N charges accumulated on the floating gate 13. Therefore, the current flowing between the source and drain of the memory transistor 19 is amplified by a sense circuit (not shown) via the select transistor 20, and the memory transistor 19 is turned on/off according to the 74 1yE value. By detecting the state, the memory 11I information held in the memory transistor 19 is read out. Figure 4 is the same as Figure 2A. FIG. 4 is a diagram showing a capacitor circuit configured by a memory transistor of a memory cell of the nonvolatile semiconductor storage device shown in FIGS. 2B and 3; As can be seen from FIG.
Capacitors are formed in parallel between them, and a control gate-to-fing gate capacitance WCI is formed in series with the parallel body of these capacitors. Here,

[The capacitance between the coating gate 13 and the source 4 is 04. It is assumed that the capacitance between the floating gate and the semiconductor substrate is C2, and the capacitance between the floating gate and the drain is 03. Next, referring to FIG. 4, assuming that the high voltage applied during writing and erasing is VPP, the floating gate i-13 at that time is
The potential Vr and the potential difference Vox between the floating gate and the drain are determined. However, the potentials applied to the control gate, source, drain, and semiconductor substrate are each VcG. Let Vs, Vo, and Vs s. The charge currently accumulated in the floating gate 13 is Qr
Then, the following formula (1)% formula %) is now established. If Q, -Q coulombs are used to simplify the junction, the potential Vr 13 of the floating gate during erasing and writing and the potential difference (2) between the floating gate and the drain. X is expressed as follows. When erasing: Vc G=Vrp, Vo −Vs −
Since Vs s-〇■, Vr-V. X-C1XVFF/C-cho -----(2)
When writing: Vc G=Vs *-OV, VD -VF
Since F, V, -VC (5V), Vr'' (C3XVP F +C4XVt
)/CT----(QAt this time, the potential difference Vox between the 70-ting gate and the drain is given by VP P-Vr, so V,, = ((C,1tc2+(,4-)
Vpp-C4・Vs E/CT ------(4) However, CT-01+02+03+04. Potential difference V between floating gate and drain. To increase the electric field in the tunnel oxide film,
The potential Vr of the floating gate may be made high during erasing, and the potential Vr of the floating gate may be made low during writing. To realize this, from the above equations (1) to 4), the ratio (C1/CT
) and decrease the ratio (C:3/CT) between the total ICT and the floating gate-drain capacitance 1c3. Furthermore, in order to ensure charge tunnel injection between the floating gate and drain and to sufficiently change the threshold voltage of the memory transistor, it is desirable to apply as high an electric field as possible to the tunnel region. It is desirable to make the seawall as thin as possible. Generally, in order to increase (reduce) the capacitance, the area and permittivity of the dielectric region must be increased (reduced).
The film thickness must be made thinner (thicker). therefore,
If the thickness of the tunnel oxide film is reduced in order to apply a high electric field to it, the capacitance between the floating gate and the drain will increase, so to avoid this, it is desirable to keep the area of the tunnel oxide film as small as possible. . [Problems to be Solved by the Invention] Since a conventional nonvolatile semiconductor memory device using a single layer of polysilicon gate is arranged as shown in FIG. 2A, the area of the tunnel region is smaller than that of the floating gate. It is limited by the polycrystalline silicon that constitutes it and the processing dimensions of the active region. For example, in the case of a 2 micron rule process, it is impossible to reduce the area of this region to less than 2 microns x 2 microns. Therefore, in order to reduce the area of the tunnel region and the area occupied by the memory cell, a finer manufacturing process is required. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to eliminate the above-mentioned problems and provide a semiconductor memory device that uses the same manufacturing process as the conventional one and includes memory cells that are smaller than the conventional one. [Means for Solving the Problems] A nonvolatile semiconductor memory device according to the present invention has an ffl? l! The thickness of the tunnel insulation Tf4 (yt'm body film) is made thinner than the other gate insulation films, and the tunnel insulation Tf4 (yt'm body film) is formed with a minute area. [Operation] In the memory transistor of the nonvolatile semiconductor memory device according to the present invention, an N+ region is formed by lateral diffusion from the drain region directly under the floating gate. An insulating film (dielectric ([) 1 region) is provided between this lateral diffusion region and the floating gate, which is thinner than other gate insulating films (dielectric films) and narrower than the floating gate width.
A tunnel region with a minute area is formed. therefore,
Due to the thin dielectric hood in the tunnel region, a high electric field is applied between the floating gate and the drain, and the small area allows the floating gate-drain space ω to be reduced, for example, in a 2-micron process. A tunnel region with an area of 2 microns by 0.4 microns (lateral diffusion length) is obtained, allowing the footprint of the memory cell to be reduced using conventional manufacturing processes. [Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 18 to 1C are diagrams showing the arrangement of memory cells of a nonvolatile semiconductor memory device according to an embodiment of the present invention, in which FIG. 1A shows a planar arrangement, and FIG.
Figure 1C shows the cross-sectional structure along line A-A in the figure.
It is a figure which shows the cross-sectional structure along the BB line of A figure, respectively. As seen in Figures 18 to 1C, the second
Unlike the conventional semiconductor memory devices shown in FIGS. A and 2B, no protruding portion is formed on the drain 3 of the memory transistor 19. Further, the active region 2 is formed in an L-shape, and the thin gate oxide film 15 formed thereon is also formed in an L-shape. Further, as a feature of the present invention, a thin gate oxide film (tunnel insulation film) 17 having a small area is provided using a manufacturing process similar to the conventional one. The tunnel region 18 where the tunnel oxide 1117 and the 70-ting gate 13 overlap is arranged to overlap with the N+ diffusion region formed by lateral diffusion of the drain 3 directly under the floating gate 13. Further, the film thickness of tunnel oxide y417 is made thinner than the film thickness of other gate oxide film regions. Furthermore, its width (first
(in the lateral direction in FIG. A) is made narrower than the lateral width of the floating gate 13 in this region. 30
is the field oxide film. Next, the operation will be explained. The structure of the equivalent circuit of the memory cell and the capacitor ffi connection circuit shown in FIGS. 18 to 1C is the same as the conventional one shown in FIGS. 3 and 4. However, unlike the conventional device, the floating gate-drain capacitance IC3 is made smaller than the conventional device due to the small area of the tunnel region 18, and an electric field is applied to this region due to the thin S thickness. Thereby, charge can be sufficiently injected between the gate and the drain. Sufficient charge injection to sufficiently shift the threshold voltage of a memory transistor is important in terms of write durability, memory retention characteristics, etc. of a semiconductor memory device. As shown in equation (1)-<4), the tunnel region 18
By applying a sufficiently high electric field to the floating gate 13
In order to increase the charge injected into the floating gate-drain potential difference V. It is necessary to increase A and reduce the thickness of the tunnel oxide film. On the other hand, Tunnel Territory IIi! If a sufficiently high electric field can be obtained at 18, it is also possible to lower the value of the applied high voltage Vrr. In order to increase the potential difference between the floating gate and the drain during erasing, it is sufficient to increase the capacitance IC1 between the floating gate and the control gate according to equation (2). Depending on the embodiment of the present invention, the capacity will not be smaller than that of the conventional example. This is because both the control gate 5 and the second gate oxide 11115 are formed in an L-shape, and their film thickness is the same as before, so the area of the capacitance formed by this region will not be smaller than before. That's because there isn't. Further, other capacitances can be easily optimized because the thickness of each oxide film can be set individually. Furthermore, in order to increase the potential difference VOX between the floating gate and the drain during writing, the capacitance between the floating gate and the drain can be made smaller according to equation (3). The film thickness of this region is made thinner in order to apply an alt field to the region, but the area is much smaller than before, so the capacitance between the floating gate and the drain can be reduced. In the conventional method, the minimum area of this tunnel region is given by the product of the minimum dimensions of the floating gate and the active region process, but in this invention,
The minimum area is the product of the lateral diffusion distance of the drain and the minimum dimension of the process! ￥5ff compared to before.
This can be done by reducing i. As described above, it is possible to inject sufficient charge into the floating gate by applying a higher electric field to the tunnel 1Jil+ than in the past, and also to reduce the area occupied by the tunnel 'AM, so that the memory It becomes possible to reduce the area occupied by the cell. Further, in the above practical example, the insulating film in the tunnel region is explained as an oxide film, but the invention is not limited to this, and the same applies when it is formed with a two-layer or multilayer structure of a nitride film, an oxide film, and a nitride film. effect can be obtained. [Effects of the Invention] As described above, in this invention, the tunnel region is formed in a very small area at the portion where the lateral diffusion distances of the floating gate and the drain overlap, so that the capacitance of the tunnel region can be reduced. This makes it possible to reduce the area occupied by the memory i transistor and to realize a nonvolatile semiconductor memory device equipped with memory cells suitable for high integration. Furthermore, if the area occupied by the memory cell is the same as that of the conventional example, even if the value of the applied high voltage Vpp is lowered by the amount that the capacitance between the floating gate and the drain is reduced, a sufficiently large high electric field will be applied to the tunnel region. Since the voltage is applied to the l region, reliable writing/erasing is possible, and deterioration of the memory transistor due to high voltage application can be prevented. Thus, write durability according to this invention. A nonvolatile semiconductor memory device suitable for high integration can be realized without impairing reliability such as memory retention characteristics.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 18 to 1C are diagrams showing the configuration and structure of a semiconductor memory device which is a practical example of the present invention.
The figure shows the planar arrangement, Figure 1B schematically shows the cross-sectional structure taken along line A-A in Figure 1A, and Figure 1C schematically shows the cross-sectional structure taken along line B-B in Figure 1A. FIG. FIGS. 2A and 2B are diagrams of conventional non-ignitable semiconductor devices. !
FIG. 2B is a diagram showing the composition and structure of the mushroom, the second eighth factor is a diagram showing its planar arrangement, and FIG.
FIG. 2 is a diagram schematically showing a cross-sectional structure along a Japanese cypress. FIG. 3 is a diagram showing a logic circuit of a nonvolatile semiconductor memory device. FIG. 4 is a diagram showing a capacitive circuit constituted by parasitic capacitance formed in a memory cell of a nonvolatile semiconductor device. In the figure, 1.2 is an active region, 3 is a drain of a memory transistor, and 4 is a Memorized transistor source, 5
13 is a flow gate, 15 is a gate insulating film, 17 is a tunnel insulating layer, 18 is a 1-channel insulation layer, 19 is a memory 1 to 5 transistor, 2
0 is select, 1-ra>, jista.・'j6 In the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1A 13: Fuwarty〉7゛Kate 15: Ke2to #
]JIL 17: l->*rLJfl'#f
t(8: tunnel 4ψdp,, rQ:
Memo, Re-transistor ZO:"IL Okuranshi λ7 Figure 1B Figure 1C Figure 28 Figure 2B Figure 30 Figure 4 Procedural Amendment (Voluntary) 2.5d Name Nonvolatile Semiconductor Memory Device 3, Relationship with the case of the person making the amendment Patent Applicant Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation 5 Column 6 for the detailed description of the invention in the specification to be amended; Contents of the amendment (1) “Aluminum” on page 5, line 14 of the specification has been replaced with “
Corrected to "polycrystalline silicon." (2) Change the “selector” in lines 9 to 10 on page 6 of the specification to “
Correct to "Select". (3) "Control gate" on page 7, line 11 of the specification is corrected to "70-ting gate." (4) Replace “V,” in the second line of page 11 of the specification with “vcc”
Correct. that's all

Claims (6)

[Claims] (1) A conductor surrounded by a dielectric material and arranged in a first predetermined region on the semiconductor substrate to accumulate charge; and a conductor formed in a second predetermined region on the surface of the semiconductor substrate. an impurity diffusion layer, and a control region for controlling charge accumulation and release of the conductor.
What is claimed is: 1. A nonvolatile semiconductor memory device including at least a type transistor, characterized in that a dielectric formed between the conductor and the semiconductor substrate has a partially different thickness. (2) The nonvolatile material according to claim 1, wherein the conductor is made of polycrystalline silicon, and the dielectric between the semiconductor substrate and the conductor is partially thinned. semiconductor memory device. (3) The partially thinned dielectric region includes the MO
The nonvolatile semiconductor memory device according to claim 1 or 2, wherein the nonvolatile semiconductor memory device is formed in a region in contact with one end of an impurity diffusion region forming one conduction region of an S-type transistor. (4) The nonvolatile semiconductor memory device according to any one of claims 1 to 3, wherein the dielectric is formed of an oxide film. (5) The nonvolatile semiconductor memory device according to any one of claims 1 to 3, wherein the dielectric is formed of a nitride film. (6) The nonvolatile semiconductor memory device according to any one of claims 1 to 3, wherein the dielectric is formed of two or multiple layers of a nitride film and an oxide film.