JPS6250939A - Dual port memory - Google Patents

Abstract

PURPOSE:To transmit a random and serial port asynchronously by controlling the connection between a memory cell array and a serial data buffer with a write and read pointer, and controlling the connection between a data buffer and the serial data buffer with an input/output pointer. CONSTITUTION:Two data buffers 30 are provided between a memory cell array 10 and a serial port 40, and the connecting relation is controlled by a write pointer 37 and a read pointer 33. The connecting relation of the buffers 30 and a serial data buffer SDB is controlled by an output pointer 38. Here, by the level of the writable signal, the mode to read and write the memory cell is determined, and respectively, the read or write transmitting cycle signal is set. At present, a read data transmitting cycle signal is '1', then, a switch 35 is turned on, the read data are sent from the array 10. When a write data transmitting cycle signal is '1', a switch 36 is turned on, and the buffer data designated by the FF for the write pointer are sent to the array 10 by a switch 37.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a dual port memory having a serial port.

[Prior Art] A dual port memory has a serial port that can serially input and output data independently of the input and output of a random access port, and has begun to be put into practical use.

Dual-port memory is advantageous in that random access and serial input/output can be performed almost independently. Hence, Siri.

Since the random access performed by the CPU can be executed by almost 100% in parallel with the input/output of the memory, the memory can be rewritten quickly. Therefore, when used as an image memory, its display performance and drawing performance can be easily improved.

There are two types of serial ports currently announced:

The first type uses a shift register as a serial data buffer. This type has a problem in that input/output is possible only from the beginning of a line (ROW') on one screen, and input/output from the middle of the line is impossible. Also, data on the same line that is not serially input is also shifted all at once.

There is a problem in that the data in the part that is not serially input cannot be saved. Furthermore, there is a problem in that the above type cannot be input/output following the primary line.

On the other hand, as a second type, there is a dual port memory that can continuously output serial data for a certain length or more. This type uses a data buffer and a serial selector.

In the second type, in order to perform continuous operation to the next line, it is necessary to synchronize the read/write transfer cycle (data transfer cycle) to the data buffer with the clock at the serial port. For this purpose, a data transfer cycle is performed outside the storage device.
There is a problem in that the serial port clock must be synchronized. In other words, it is necessary to synchronize the random access port and the serial port, and in order to achieve this synchronization, there is also the problem that a portion of the internal part must be made into a high-speed circuit.

[Object of the Invention] The present invention has been made by focusing on the problems of the prior art described above, and allows data of any length to be input/output from any address, and completely asynchronously connects a random access port and a serial port. The purpose is to provide a serial port that can input and output data using standard speed circuits.

[Summary of the Invention] The present invention provides a serial data buffer that allows data of any length to be input/output from any address and to input/output completely asynchronously between a random access port and a serial port. The data buffer is selected by three pointers: a read pointer, a write pointer, and a serial input/output pointer to the data buffer. Furthermore, when the input/output mode of the serial port changes, the above three pointers are set.

[Embodiments of the invention] FIG. 1 is a block diagram showing one embodiment of the present invention.

This embodiment includes a memory cell array 10 as a storage section, a random access port section, a serial port section, and a timing generator 70.

As the above random access part, the row address X /<
A buffer 11, a row address decoder 12, a column address buffer 13, a column address decoder & selector 14, and a data buffer 15 are provided.

Also, as the serial port part, a data transfer gate 20 and a double serial data buffer 30 are included.
, a serial data gate 4°, an input/output data buffer 40a, a serial shift register 50, a serial address buffer 60a, and a serial address decoder 60.

FIG. 2 is a circuit diagram showing details of the serial port section, and is a circuit diagram focusing on one memory cell (i bit) in the memory cell array 10.

Therefore, in reality, the circuits shown in FIG. 2 are arranged in the horizontal direction for a predetermined number of bits.

FETs 21 and 41 are provided as the data transfer gate 20 and the serial data gate 40, respectively.

The double serial data buffer 30 is provided with two buffers that hold serial data. This switching of the double serial data buffer 30 is performed in the above-mentioned 3.
Two pointers do.

That is, the write pointer 37 and the read pointer 33
and the input/output pointer 38 according to their respective operations.
Controls which data buffer among the double serial data buffers 3° is selected.

In other words, as the double serial data buffer 30,
Serial data buffer 31 (also referred to as serial data buffer OJ) and serial data buffer 32 (r
(also referred to as "serial data buffer 1"), and switches 33, 34, 35, and 36 that select and control data connection relationships according to various pointers, modes, and cycle states.
37, 38, 39, and an AND circuit 30a and NOR circuits 33a and 34a that operate together with switches 33 and 34 to provide a load pulse to the serial data buffer.
It consists of

The serial shift register 50 and the serial address decoder 60 each have a shift register 51 . AND circuit 52) One decoder 61 is provided.

FIG. 3 is a circuit diagram showing a specific example of the timing generator 70.

AND circuit 7 that creates a data transfer enable signal
1 and flip-flops 72-76 for storing various modes or cycle states.

Flip-flop 72 indicates the serial operation mode (serial in or serial out), flip-flop 73 indicates that a data transfer cycle is in progress, and flip-flop 74 indicates that a data transfer cycle is in progress. The flip-flop 75 indicates that the write data transfer cycle is in progress, and the flip-flop 76 is in either serial out/serial in mode. It shows that.

AND circuits 72a, 74a, and 75a are circuits that generate set clocks or input data for flip-flops 72-76.

The AND-NOR composite circuit 77 is a flip-flop 72
A serial pointer reset signal is generated in the cycle in which the serial pointer changes.

AND circuits 78 and 79 are circuits that generate respective load clocks (serial register load clock signal and serial data buffer load signal).

In addition, flip-flops 80, 81, 82 and 83 hold the states of the read pointer, line pointer, serial input/output pointer for the θth data buffer, and serial input/output pointer for data buffers other than the θth data buffer, respectively. It is something to do.

AND circuit 82a and inverter 83i supply inverted signals to flip-flops 82 and 83, respectively.

Next, the operation of the above embodiment will be explained.

FIG. 4 is a time chart showing the operation of the data transfer cycle.

This time chart shows data exchange between the memory cell array 10 and the double serial data buffer 30.

The data transfer cycle is executed when the condition of the AND circuit 71 is satisfied at the timing when the row address strobe signal becomes active (when the leading edge differential signal is generated). That is, at the beginning of a memory cycle, a data transfer cycle is started by the output enable signal being "0", and the data transfer cycle signal is set.

This turns on data transfer game 20 during this cycle.

The level of the write enable signal at this time determines the memory operation mode (that is, the mode that specifies whether to read or write to the memory cell array 10 in the data transfer cycle), and the read data transfer cycle signal or the write data Transfer cycle signal is set.

Next, depending on the level of the write enable signal at the timing when the column address strobe signal becomes active (when the leading edge differential signal of the column address strobe signal is generated), the serial operation mode
The contents of the input/output mode of the serial host are determined.

This value is transferred to flip-flop 76 in serial out/serial in mode at the timing when the column address strobe signal becomes inactive. At this time, if the serial operation mode has changed compared to the previous value, the output of the composite circuit 77 becomes rOJ,
The pointers of flip-flops 80-83 are all reset.

Next, the read data transfer cycle signal is “1”
At this time, the input condition of the AND circuit 79 is satisfied at the timing (timing at which the column address strobe signal becomes inactive). Therefore, a serial data buffer load signal is output, and a load strobe pulse to the -serial data buffer 2a is supplied through the switch 33, 33a or 34a shown in FIG.

Since the read data transfer cycle signal is "1" and the switch 35 is turned on, the memory cell array l
Read data from O is supplied. Also, at this time, a strobe pulse is applied to the data buffer specified by the read pointer flip-flop 80.

Next, the write data transfer cycle signal is “1”
At this time, the switch 36 is turned on. At this time, the data in the buffer designated by the write pointer flip-flop 81 is selected by the switch 37 and transferred to the memory cell array 10 (416).

In the above data transfer cycle.

Data transfer is performed between memory cell array 10 and data buffer. The memory cell array IO is specified by the row address in the leading edge differential signal.

On the other hand, the column address is taken into the serial address bar 2 at the timing of generation of the leading edge differential signal of the column address strobe signal. This address value is transmitted to the serial address decoder 60, and the output of one serial address decoder 61 that matches this decoded value is
It becomes "1".

In this state, when the trailing edge differential signal of the column address strobe signal is generated, the serial port is in the idle state F.
! On the condition that the serial enable signal is "0", the AND circuit 78 is established and the load clock signal is output. This provides the serial shift register 50 with a load clock. Then, the serial shift register 51 corresponding to the decoder 61 whose output is "1" is set.

After this, the data transfer enable signal becomes "0" at the leading edge differential signal of the primary row address strobe signal (in this case, the data transfer cycles are not continuous). Therefore, the data transfer cycle signal , read data transfer cycle signal,
All write data transfer cycle signals are reset. As a result, the flip-flop 80 as a read pointer or the flip-flop 81 as a write pointer is inverted and alternately selects a data buffer every time a data transfer cycle is completed.

FIG. 5 is a time chart showing data exchange between the double serial data buffer 30 and the input/output data buffer 40a.

The dot clock signal and the enable signal are external signals, and based on these, the serial enable signal and the serial clock signal are generated externally. Now, assuming that the value of the serial address buffer 760a is 253, the load clock signal causes the serial counter 2 to
53 is on.

When the serial enable signal = "l", the AND circuit 52 turns 5E253 into rlJ, and only the 253rd gate 41 becomes conductive. - Now, the serial operation mode signal = "0", the serial in signal (inverted serial out signal) signal)=rl'', the switch 39 supplies the data on the serial data bus as data to the data buffers 31 and 32. When the serial clock arrives in this state, the NOR circuit 30a is established and a strobe pulse is applied to the data buffer γ designated by the switch 34.

Serial operation mode signal = ``rl''.

When the serial out signal is set to "1", switch 38.
39, the data of the 253rd serial data buffer is transmitted to the serial data bus. 1-bit data transfer is executed between the double serial data buffer 30 and the serial data gate 40 by 0 or more.

In parallel with the above operation, when the serial shift clock is turned on, the serial shift register 50 performs a shift operation at this trailing edge, so that the 5C254 is set. As a result, the first shift clock cycle is entered, and the serial transfer is stopped.

When 5C255 is set, a serial runout signal is outputted by the AND circuit 82a, the serial input/output pointer for 0 bits is inverted at the leading edge, and the serial input/output pointers for bits other than 0 are inverted at the trailing edge.

In addition, as shown in FIG. 1, a serial shift register 5
Since the final stage output of 0 is connected to the 0#I-th data input, the next one after 5C255 is 5CO (zero). At this time, the O bit serial input/output pointer is inverted by the serial runout signal. Switch 3
4.38 specifies the primary buffer.

The reason why the 0-bit serial input/output pointer is inverted at the leading edge is to switch the 0-bit switch 38 at an early timing to compensate for the delay of one circuit.

As described above, the read pointer is inverted by executing the read data transfer cycle, and the write pointer is inverted by executing the write data transfer cycle. Further, the serial runout signal inverts the serial input/output pointer. These illustrate the operation of alternately selecting double serial data buffers.

Next, a specific operation of serial out/serial in, which is a combination of the above operations, will be explained.

FIG. 6 is a time chart showing the serial out operation in the above embodiment.

First, data A starting from the middle of a certain line, data B of the next line, data C of the next line, and data D up to the middle of the next line are sequentially processed from the memory cell array IO. Assume that data is read and serially output. The data read from the memory cell array 10 is alternately held in two buffers forming the double serial data buffer 30 for one life each. The above two buffers are "Buffer O" and "Buffer 1" respectively.

First, at time T1, an external controller performs a dummy serial-in (SI) data transfer in combination with a zero-order original serial-out (SO) data transfer to transfer all pointers. Reset.

At time T2, read transfer is performed. At this time, since the read pointer signal is "0", data A is taken into buffer "0", the start point of data A is given by the column address, and the read pointer signal is switched to "1". At time 0 T3, read transfer is executed and the read pointer signal is "1", so data B is taken into "buffer l" and the read pointer is switched to rOJ.

Then, at time T4, when the serial enable signal rises, serial out of data A is executed.

When the serial output of data A is completed, the timing generator 70 outputs a serial runout signal. As a result, the input/output pointer signal becomes "1", and by this switching of the input/output pointer, execution of serial out of data B begins.

The external controller executes read data transfer for the primary data C by detecting this serial runout signal. As a result, data C is taken into "buffer O" and the read pointer signal is switched to "1".

At the timing when the serial enable signal is 1, the above operation is repeated and the serial out operation continues. If the external controller wants to complete the data in the middle, it can complete the serial output by setting the serial enable signal to "0".

FIG. 7 is a time chart showing the serial-in operation in the above embodiment.

The difference between this operation and the serial out operation shown in FIG. 6 is that a dummy serial out (S
O) Execute a data transfer cycle and reset all pointers in the next serial-in data transfer cycle. Furthermore, before serial input, the previous memory data is set in the data buffer by redundant data transfer, and even if data is input from the middle of the row, the part that will not be serially input. so that the data does not change.

Further, after a write data transfer is executed by detecting a serial enable signal, a read data transfer involves an operation of reading the contents of the next row into the memory and setting it in the data buffer.

Furthermore, after setting the serial enable signal to "0", the controller performs an operation of writing the last data into the memory by write data transfer in order to completely terminate the operation, and the controller terminates the operation. .

Note that another storage section may be used instead of the memory cell array 10.

[Effects of the Invention] According to the present invention, data of any length can be input and output from any address, data can be input and output completely asynchronously between a random access port and a serial port, and only a normal speed circuit can be used. It has the advantage that it can be operated with

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a circuit diagram showing details of the serial port portion in the above embodiment, and is a circuit diagram focusing on one memory cell (I bit) in the memory cell array. 3rd rgJ is a circuit diagram showing a specific example of a timing generator. FIG. 4 is a time chart showing the operation of the data transfer cycle. FIG. 5 is a time chart showing data exchange between the double serial data buffer and the input/output data buffer. FIG. 6 is a time chart showing the serial out operation in the above embodiment. FIG. 7 is a time chart showing the serial-in operation in the above embodiment. 10... Memory cell array, 20... Data transfer gate, 30... Double serial data buffer. 40...Serial data gate. 50... Serial shift register, 60... Serial address decoder, 70... Timing generator. Fig. 1 IF5
.

Claims (6)

[Claims] (1) Two data buffers provided between the storage section and the serial port; A write pointer and a read pointer that control the connection relationship between the storage section and the data buffer; The data buffer and the serial data A dual port memory characterized by having: an input/output pointer for controlling a connection relationship between the memory and the buffer. (2) In claim 1, resetting the pointer is achieved by resetting the pointer when a change in the input/output mode of the serial data buffer specified by a data transfer cycle occurs. Dual port memory characterized by: (3) In claim 1, the write pointer and the read pointer operate independently of each other, and when the execution of the data transfer specified by each pointer is completed, the pointer is inverted. Dual port memory characterized by: (4) The dual port memory according to claim 1, wherein the input/output pointer is inverted when the serial select address designated by the serial address buffer runs out. (5) The dual port memory according to claim 4, wherein the dual port memory outputs the runout signal. (6) In claim 1, the input/output pointer is characterized by comprising a pointer for a serial data buffer at address 0 and a pointer for serial data buffers at addresses other than address 0. Dual port memory.