JPS6250792A - Image memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an image memory suitable for image signal processing.

[Background of the invention]

Conventional examples of image memory used in image signal processing for TVs, VTRs, etc. include Nikkei Electronics,
In the February 11, 1985 issue, 362, the eldest author, Hara, describes an image-dedicated serial input/output type dynamic camera with a 320-row x 700-column configuration for the field system of 1 TV and VTR.
This is discussed in the document entitled Memory 1.

FIG. 3 shows a boot diagram of an example of an image-only dynamic memory of the field memory discussed in this document.

This image memory is provided with a data register 117 having a capacity for one line (one line is one horizontal scanning line), and in particular, it inputs continuous serial data from the input terminal 101 for one line at high speed, and outputs it. Output to terminal 102 at high speed.

In this case, 120 is a data buffer, and terminal 110
Data input/output is controlled by the serial control a-left signal SC from the terminal 109 and the write enable signal v from the terminal 109. 118 is a select circuit, which outputs the serial control a-left signal SC shifted by the shift register circuit 119;
The address of the data register 117 to which the data buffer 120IC is connected is determined. Transfer between this one line of data register 117 and field memory cell 115 is performed through gate circuit 116, and terminal 10
8) a-p signal RAS and terminal 10
It is controlled by the write enable signal WE from 9. By doing so, it is possible to reduce the transfer speed between the data register 117 and the field memory cell array 115, and to input and output serial data to and from the image memory without speeding up the operation of the field memory cell array 115. This makes it possible to increase the speed.

In the embodiment of FIG. 3, a refresh control address counter 111 is controlled by the refresh control a-left signal REF from the terminal 103, an up clock signal TNC and a down clock signal D from the terminals 104 to 106.
A row address counter 112n controlled by EC and a reset signal RCR is built-in, and a multiplexer 113
The field memory cell 115 is automatically refreshed and row addressed through the decoder 114 and is designed to be conveniently used as an image memory.

However, the memory actually used for image processing is
It is more often used in frame units such as one or two frames than in field units, and the conventional example described above uses a large number of memory ICs and requires a complicated external control signal.

[Purpose of the invention]

In view of the problems of the conventional example, an object of the present invention is to have a frame unit capacity of one frame or two frames,
Another object of the present invention is to provide an image memory convenient for use as an image signal processing memory.

[Summary of the invention]

In order to achieve the above object, in the present invention, the capacity of the image memory is set in frame units of 1 frame or 2 frames, and for example, in the case of 1 frame, the output is delayed by 1 field, and in the case of 2 frames, the output is delayed by 1 field, or by 1 field or 1 frame in the case of 2 frames. In addition to providing an intermediate tap such as a frame delay output, an address control circuit is provided in the image memory that can arbitrarily set the read address and write address positions of the memory cell by external synchronization, for example.

[Embodiments of the invention]

FIG. 1 shows an embodiment of an image memory using the present invention.

In this embodiment, the capacity of the image memory is one frame, and the description will be made assuming that a one-field delayed output signal is derived as the intermediate tap output.

In FIG. 1, 1 is an input terminal for rubit image digital data, 2 is an output terminal for image data delayed by one field, 3 is an output terminal for image data delayed by one frame,
4 is an input terminal of, for example, a vertical synchronization VD, 5 is an input terminal of, for example, a horizontal synchronization HD, 6 is an input terminal of a clock phase-synchronized with the data sampling clock, 7 is a frame memory cell, 15 to 17 are data buffers, 9 to 11 is a data register; 12-14 is a select circuit that determines which address of each data register 9-11 and each data buffer 15-17 is to be transferred with data; 8 is each data register 9-11 and a frame memory self. a selection circuit that determines which column address data is to be transferred between;
8 is the row address of the frame memory self, the column address of the select circuit 8 in block units, and the select circuits 12 to 1.
This is a timing and address control circuit that generates a column address for each dot of 4. The circuit operation will be briefly explained below.

Lubit serial image digital data from the input terminal 1 passes through a data buffer 15 and a select circuit 12, and is led to a data register 9 at one end.

A control signal specifying which address in the data register 9 is to be transferred is sent to the timing color address generation circuit 18.
It is obtained by decoding the output love code circuit 28 of the dot counter 27 inside.

If this data register 9 is filled with, for example, N dots, the data of N dots is set as one group and passes through the selector circuit 8, and the data is transferred to the frame memory self in blocks.

The control signal that specifies which column address of the frame memory cells this block unit data is transferred to is the block counter 2 that counts N dots as one block.
It is obtained by decoding the output of 5 in the decoding circuit 26. When this column address becomes full, for example with M blocks, the row address is changed. The control signal specifying this row address is sent to the multiplexer 25 by the output of the write address counter 22 that counts M blocks as one column.
It is obtained by decoding the signal in the decoding circuit 24. The data written in the frame memory self as described above is transferred to the data registers 10 and 11 in blocks through the select circuit 8. The control signal that specifies which row of data in the frame memory self is to be transferred is a signal obtained by decoding the output of the read address counter 21, and a circuit that provides an offset of one field to the output of the read address counter 21. The output of 20 is decoded and given. That is, the row address signal of the data transferred to the data register 10 is given by the output of the field offset address circuit 20, and the row address of the data transferred to the data register 11 is given by the output of the read address counter 21. Further, a control signal specifying which column of data in the frame memory self is to be transferred is incremented by 4 in the block counter 25 in the same manner as in writing. The block unit data delayed by one field with respect to the input data to the data register 10 transferred in this way and the block unit f-data delayed by one frame to the data register 11 are transferred to the select circuits 15 and 14. The data is converted into serial data in the opposite manner to that during writing, guided to data buffers 16 and 17, and output from terminals 2.3.

As described above, the feature of the embodiment of the present invention shown in FIG. 1 is that data is transferred between the write data register 9 and the frame memory self, and between the read data registers 10 and 11 and the frame memory self in units of blocks. During this one read period, data is read from the frame memory self twice with different row addresses, and the data register 10 is
, 11 and data transfer from the write data register 9 to the frame memory self once. In this way, for one data write to the frame memory self, by reading data twice with a different row address by one field, data delayed by one frame and data delayed by one field can be read. can be easily obtained as output.

In the embodiment of the present invention shown in FIG.
There are four points to consider, such as how to deal with the time difference in dot units between data delayed by one field and data delayed by one frame, which are obtained by reading twice during the interval.

First, as a refresh method, a refresher address 19 is provided in the timing color address generation circuit 18, and the refresher address 19 is set in the timing color address generation circuit 18, and the refresher address is set in the busy column direction every one block period, thereby automatically performing seven refreshes. ■The block time delay caused by the data registers 9 to 11, on the order of $, can be achieved by, for example, providing two block counters 25, one for reading and one for writing, the frame memory self in the select circuit 8, the nine data registers, and the data register 10,
This can be handled by changing the transfer address between 11 and 11. ■The time difference in dot units between data delayed by 1 field and data delayed by 1 frame is, for example, when data delayed by 1 field is read from the frame memory self first, data delayed by 1 frame is delayed by 1 field. Since there is a delay with respect to the data, this can be handled by providing a delay circuit (for example, a shift register) for the data that is delayed by one field by the delay. Also, for example, the data registers 10, 11 and the select circuit 15,
A shift register is provided between shift register 1 and
This can be handled by changing the selection timing for the 0.11 or laterator buffers 16 and 17 between the output side delayed by one field and the output side delayed by one frame.

FIG. 2 shows an embodiment of the present invention including the countermeasure circuit described above. In this one embodiment, a specific 7-ram memory cell 7
The size of 910 columns x 525 rows will be explained below.

In NTSC, if the relay frequency is selected to be 4 fzc (the subcarrier frequency of fsc and ama), one line will have 910 dots. Further, one frame has 525 lines. In this case, for example, the count number of the dot counter 40 is selected to be 35 dots, the unit of 110 dots for data transfer between data registers 9 to 11 and the frame memory self is set to 35 dots, and the count number of block counter 3 is set to 26 dots. If you select a block and the number of dots in one row of the frame memory self is 55 dots x 26 blocks = 910 dots, then one row of the frame memory self will be exactly 1.
This corresponds to a line, and has the advantage that the line address can be specified in line numbers. - In FIG. 2, 29 and 1 are shift register circuits, and the select positions of the select circuit 12 when writing data and the select circuits 15 and 14 when reading data are different, for example, the select circuit 12 is set to the dot counter 40.
Using the control signal obtained by decoding the output of , the select circuit 13 mixes the output of the dot counter 4o and the output of the L1 dot data 38 in the subtracter 39. Similarly, the select circuit 14 receives the dot data 41 using the control signal obtained by decoding the output with an offset corresponding to the dot.
By selecting the output with an offset of 4 dots obtained by the subtracter 42 using the decoded control signal, the timings of the output delayed by one field and the output delayed by one frame can be matched in units of dots. 35 is block data, block count 3
By mixing the output of 7 with the subtracter 36, an output having a block offset with respect to the neutral value of the block counter 37 is obtained. If these outputs are selected by multiplexer T45 during writing and reading, and the decoded output is used as a control signal for the select circuit 80, the column address of the transfer data during writing and reading can be switched, and the data It is possible to correct time delay errors in block units caused by registers 9-11. 31
is 262 line data, and by mixing it with the read address counter output that counts 525 lines in the subtracter 32, 26 lines corresponding to 1 field are generated for 525 lines.
An output with an offset of 2 lines is obtained, and by using the control signal decoded from this output as the row address, the row address of data delayed by 1 field and 1
The row address of frame-delayed data can be switched.

The above is an example in which one frame memory cell is used as a memory cell and data delayed by one field is output as an intermediate tap output. However, the present invention is not limited to the case where the memory cell is a 1-frame memory cell, but may be a 2-frame memory cell or a 3-frame memory cell, for example. Also, as an intermediate tap output,
For example, in the case of a 2-frame memory cell, data delayed by 1 field, data delayed by 1 frame, or data delayed by 3 fields may be used (or, multiple intermediate tap outputs may be provided for data.

In addition, in the explanation of the embodiment in FIG. 2, in the case of the NTSC system, the clock is 4 fzc, and one block is 35
Although the cell size is 525 lines x 910 dots, the present invention is not limited to these television systems or a/c frequencies; for example, the pAL system may be used.

Further, the clock frequency may be 5 fzc. Further, the number of dots per block may be arbitrary, such as 26 dots, 52 dots, or 64 dots.

Next, as an example of an embodiment of the present invention in which m memory cells of approximately one field are provided, an example in which two cells of approximately one field are provided will be described.

FIG. 4 shows an embodiment of this invention. This embodiment differs from the embodiments in FIGS. 1 and 2 in that it has two field memory cells 49 and 50, and by connecting these two field memory cells 49 and 50 in parallel, the field memory It can be used as a frame memory by connecting serially.

In FIG. 4, 44 and 45 are four input terminals for rubit image digital data, 46 and 47 are output terminals,
48 is an input terminal for a control signal that switches the input data of the select circuit 650; 53 to 56 are data registers; 51
, 52 is a select circuit that specifies data transfer between each field memory cell 49, 50 and data registers 53 to 56 in units of programs; 61 to 64 are data buffers; The selection circuit for specifying data transfer between the backs 761 to 64 in units of dots and other features are the same as in the embodiment shown in FIG.

This embodiment is characterized by two data input terminals 44,
45 and a select circuit 65, and when used in field memory mode, the select circuit 65 selects data from the input terminal 45 through the data buffer 62 and leads it to the select circuit 58, so that each input terminal 44
, 45 and field memory cells 49 , 50 and output terminals 46 , 47 are connected in parallel, and the output terminals 46 , 45 are connected in parallel.
Data delayed by one field from each of input terminals 44 and 45 is led to input terminal 7. When used in frame memory mode, the select circuit 65 selects the data buffer 63.
By selecting data delayed by one field from input terminal 44° field memory cell 49 . and guiding it to select circuit 58 . Output terminal 46. field memory cell 50
．． Output terminal 47 is serially connected. This results in
The output terminal 46 receives data delayed by one field, and the output terminal 47 receives data delayed by one frame.

In this way, by providing a plurality of memory cells for approximately one field and providing a selector circuit for switching the input/output of each field memory cell, the image memory can be easily switched between the field memory mode and the frame memory mode using an external signal. be able to. Furthermore, when used in frame memory mode, unlike the embodiment shown in FIG. 1, it is possible to easily obtain a signal with no delay error between field-delayed data and frame-delayed data.

FIG. 5 shows an example of the timing and address control circuit 18 used in the embodiment of the present invention shown in FIG. here,
A case will be described in which one row of field memory cells 49 and 50 corresponds to one line in NTSC, similar to the embodiment in FIG. 2.

In FIG. 5, 66 is a refresher address, 67
, 68 is an address counter whose count number switches between 262 lines and 265 lines for each field, and when one counts 262 lines, the other counts 265 lines, and the counter is reset by the vertical synchronization VD of terminal 4. be done.

69 is a block counter, the counter is reset by horizontal synchronization HD from terminal 5, and the output of counter 69 is led as a clock for address counters 67 and 68. 70 is a dot counter, which counts, for example, N dots using the clock CK from the terminal 5, and the output is led as the clock counter 69. 71-7
5 is a decoding circuit that decodes each counter output, and the output of the decoding circuit 74 is sent to the select circuit 51.5.
2 as a selection control signal, and the decoding circuit 7
The output of 5 is led as a control signal for selection of select circuits 57-60. Multiplexers 76 and 77 switch signals obtained by decoding the outputs of the refresh counter 66 and the two address counters 67 and 68, and lead them as refresh and address signals to the field memory cells 49 and 50, respectively. 78 is a multiplexer switching signal generator, which connects, for example, the field memory cells 49 and 50 to parallel I/c'm! When subsequently used in a field memory card, the same signal is output as the output of the two multiplexers 76 and 78. When connected serially and used in frame memory mode, the address signals derived from the two address counters 67 and 68 output signals that are opposite to each other. Whether it is used in the field memory mode or the frame memory mode, the discrimination signal is led from the terminal 48 to the switching signal generator 7, and the signals led to the two multiplexers 76 and 78 are either the same or opposite to each other. It can be easily switched depending on the source. Terminal 79 is an input terminal for a control signal for switching, for example, whether the field memory amount is 262 lines or 263 lines when used in the field memory mode. For example, in the case of 262 lines, the 262nd line is the read address counter in the odd field, and the 2nd line is the write address counter.
63 lines, and vice versa for even fields. 2
The case of 65 lines is the opposite of the case of 262 lines. When using this as frame memory mode,
For example, if the field memory output is 262 lines,
It is also possible to switch between 263 lines and 263 lines.

Although FIG. 5 has been explained in the case of the NTSC system, the present invention is not limited to the television system; for example, the PA
In the L method, the amount of delay in field memory mode is 312
It can be switched by line or 313 line. Furthermore, in the case of the two-frame configuration of the NTSC system, the two address counters 67 and 68 are both 525 line counters, and the same counters can be used.

FIG. 6 shows an embodiment in which a masking function is added to the embodiment of the present invention shown in FIG.

6, 80 and 81 are input terminals for masking control signals, 82 to 85 are shift registers,
In the embodiment shown in FIG. 4, a select circuit is used to select an address to a data register to convert serial data to parallel data in units of blocks, or to convert parallel data to serial data. Using the shift registers 82 to 85, directly input serial data to the shift registers 85 and 86 K, and lead it to the data registers 55 and 54 in parallel in block units, converting it to serial parallel data, and similarly converting it into parallel data. The case of converting data into serial data was used as an example. 85-88 are select circuits, which include input terminals 44, 45 and output terminals 46, 47.
The control signals from the terminals 80' and 81 are decoded by the decoding circuit 89 to generate signals α, h,
C.

It can be switched with d and -.

FIG. 7 shows a specific example of the decoding circuit 89 shown in FIG. 6. FIG. 8 also shows the decoding circuit 89 shown in FIG.
This shows which data is guided to the two field memory cells 49 and 50 by the select circuits 85 to 88 and the timing table address control circuit 18 controlled by the timing table address control circuit 18.

In FIG. 7, C90 is an exclusive NOR circuit, and if the control signals shown in FIG. 8 are input from two terminals 80 and 81 (Snow H1 indicates Higk, IL@ indicates LOW), the decoding circuit The output signals α to - of 89 become VC as shown in the figure. In addition, in FIG. 6, when the select signal h-a from the decoding circuit 89 is "H", the select circuits 85 to 88 select the left input signal, and the tying &
When the signal a from the decode circuit 89 to the address control circuit 18 is °H1, the field memory mode is set to 1L.
If the frame memory mode is set in the case of 0.degree., the data shown in FIG. 8 is introduced into each field memory cell 49, 50, respectively. In other words, when both terminals 80 and 81 are 1H, field memory mode is entered, and field memory mode is set.
The field memory cells 49 and 501c have input terminals 44°45
Current field data from is derived. In addition, the terminal 80
. This is the same as the embodiment shown in FIG. Next, terminal 8
When 0 is L° and terminal 81 is lH', the field memory mode is activated, and the masking function in field units operates, and field memory cells 49 and 50 receive data delayed by one field from output terminals 46 and 47, respectively. be guided. When the terminal 80 is "H" and the terminal 81 is "S", the frame memory mode is set, and the masking function is activated in units of frames, and the data delayed by one frame from the output terminal 47 is transferred to the field memory cell 49. Data delayed by one field from the output terminal 46 is led to the output terminal 50.

As described above, by using the embodiment shown in FIG. 6, a masking function can be easily added from the outside, and the field memory mode and frame memory mode can be easily used.

As described above, in one embodiment of the present invention shown in FIG. Although a shift register is used in the embodiment shown in the figure, the present invention is characterized in that it includes such a conversion means, but the specific method of the means may be a select circuit, a serial circuit, or any other method. good.

In addition, in the embodiment shown in FIGS. 4 and 6, data delayed by one frame and data delayed by one field are output in parallel, but four of these field memory cells are used to output data delayed by one frame. The data delayed by two frames and the data delayed by two frames may be output in parallel. Although not shown, data delayed by one field, data delayed by one frame, data delayed by three fields, and data delayed by two frames may be output to the circuit in parallel. It is also possible to provide a select circuit on the output side and to arbitrarily switch and output data delayed in units of fields using an external signal.

〔Effect of the invention〕

By using the present invention, an image memory capable of high-speed serial input/output and which can simultaneously obtain data delayed by one frame and data delayed by one field by simply inputting a clock signal and a synchronization signal can be created. This has the effect of simplifying the digital processing of image signals from televisions, VTRs, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image memory showing one embodiment of the present invention, FIG. 2 is a block diagram of an image memory showing another embodiment of the invention, and FIG. 3 is an example of a conventional image memory. FIG. 4 is a block diagram of an image memory showing another embodiment of the present invention, and FIG. 5 is a block diagram of a timing and address control used in the embodiment of the present invention shown in FIG. circuit 1
8 is a block diagram showing an example of the image memory 89, FIG. 6 is a block diagram of an image memory showing another embodiment of the present invention, and FIG. 7 is an example of the decoding circuit 89 used in the embodiment of the present invention shown in FIG. FIG. 8 is a diagram illustrating the operation of the embodiment of the present invention shown in FIG. 6 when the decoding circuit 89 shown in FIG. 7 is used. Explanation of symbols 1, 44, 45, 101...Image data input terminal 2, S, 46.47.102...Image data output terminal 4...Vertical synchronization VD input terminal 5...Horizontal Synchronous HD input terminal 6... Rack signal input terminal 7... Frame memory cell array 8.51.52... Select circuits 9-11 for transferring data between memory cells and data registers.53-56・-Data register 12 to 1
4.57 to 60, 118... Select circuits 15 to 17 that perform transmission between the data buffer and the data register or shift register. 61 to 64, 120... Data buffer 18... Timing & address control circuit 19, <56
, 111...Refresher address counter 20...
・Field offset address circuit 21.55...
Read address counter 22.54...Write address counter 25.45, 76.77.115...Multiplexer 24.26.28.71-75,89,11
4...Decode circuit 25.37.69...Glock counter 27.40.70...Dot counter 29.30.82-85,119...Shift register 31...262H data 32.36, 39.42 river subtractor 55...K7''a-tuck data 38.41...dot data 48.79-81.103-106, 108-110.
...Control signal input section 49, 50, 115...Field memory cell array 65.85-88...Select circuit for switching input/output signals 67,68,112...Address counter 78.
...Multiplexer 76,77 switching signal generator 116...Gate circuit 107 that transfers data between the field memory cell and the data register...Synchronous output terminal Lying down Patent Attorney Katsuo Ogawa Figure 3 Figure 5

Claims (1)

[Claims] It is equipped with either n memory cell arrays (n is an integer) with a memory capacity of m times the memory capacity of one field (m is an integer) or m x n memory cell arrays with a memory capacity of about 1 field, and n x k (k is an integer) memory cell arrays. a data register, means for transferring data between the memory cell array and the data register in parallel in block units, and inputting serial data from n input terminals to at least n data registers among the data registers; means for outputting serial data from at least 2n data registers to at least 2n output terminals; and means for controlling at least a row address of the memory cell array and data transfer between the memory cell array and the data register. and a signal for controlling data transfer between the data register and the input/output terminal, and at least a clock signal and a synchronization signal of the image signal or a signal equivalent to the synchronization signal as input signals of the circuit. At the same time, among the 2n output terminals, data delayed by approximately m fields is introduced to n output terminals, and data delayed by approximately m fields is transmitted to the other n output terminals with a delay of less than (m-1) fields and approximately in field units. An image memory characterized in that data delayed by an integral multiple of is simultaneously derived.