JPS6250017B2 - - Google Patents

Info

Publication number
JPS6250017B2
JPS6250017B2 JP56069178A JP6917881A JPS6250017B2 JP S6250017 B2 JPS6250017 B2 JP S6250017B2 JP 56069178 A JP56069178 A JP 56069178A JP 6917881 A JP6917881 A JP 6917881A JP S6250017 B2 JPS6250017 B2 JP S6250017B2
Authority
JP
Japan
Prior art keywords
terminal
blanking
external
external terminal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56069178A
Other languages
Japanese (ja)
Other versions
JPS57183182A (en
Inventor
Junji Sakamoto
Hiroyasu Kishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Denki Co Ltd
Original Assignee
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Denki Co Ltd filed Critical Sanyo Denki Co Ltd
Priority to JP6917881A priority Critical patent/JPS57183182A/en
Publication of JPS57183182A publication Critical patent/JPS57183182A/en
Publication of JPS6250017B2 publication Critical patent/JPS6250017B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/24Blanking circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Details Of Television Scanning (AREA)

Description

【発明の詳細な説明】 本発明はテレビ受像機のブランキング回路に係
り、特に集積回路等の回路ブロツクに設けた外部
端子に外部抵抗を介してフライバツクパルスを印
加し、該外部端子より水平及び垂直ブランキング
信号を導出できる同回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a blanking circuit for a television receiver, and in particular, a flyback pulse is applied to an external terminal provided on a circuit block such as an integrated circuit via an external resistor. and the same circuit capable of deriving a vertical blanking signal.

従来のテレビ受像機に用いる集積回路(以下
ICと称する)は、各種の信号を処理するため
各々入力信号を印加する入力端子、出力信号を導
出する出力端子が外部端子(端子ピン又は単にピ
ンと呼ばれることもある)として設けられてお
り、ブランキング信号を導出するブランキング回
路も、この様なピン数を減少させるという課題は
解決されていなかつた。
Integrated circuits (hereinafter referred to as integrated circuits) used in conventional television receivers
In order to process various signals, ICs are equipped with input terminals to apply input signals and output terminals to derive output signals as external terminals (also called terminal pins or simply pins). The problem of reducing the number of pins in the blanking circuit that derives the ranking signal has not yet been solved.

そこで本発明は前記欠点に鑑みなされたもの
で、以下図面に従つて説明すると、第1図は本発
明のブランキング回路、第2図イ〜ニは第1図の
各部波形を示し、はトランジスタ2,3より成
る比較器、は抵抗5,6より成る第1の分圧抵
抗回路網、7はエミツタ抵抗、8は負荷抵抗、9
はエミツタフオロア段、10は抵抗11,12よ
り成る第2の分圧抵抗回路網、13はブランキン
グ用トランジスタ、14はクリツプ用ダイオー
ド、15は外部端子、16は外部抵抗、17はフ
ライバツクパルス印加端子、18は電源端子、1
9はブランキングパルス印加端子、20は水平ブ
ランキング信号が得られる出力端子、一点鎖線内
はIC内部回路を示す。
The present invention has been made in view of the above drawbacks, and will be explained below with reference to the drawings. FIG. 1 shows the blanking circuit of the present invention, FIG. 2 A to D show waveforms of each part of FIG . A comparator consisting of transistors 2 and 3, 4 a first voltage dividing resistor network consisting of resistors 5 and 6, 7 an emitter resistor, 8 a load resistor, 9
is an emitter follower stage, 10 is a second voltage dividing resistor network consisting of resistors 11 and 12, 13 is a blanking transistor, 14 is a clip diode, 15 is an external terminal, 16 is an external resistor, and 17 is a flyback pulse application. Terminal, 18 is power supply terminal, 1
9 is a blanking pulse application terminal, 20 is an output terminal from which a horizontal blanking signal is obtained, and the area within the dashed line indicates the IC internal circuit.

次に本発明回路の動作について説明すると、端
子17には第2図ニに示すフライバツクパルスV
Dが加わり、ブランキング用トランジスタ13の
ベースには第2図ロに示す垂直ブランキングパル
スVBが印加される。
Next, to explain the operation of the circuit of the present invention, the terminal 17 receives a flyback pulse V as shown in FIG.
D is added, and a vertical blanking pulse V B shown in FIG. 2B is applied to the base of the blanking transistor 13.

このとき外部端子15には、第2図ハに示すよ
うに前記クリツプ用ダイオード14によつて、
(VCC+Vf)(Vfは該クリツプ用ダイオードの順
方向電圧)でクリツプされた波形が現われる。一
方端子19には前述の垂直ブランキング信号が印
加されているので、垂直ブランキング期間ブラン
キング用トランジスタ13がオフになり、エミツ
タフオロア段9のベース電圧はVCCR6/(R5
R6)となる。
At this time, the external terminal 15 is connected to the clip diode 14 as shown in FIG.
A waveform clipped at (VCC+Vf) (Vf is the forward voltage of the clipping diode) appears. On the other hand, since the above-mentioned vertical blanking signal is applied to the terminal 19, the blanking transistor 13 is turned off during the vertical blanking period, and the base voltage of the emitter follower stage 9 is VCCR 6 /(R 5 +
R6 ).

ここで抵抗11,12の値R5及びR6が等しい
場合(R5=R6)、前記エミツタフオロア段9のベ
ース電圧はVCC/2となる。
Here, when the values R 5 and R 6 of the resistors 11 and 12 are equal (R 5 =R 6 ), the base voltage of the emitter follower stage 9 becomes VCC/2.

前記フライバツクパルスVDのクリツプ波形と
前記垂直ブランキングパルスとが重畳されると、
全体として第2図ハに示す波形VCが端子15に
現われ、この電圧VCは水平及び垂直のブランキ
ング信号として別チツプのICに含まれている映
像増幅段に使用でき、水平及び垂直のブランキン
グが行える。
When the clip waveform of the flyback pulse V D and the vertical blanking pulse are superimposed,
As a whole, the waveform V C shown in FIG. Blanking can be performed.

又比較器の出力端子20には、水平ブランキ
ング信号として利用できる電圧VAが現われ一点
鎖線で示したIC内における水平ブランキングが
可能となる。
Further, a voltage V A that can be used as a horizontal blanking signal appears at the output terminal 20 of the comparator 1 , making it possible to perform horizontal blanking within the IC shown by the dashed line.

前記第1の分圧抵抗回路網の分圧点である比
較器の一方の入力端子の電圧V1を第2の分圧抵
抗回路綱10の(分圧点電圧−VBE)より高く設
定してあり、比較器の他方の入力端子の電圧
V2がV1より高くなるのはフライバツク期間のみ
で、トランジスタ3のベースがトランジスタ2の
ベースより高くなると、トランジスタ2がオン
し、負荷抵抗8に電流が流れ、端子20に前述の
通り電圧VAが現われることになる。
The voltage V 1 at one input terminal of the comparator, which is the voltage dividing point of the first voltage dividing resistor network 4, is set higher than (voltage dividing point voltage −V BE ) of the second voltage dividing resistor network 10 . and the voltage at the other input terminal of comparator 1
V 2 becomes higher than V 1 only during the flyback period, and when the base of transistor 3 becomes higher than the base of transistor 2, transistor 2 turns on, current flows through load resistor 8, and voltage V at terminal 20 as described above. A will appear.

以上の通り本発明によれば、IC等の同一回路
ブロツク内で生成された垂直ブランキング信号と
外部から印加されたフライバツクパルスとによつ
て、前記回路ブロツク内の端子に水平ブランキン
グ信号が得られると共に前記フライバツクパルス
が印加される外部端子から水平及び垂直のブラン
キング信号を導出でき、1個の外部端子で外部の
信号を内部に取入れ、内部の信号を外部に出力す
ることができる。
As described above, according to the present invention, a horizontal blanking signal is generated at a terminal within the circuit block by a vertical blanking signal generated within the same circuit block such as an IC and a flyback pulse applied from the outside. Horizontal and vertical blanking signals can be derived from the external terminal to which the flyback pulse is applied, and one external terminal can take in an external signal and output the internal signal to the outside. .

なお前述のクリツプ用ダイオードの代りにクリ
ツプ用のトランジスタを用いても同様の効果が得
られ、又、外部抵抗はフライバツクトランス源の
内部インピーダンスが小なる場合の補償用で最適
な値を選べば良い。
The same effect can be obtained by using a clip transistor instead of the clip diode mentioned above, and if the external resistor is used to compensate for the small internal impedance of the flyback transformer source, the optimal value can be selected. good.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のブランキング回路、第2図イ
〜ニは第1図における各部波形を示す。 主な図番の説明、……比較器、……第1の
分圧抵抗回路網、9……エミツタフオロア段、
0……第2の分圧抵抗回路網、14……クリツプ
用ダイオード、15……外部端子、16……外部
抵抗。
FIG. 1 shows a blanking circuit of the present invention, and FIGS. 2A to 2D show waveforms of various parts in FIG. Explanation of main figure numbers, 1 ...Comparator, 4 ...First voltage dividing resistor network, 9...Emitter follower stage, 1
0...Second voltage dividing resistor network, 14...Clip diode, 15...External terminal, 16...External resistor.

Claims (1)

【特許請求の範囲】[Claims] 1 一対の入力端子を有する比較手段と、該入力
端子の一方が接続されかつ電源電圧を分圧する第
1の分圧抵抗回路網と、前記入力端子の他方が接
続される外部端子及びエミツタフオロア段と、該
エミツタフオロア段の入力端が接続されかつ電源
電圧を分圧する第2の分圧抵抗回路網の一部にコ
レクタ・エミツタ路が並列に接続されたブランキ
ング用トランジスタと、前記外部端子と電源端子
との間に接続されたクリツプ手段とを備えた集積
回路等の回路ブロツク、該回路ブロツクの前記外
部端子とフライバツク印加端子との間に接続され
た外部抵抗とから成り、前記フライバツク印加端
子にフライバツクパルスを印加すると共に前記ブ
ランキング用トランジスタの入力端に垂直ブラン
キングパルスを印加し、前記比較手段の出力側よ
り水平ブランキング信号を導出し、前記外部端子
より水平及び垂直ブランキングパルスを導出する
ことを特徴としたブランキング回路。
1 Comparison means having a pair of input terminals, a first voltage dividing resistor network to which one of the input terminals is connected and divides the power supply voltage, and an external terminal and an emitter follower stage to which the other input terminal is connected. , a blanking transistor to which the input terminal of the emitter follower stage is connected and whose collector-emitter path is connected in parallel to a part of a second voltage dividing resistor network that divides the power supply voltage; and the external terminal and the power supply terminal. a circuit block such as an integrated circuit having a clip means connected between the circuit block and an external resistor connected between the external terminal of the circuit block and a flyback application terminal; At the same time as applying a back pulse, a vertical blanking pulse is applied to the input terminal of the blanking transistor, a horizontal blanking signal is derived from the output side of the comparing means, and horizontal and vertical blanking pulses are derived from the external terminal. A blanking circuit characterized by:
JP6917881A 1981-05-07 1981-05-07 Blanking circuit Granted JPS57183182A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6917881A JPS57183182A (en) 1981-05-07 1981-05-07 Blanking circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6917881A JPS57183182A (en) 1981-05-07 1981-05-07 Blanking circuit

Publications (2)

Publication Number Publication Date
JPS57183182A JPS57183182A (en) 1982-11-11
JPS6250017B2 true JPS6250017B2 (en) 1987-10-22

Family

ID=13395200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6917881A Granted JPS57183182A (en) 1981-05-07 1981-05-07 Blanking circuit

Country Status (1)

Country Link
JP (1) JPS57183182A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59105781A (en) * 1982-12-08 1984-06-19 Sanyo Electric Co Ltd Video signal processing circuit
JPH0636558B2 (en) * 1986-11-19 1994-05-11 株式会社日立製作所 Horizontal blanking pulse generator

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5394166A (en) * 1977-01-27 1978-08-17 Philips Nv Circuit partly contained in monolithic integrated semiconductor body

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5394166A (en) * 1977-01-27 1978-08-17 Philips Nv Circuit partly contained in monolithic integrated semiconductor body

Also Published As

Publication number Publication date
JPS57183182A (en) 1982-11-11

Similar Documents

Publication Publication Date Title
US4178558A (en) DC Level clamping circuit
JPS6250017B2 (en)
US5892555A (en) Video signal clamping circuit
JPS6339146B2 (en)
US3870898A (en) Frequency-to-voltage converter
US4800585A (en) Saturating bipolar switch circuit for telephone dial pulsing
KR100396353B1 (en) Input signal limiter and pulse limiter
JPH0533105Y2 (en)
JP2931713B2 (en) Clamp circuit
JP3038733B2 (en) Video signal processing circuit
JPH0522633A (en) Picture quality adjustment circuit
JPS6022862A (en) Power supply circuit
JP2553693B2 (en) Clamp circuit
JPS5941637B2 (en) Color signal processing device
JPH0514767A (en) Clamp circuit
JPS60154711A (en) Frequency doubling circuit
JPS6040730B2 (en) emitter follower circuit
JPS6258189B2 (en)
JPH0411426Y2 (en)
JPS58161424A (en) Switching circuit
JPS6224990B2 (en)
JPH01200714A (en) Pulse generation equipment
JPH08139574A (en) Sawtooth wave signal generation circuit
JPH0294811A (en) Level variable circuit
JPH0682496A (en) Voltage comparison circuit