JPS6249660A - Heterojunction bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To make an emitter area small in size substantially by a method wherein a semiinsulative layer, a part of which is converted into a vertically penetrating highly-doped n-type region, is provided on a highly-doped n-type base, and the emitter layer, the circumference which is converted into a highly- doped p-type region, is provided thereon. CONSTITUTION:A highly-doped n-type base layer 2 is formed on a semiinsulative or highly-doped n-type GaAs substrate 1, and a semiinsulative layer 11 and an InAs thin film layer are formed on the layer 2. Then, ions are implanted on the part 12 of the layer 11, and a highly-doped n-type region is formed. Subsequently, the InAs thin film layer is removed, and an n-type doped emitter layer 3 made of material having a large band gap, a highly-doped p-type base layer 4, an n-type doped collector layer 5, and a highly-doped n-type cap layer 6 are epitaxially grown successively. Then, a p-type region is formed vertically penetrating those regions of the layers 3 and 4 remaining after the emitter region, has been excluded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a heterojunction bipolar transistor that is promising as an ultra-high speed and ultra-high frequency transistor.

BACKGROUND OF THE INVENTION In recent years, heterojunction bipolar transistors, in which the emitter of a bipolar transistor uses a material with a larger bandgap than the base, have been actively researched as one of the leading candidates for ultra-high speed and ultra-high frequency transistors.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A conventional heterojunction bipolar transistor (hereinafter referred to as HBT) in which an emitter is provided on the lower side will be described below with reference to the drawings.

Figure 4+81 shows a conventional HBT with an inverse structure in which the emitter is located at the bottom, and Figure 4 (bl) shows a conventional HBT with an inverted structure in which the emitter is located on the lower side. It is.

In FIGS. 4(a) and (b), l is the substrate, 2 is a highly doped n-type layer, 3 is an emitter layer made of a material with a larger bandgap than the n-type doped base, and 4 is a highly doped layer. 5 is a p-type base layer, 5 is an n-doped collector layer, 6 is a highly doped n-type cap layer, 7 is a collector electrode, 8 is a base electrode, 9 is an emitter electrode, 10 is a highly doped p-type The region 14 is a heavily doped p-type (p') and n-type p'n junction made of a material with a large band gap.

The operation of the HBT constructed as described above will be described below from the viewpoint of emitter pace and base-collector junction capacitance.

f and f are indicators of high-speed operation of HBT.

is expressed as follows.

Here, r is the collector current, W is the base width, and ■3.
is the running velocity of electrons in the collector region, l is the width of the collector depletion layer, cty+ is the emitter-base capacitance, CCS is the collector-base capacitance, C1 is the stray capacitance, W is the base width, and D is the electron at the base. The diffusion coefficient, q, is a natural constant, and T is the absolute temperature.

In an HBT, hole leakage from the base to the emitter is suppressed by using a material with a larger bandgap than the base as the emitter, so the base is highly doped and the emitter and collector are lightly doped, contrary to normal bipolar transistors. can do. This makes it possible to reduce the base resistance, so f
l can be increased. Furthermore, in general, in bipolar transistors, CEI and C0 are factors Ctm (n, h) and Ccx (n
, h) and the junction area AEII, Act. In HBT, the emitter and collector are lightly doped and the base is highly doped, so C□(n, h), Cc
i (n, h) depends only on the doping of the emitter and collector, and CEl1% CC1 is as follows.

CtwocJ nt ・AEI, CcmocJ n
c ・Ace Therefore, HBT has CE8% smaller CCI than normal bipolar transistor and rT
It is possible to increase the Furthermore, by reducing the transistor size and reducing the AEI% ACI, the C
Since EII+CCII can be made smaller, higher speeds and higher frequencies are possible.

In the configuration shown in FIG. 4(a), since the emitter is provided on the lower side, it is suitable for integration with a common circuit configuration for the emitters, and since the collector is on the upper side, the collector area can be reduced by lithography. This is effective in reducing the base junction capacitance and increasing fl.

However, the problem is that the area of the emitter cannot be reduced.

FIG. 4(b) shows a structure proposed to solve this problem. In other words, if a highly doped p-type (p) region connected to the base is formed around the emitter as shown in the figure, the emitter is made of a material with a large band gap, so p
``Since the n-junction 14 is formed at the periphery of the emitter, electrons do not flow through this junction, but instead flow only to the center, effectively reducing the emitter area.This reduces the emitter-collector junction capacitance. be.

Problems to be Solved by the Invention However, in the above configuration, although current concentration occurs in the center and the actual emitter area becomes smaller, the emitter base capacitance is smaller than p″n at the periphery of the emitter. Since the joint part also contributes, it becomes large, and there is a problem that C□ cannot be made small.

In view of the above-mentioned problems, the present invention aims to provide a structure in which the emitter area can be significantly reduced in an inverted structure HBT, and a method for manufacturing the same.

Means for Solving the Problems In order to solve the above problems, the heterojunction bipolar transistor of the present invention includes a semi-insulating layer of a material that is lattice-matched to the underlayer on a heavily doped n-type underlayer. A highly doped n-type region (a layer changed to an n'' region) extending above and below that part, and an n-type doped layer made of a large bandgap semiconductor material that is lattice matched on top of the n'' region.
A layer in which the region containing the region is left as an emitter and the rest is changed into a highly doped p-type region, a heavily doped p-type base layer that is lattice matched on top of it, and a highly doped p-type base layer that is lattice matched on top of it, and a layer that is doped with a lattice matched n-type layer on top of it. It is characterized by having a small number of collector layers located above the emitter.

In addition, the method for manufacturing a heterojunction bipolar transistor of the present invention includes a semi-insulating layer made of a material lattice-matched to the base on a highly doped n-type base, and a protective layer on top of the semi-insulating layer made of a material that lattice-matches with the base. After epitaxy is performed to convert the insulating layer into a highly doped n-type region (n" region) extending above and below, the protective layer is removed in an epitaxy apparatus so as not to come into contact with air. A n-type doped emitter layer, a p-doped base layer, and a p-doped base layer of a lattice-matched large bandgap semiconductor material are removed and placed on top of the layer.
The doped collector layer is sequentially epitaxially formed in the mold.
The periphery of a columnar part that is a transistor component with a layered structure consisting of an emitter layer, a base layer and a collector layer located so as to include the n'' region, or the columnar part excluding the collector layer in the periphery of the columnar part up to the base layer. It is characterized in that the periphery of the region is replaced with a highly doped p-wall region so as to be in contact with the insulating region.

Effects With the structure of the present invention, in addition to being able to reduce the carrier concentration-dependent capacitance of a heterojunction bipolar transistor, the area of the collector can be reduced by photolithography, and the emitter area can be reduced by reliably introducing an insulating layer under the base layer. Since it is possible to reliably reduce the capacitance component that depends on the junction area, and the emitter-base junction capacitance and the base-collector junction capacitance can be significantly reduced as a whole, it is possible to increase the speed and frequency of the transistor.

By using the manufacturing method of the present invention, a high-quality insulating layer can be reliably introduced, so that the emitter area can be reduced. Since the insulating layer according to the present invention is formed of an undoped material, it does not change during the formation of highly doped p-wall regions by ion implantation, diffusion, etc.

In order to form an n'' region on the insulating layer, it is necessary to interrupt the epitaxy and take it out into the air, and there is a risk that the interface will be damaged.

This can be solved by using a method in which InAs is epitaxially formed and taken out, and then InAs is removed in an epitaxial growth apparatus.

Another advantage of the manufacturing method of the present invention is that the emitter-base and base-collector interfaces, which are most important for the structure of a transistor, are not used as problematic interfaces.

EXAMPLES Hereinafter, heterojunction bipolar transistors and methods of manufacturing the same according to examples of the present invention will be described with reference to the drawings.

FIG. 1 (al, (bl) shows the structure of a heterojunction bipolar transistor showing a conceptual diagram of an embodiment of the present invention.

An insulating region 11 is formed in place of the p''n junction 14 made of a material with a large band gap formed in the emitter layer of the conventional example shown in FIGS. 4(al and 4(b)). Fig. 3 shows an example of the manufacturing method of these structures.First, as shown in Fig. 4(a), a semi-insulating or highly doped n-type G-As substrate is prepared. A highly doped n-type G, As layer 2 is formed on 1. by molecular beam epitaxy, and on top of that a thin film layer 13 of undoped semi-insulating G, A, layers 11 and 1.A is formed by molecular beam epitaxy. Form epitaxy.

Next, as shown in b, a highly doped n-type region (n'' region) is formed in the portion I2 of the insulating layer 11 by photolithography and ion implantation of S. After that, it is put back into the molecular beam epitaxy apparatus and l- After completely removing As in the atmosphere, it is a material with a large bandgap doped to n-type as shown in C./1N!XG□-X A
3, a highly doped p-type base layer 4 of G, A, a collector layer 5 of n-type doped G, As, and a highly doped n-type cap layer 6 of G, As. Sequential epitaxial growth. Next, a structure d is obtained by photolithography and etching, and B and ions are implanted to form a highly doped p-type region 10 as shown in e.

Next, a collector electrode 7, a base electrode 8, and an emitter electrode 9 are formed into a structure f by photolithography and etching.

By adopting the configuration shown in Figure 1.2, the emitter-base junction capacitance and base-collector junction capacitance, which depend on the carrier concentration distribution state, can be reduced due to the carrier concentration distribution peculiar to a heterojunction bipolar transistor, and in addition, the collector area can be reduced. It can be made sufficiently small by photolithography, and the emitter area can also be made sufficiently small because the peripheral part of the emitter region is changed to a highly doped p-wall region and this p-wall region is in contact with the underlying insulating layer. This makes it possible to reduce the emitter-base junction capacitance and base-collector junction capacitance due to the junction area. Therefore, it is possible to increase f7, f, , l.

In the method of the embodiment, the highly doped p-type region can penetrate through the collector forming layer and into the insulating layer region, so it is easy to form. As this method, Bo ion implantation is used in the embodiment, but other ions may be used, and methods such as diffusion can also be applied.

In addition, in the actual example, Aε, G, 1-X A
3-G, A, but lattice-matching material systems such as ■, XG1□As-I, lXA1. −
XAs-I,,P system,I,lXG,,,PG,A,system,G,A.

It goes without saying that the structure and manufacturing method of the present invention can also be applied to heterojunction bipolar transistors using -G, c, p-s, and the like.

Further, in the embodiment, a material having a larger band gap than the base is used only for the emitter, but it goes without saying that a heterojunction bipolar transistor using a material having a larger band gap than the base for the collector may also be used. In addition, as a manufacturing method, an insulating layer and I, IA,
After epitaxy of the layer, highly doped n6B
The method is to form a region, but 1. Although A is not resistant to various treatments, it is also possible to cover the surface with A and take it out of the epitaxy apparatus to form a highly doped n-type region. Also, 1. , A, instead of 1 llX
A Gm1-Xi mixed crystal epitaxy film can also be used. Further, as the epitaxy method, various methods other than MBE can be applied.

Effects of the Invention As described above, in the present invention, out of the emitter and the collector,
In a heterojunction bipolar transistor in which at least the emitter is made of a material with a larger bandgap than the base, and the emitter is placed on the lower side, a semi-insulating semiconductor material that is lattice-matched to the base is placed on a highly doped n-type base. The layer and its surface protection layer are epitaxially formed, and highly doped n-type regions (n”?) extend above and below the insulating layer.
+1 region), the surface protective layer is removed, and on top of the layer, an n-type doped emitter layer, an ivy layer, a p-doped base layer, and an n-type doped base layer of a lattice-matched semiconductor material are formed. Doped collector layers are sequentially epitaxially formed, and the n″
Using a manufacturing method that changes the periphery of a columnar part, which is a transistor component with a layered structure consisting of an emitter layer, a base layer, and a collector layer, to a highly doped p-type, the periphery of the emitter is used as a base. A connected highly doped p-type region (a p'' region, and a highly doped n'' region below the emitter and the p'' region, which contacts only the emitter part)
The structure is a heterojunction bipolar transistor having an insulating region in contact with the emitter region, the emitter region, and the p″ region.This allows the emitter area to be easily reduced together with the collector area, so that the emitter-base junction capacitance and the base- Collector junction capacitance can be significantly reduced,
fT,f, can be increased.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram of the basic structure of the present invention, FIG. 2 is a cross-sectional view of a heterojunction bipolar transistor showing an example using actual materials, and FIG. 3 is an example of an example of the manufacturing method of the present invention. FIG. 4 is a cross-sectional view showing the structure of a conventional reverse structure heterojunction bipolar transistor. 1...Substrate crystal, 2...Highly doped n-type underlayer, 3...N-type doped emitter layer (large band gap), 4...High doped n-type underlayer, 5
...... N-type doped collector layer, 6... Highly doped n-type doped cap layer, 7... Collector electrode, 8... Base electrode, 9... ...Emitter electrode, 10...Ion implantation or diffusion. Highly doped p-type region, 11... Epitaxial formation insulating layer, 12... Highly doped ion-implanted n-type region. Name of agent: Patent attorney Toshio Nakao Haka 1 person 3...
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Claims (3)

[Claims] (1) In a heterojunction bipolar transistor in which at least the emitter and collector of the bipolar transistor are made of a material with a larger bandgap than the base and the emitter is provided on the lower side, the base and lattice are placed on a highly doped n-type base. A semi-insulating layer of a matching semiconductor material in which portions of this semi-insulating layer are replaced with highly doped n-type regions (n^+ regions) extending above and below, and this semi-insulating region. An n-type doped layer of a semiconductor material with a large bandgap that is lattice-matched on a layer consisting of a The layer that changed to the area,
A highly doped p-type base layer of a lattice-matched semiconductor material is placed on the layer consisting of this n^+ region and a highly doped p-type region, and a highly doped p-type base layer of a semiconductor material is placed on top of this p-type base layer in the upper part of the emitter portion. 1. A heterojunction bipolar transistor comprising at least an n-type doped collector layer of a lattice-matched semiconductor material. (2) In a heterojunction bipolar transistor in which at least the emitter and collector of a bipolar transistor are made of a material with a larger bandgap than the base, and the emitter is placed on the lower side, the material is lattice matched to the base on a highly doped base. A semi-insulating layer of a semi-insulating semiconductor material and a surface protective layer of this semi-insulating material are epitaxially formed, and a highly doped n-containing layer is formed by penetrating the top and bottom of the semi-insulating layer.
After changing to the type region (n^+ region), the surface protective layer is removed, and an n-type doped emitter layer and a p-type emitter layer of a lattice-matched, large bandgap semiconductor material are placed on the layer. A base layer doped with n-type and a collector layer doped with n-type are sequentially epitaxially formed, and an emitter layer positioned to include the n^+ region, a columnar part that is a transistor component consisting of a layered structure of a base layer and a collector layer is formed. The peripheral part of the columnar part or the peripheral part of the columnar part excluding the collector layer of the peripheral part of the columnar part up to the base layer is manufactured by replacing the peripheral part of the columnar part with a highly doped p-type region so as to be in contact with the insulating region. A method for manufacturing a heterojunction bipolar transistor. (3) A method for manufacturing a heterojunction bipolar transistor according to claim 2, characterized in that InAs is used as the surface protective layer.