JPS6249655A - Plasma coupling element - Google Patents

Abstract

PURPOSE:To enable the titled plasma coupling element to perform a high speed operation when it is used on an image sensor by a method wherein an ultrathin insulating film is provided under the emitter electrode on which electric charge is injected in then thickness with which a tunnel effect can be generated. CONSTITUTION:A V-groove 13 (131, 132...) is formed on the wafer, on which an n-type layer 12 is epitaxially grown, located on a p<+> type Si substrate 12, and an oxide film 14 is buried in the groove 13. Then, the oxide film located on the right side face of the groove 13 is removed, and an n<+> type layer 15 and p<+> type layer 16 are formed on the exposed side face of the groove 13 by performing an ion implantation. Then, a base electrode 17 and a drain electrode 18 are formed on the left side face of the groove 13, and then an oxide film 19 if formed. After an ultrathin oxide film 21 and a gate oxide film 23 are formed on the exposed right side face of the groove 13 in the thickness with which a tunnel effect can be generated, an emitter electrode 22 and a gate electrode 24 are formed. Subsequently, a collector layer of a plasma coupled element and an n<+> type layer as an output terminal layer are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Prior Art] The present invention relates to improvements in plasma coupled devices using conductance transistors.

Conductance transistors are known as high output, low noise current injection transistors. In recent years, attention has been paid to a technology in which conductance transistors are arrayed and formed on a single semiconductor substrate to form a plasma coupled device (PCD) and utilized in a shift register or the like.

FIGS. 3(a) and 3(b) show the basic structure of a conductance transistor. N+' type layers 32 and 34, which serve as a base and collector layer, are formed on an n-type St substrate 31, and a p-type layer 133, which serves as an emitter layer, is formed between these layers. 35, 36 and 37 are the N poles of the base, emitter and collector respectively, and 38 is the insulation film such as oxide film.
It is. Although FIG. 3(a) shows no pn junction in the collector layer, FIG. 3(b) shows an example in which a p-type layer 39 is provided around the n+-type layer 34 of the collector, creating a so-called hook structure. .

In such a conductance transistor, the base
When charge is injected from the emitter while a constant voltage is applied between the collectors, a current-controlled negative resistance characteristic is observed between the emitter and the collector.

A PCD is a structure in which a plurality of such conductance transistors are arranged in close proximity on a Si substrate, and FIG. 4 is a schematic plan view showing an example of the configuration of such a PCD shift register. The n-type layer 32 serving as the base layer has each element (0) and (1).

(2), . . . are common, and the n+ type layer 34 serving as the collector layer is also commonly connected. When one of these elements, for example (0), is turned on, this element (0
), the emitter voltages of elements (1), (2), etc. near this element (0) decrease according to the injected current from the emitter of element (0). This phenomenon is called plasma coupling. Therefore, by applying, for example, three-phase clocks φri to φ3 as shown in the figure to the emitters of each element, the plasma coupling state can be sequentially transferred, and a shift register operation becomes possible.

[Problems to be Solved by the Invention] The above-mentioned PCD shift register is considered to be applied to a solid-state image sensor, for example, in combination with a photodiode. However, there are still some problems to be solved in such applications. In conventional PCD,
Similar to a normal transistor, a pn junction is used for the emitter section where current is injected. Therefore, a highly concentrated diffusion layer is required under the emitter electrode. The distance between elements that determines the operating characteristics of a PCD is determined by the distance between the diffusion layers under each electrode, but since the lateral extent of the diffusion layer depends on the diffusion depth, the variation in diffusion depth (usually 2 to 4%) ), the distance between each element varies. Such variations cause deterioration in the characteristics of the PCD shift register. Furthermore, since there is a pn junction in the emitter section, the operating speed is limited by the junction capacitance and diffusion capacitance. This causes difficulty in high-speed operation when applied to, for example, an image sensor.

An object of the present invention is to provide a PCD that solves these problems.

[Means and effects for solving the problems] The present invention provides emitter injection current control means for PCD.
Instead of a pn junction, an MIS (metal-insulating film-semiconductor) structure is used that uses an extremely thin insulating film that is thin enough to cause a tunnel effect.

In recent years, advances in insulating film forming technology have made it possible to form extremely thin, high-quality insulating films such as Si oxide films with good controllability. When an MIS structure is constructed using such an ultra-thin insulating film, the tunnel current flowing through the ultra-thin insulating film can be controlled by controlling the applied voltage, and the injection current can be controlled in the same way as in the case of a pn junction. It can be carried out. Therefore, the emitter pn junction of the PCD can be replaced with the MIS structure.

[Example] The present invention will be explained in detail below.

FIGS. 1A to 1C each show a cross-sectional structure of one element of a PCD, that is, a conductance transistor portion, according to an embodiment of the present invention. These (a) to (C) have slightly different structures, but common parts are given the same reference numerals.

The one shown in FIG. 1(a) uses a wafer in which an n-type layer 2 is epitaxially grown on a p+-type Si substrate 1.
A base electrode 5 and a collector electrode 7 are formed on these n-type layers 3 and 4, respectively. The emitter region has an extremely thin oxide film 8 instead of a pn junction.
The emitter electrode 6 is formed through the MIS structure. 9 is a thick oxide film.

In the case of FIG. 1(b), since the collector has a hook structure, an extremely thin oxide m10 is formed similarly to the emitter, and the collector electrode 7 is formed thereon.

In the one shown in FIG. 1(C), the collector has a double hook structure in order to enable more precise control of the current. That is, the first collector electrode 71 is opposed to the substrate via the ultra-thin oxide layer 1110t, and the second collector electrode 72 is also opposed to the first collector electrode 71 via the ultra-WIR layer 1102.

In these structures, the emitter electrode 6 is made of ultrathin oxide lI
Since minority carriers (holes in this example) are injected into the n-type layer 2 in the form of a tunnel current through the conductor 8, it is formed of, for example, a polycrystalline silicon film heavily doped with p-type impurities. Even if a polycrystalline silicon film, a metal or a metalloid is used as the emitter electrode 6, minority carrier injection is possible under appropriate conditions.

The PCDs of these embodiments are the same as the conventional ones, except that current injection from the emitter is controlled by tunnel injection control. According to these embodiments, since a diffusion layer is not required in the emitter region, the distance between each element of the PCD is not affected by variations in the diffusion layer.
It is set to high accuracy determined by the processing accuracy. Therefore, a PCD with excellent characteristics can be obtained. Also, in the emitter region, pn
Since there is no junction, there is no junction capacitance or diffusion capacitance, and high-speed operation is possible.

FIG. 2 shows the main structure of an embodiment in which the present invention is applied to an image sensor. In this embodiment, the p+ type S1 substrate 11 has an n
Using a wafer on which the mold layer 12 was epitaxially grown,
A trench is dug in this and a PCD is built into the side of the trench to achieve high integration.

Furthermore, the switch element section between the PCD section and the photodiode section is also formed in the groove.

To explain this according to the manufacturing process, first, V 13 (131, 132) is formed on the n/D+ wafer 8, and oxidized [114] is embedded in the groove 13 by, for example, photo-CVD. Then, reactive ion etching (RIE) is performed with the center shifted.
The oxide film on the right side of the trench 13 is removed, and the exposed side surface of each V-groove 13 is covered with an n+ type layer 15 that will become the base layer of the POD, and a p+ type layer that will become the drain of the switching MO8FET.
Each mold layer 16 is formed by ion implantation.

After that, the V-groove is filled with an impurity-doped polycrystalline silicon film or a high melting point metal film, and this is etched by off-center RIE to form the base electrode 17 of the PCD and the MOSFE.
A drain electrode 18 of T is formed. And again optical CVD
The groove 13 is filled with oxidation [119] and etched by RIE in the same manner as the previous oxide film etching to expose the side surfaces of the groove. The right side of the exposed groove 13 is now coated with a layer of heat by thermal oxidation or photo-CVD.
After forming the oxide film 21 and the gate oxide film 23, the emitter electrode 22 of the PCD is formed in the same manner as in the previous electrode formation.
Then, a gate electrode 24 of the MOSFET is formed. After that, n+ type layers 24 and 25 are formed on the flat part between the grooves 131 and 132 as the collector layer and output terminal layer of the PCD, and a MOSFET is formed at the upper right end of the V groove 132 from the side surface to the flat part. A p+ type layer 26 is formed which serves as a source region and an anode of a photodiode. Thereafter, the entire surface is covered with CvD oxide 1127, contact holes are made, and interconnections 128 (281 to 28s) made of Al1, for example, are formed to connect the respective terminal electrodes.

Although the figure shows one photodiode and one element of the PCD (i.e. conductance transistor) and one switching MO8FET controlled by the output of this element, a similar configuration can be formed in a repeating array in the direction perpendicular to the figure. Thus, a photodiode array, a PCD shift register for controlling readout of signal charges, and a switching MO8FET array are formed. In addition, a similar configuration is also formed in a reverse array in the direction parallel to the drawing, creating a two-dimensional PC.
A D image sensor is configured.

With such a configuration, signal charges are accumulated through photoelectric conversion using a photodiode, and the signal charges can be read out by sequentially turning on the MO8FETs by operating the PCD shift register.

According to this embodiment, the PCD and switching MO8
Since the FET is buried in the trench, high-density integration is achieved. Also, as explained in the previous embodiment, the PC
Since the emitter section of D has an MIS structure and tunnel injection is controlled, the PCD has excellent characteristics and can operate at high speed. Therefore, it is possible to obtain high-quality images by applying it to, for example, a video camera.

The present invention is not limited to the above embodiments.

For example, in the embodiment shown in FIG. 2, the n+ type layers 24 and 25, which will become the collector layer and output terminal layer of the PCD, are formed on the flat part of the substrate, but these can also be formed on the sidewalls of the trench. This allows for even higher density. Moreover, a U groove can be used instead of a V groove.

[Effects of the Invention] As described above, according to the present invention, the emitter section has an MIS structure instead of a pn junction, thereby making it possible to improve the performance of the PCD.

[Brief explanation of the drawing]

FIGS. 1(a) to (C) are cross-sectional views showing the main structure of a PCD according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a PCD according to an embodiment of the present invention
3(a) and 3(b) are cross-sectional views showing an example of the basic structure of a fundance transistor, which is an element of a PCD,
FIG. 4 is a schematic plan view showing the configuration of the PCD. 1...p+ type S1 substrate, 2...n type layer, 3.4.
... n + type layer, 5 ... base electrode, 6 ... emitter electrode, 7 ... collector electrode, 8 ... ultrathin oxide film, 9
...Oxide film, 11...p+ type 3i substrate, 12...
n-type layer, 13...V groove, 14.19.27-...oxide film, 15 -n+ type layer (base layer), 16...p4
Type layer (drain layer), 17... base electrode, 18...
・Drain electrode, 21... Ultra-thin oxide film, 22... Emitter electrode, 23... Gate oxide film, 24... n+
Type layer (collector layer), 25...n+ type layer (output terminal layer), 26...p+ type layer (source and anode layer), 28
...A2 wiring. Applicant's representative Patent attorney Jun Tsuboi Figure 1 Figure 3 Figure 4

Claims (2)

[Claims] (1) A plasma coupled device configured by forming an array of conductance transistors on a semiconductor substrate, characterized in that an ultra-thin insulating film is provided under the emitter electrode for charge injection to control the injection current. Plasma coupling device. (2) The plasma coupled device according to claim 1, further comprising an extremely thin insulating film under the collector electrode that collects current.