JPS624943Y2 - - Google Patents

Description

[Detailed explanation of the idea]

The present invention relates to a synchronization device for digital data detection. There have traditionally been two problems with high-density data storage on magnetic media. First, a high frequency signal must be generated to lock the detector to the input data. The second is the phenomenon of "pulse crowding" in which transitions that are written close together in a magnetic medium tend to move apart. Very expensive circuits and components were utilized to solve the first problem. New encoding techniques have mainly been used to solve the second problem. Traditionally, sawtooth lock signals and mirror encoding techniques have been used. In this encoding technique, a transition is located in the middle of a "bit cell" when a "1" is encoded, and a "0" is to be encoded and the previous "bit cell" was not a "1". If so, the transition is located at the leading edge of the "bit cell". This is also discussed in detail in US Pat. No. 3,108,261. FIG. 1 shows a typical ^M2 encoded digital signal. For this bit pattern, if a "0" is to be encoded and the previous bit does not contain a transition, the transition is located at the leading edge of the "bit cell." As shown, ^M2 encoding results in the least number of transitions for a given signal while still producing sufficient transitions for the detector lock regardless of data content. Transitions that indicate a 1 tend to have higher "pulse crowding" than transitions that indicate a 0. Conventionally, the detector lock signal is operated with a wider "window" for a "1" transition than a "0" transition. Figure 2 shows an example of a conventional phase-locked signal. It is verified by decoding it and comparing it with the original bit pattern.The first disadvantage of the conventional method is that the detection lock signal needs to be at a very high frequency, which further increases the data rate. Second, conventional methods for guaranteeing data transfer operations do not quantitatively detect pulse crowding, which means that there is a risk that some data will be decoded incorrectly in subsequent operations. According to one embodiment of the present invention, a detector is provided with wind margin detection and dual slope low frequency detection lock signal to detect whether the pulse crowding is within predetermined limits. In addition to the comparison of the encoded bit pattern and the detected bit pattern, data that may result in data errors are detected and such data records are treated as bad, thus ensuring high fidelity storage on the storage medium. 3 is a block diagram of a digital data detection apparatus according to an embodiment of the present invention. In the figure, a transition is detected and appears as a positive pulse on a transition line 10. Line 10 is a detector The data preamble and pre-detector cause the voltage controlled oscillator (VCO) 30 to be coarsely synchronized to the data so that during the positive slope of the detected lock signal 40, A 1” transition occurs, and a “0” transition occurs between the negative slopes. Then

[Table] Error signal −× +× −× +×
As is clear from this, a fast transition always reduces the error signal 60, and a slow transition always decreases the error signal 60.
There is a tendency to increase. Error signal 60 is low pass filtered by filter 70 and applied to VCO 30 to correct the frequency of its output signal. This locks the synchronizer with the input signal. In the input signal, the transition positions of the "bit cells" depend on the data content, and the transitions do not necessarily appear for each "bit cell". Filter 70 and VCO 30 can be easily formed by conventionally known means. However, the detailed circuitry of amplitude absolute value detector 50 and detector 20 is detailed in FIG. In the figure, a detection lock signal 40 is applied to the input of an amplitude magnitude detector 50. An applied voltage greater than the +V ₁ reference voltage turns on transistor T1, drawing current through both transistors T2, T1 and resistor R. Transistors T2 and T3 form a current mirror circuit so that the same current as the value of the current flowing through transistor T2 flows through transistor T3.
flows through. Therefore, the amplitude absolute value detector 50
The output current of is proportional to the voltage value of the input signal.
Further, if the input voltage is lower than the reference voltage + _V1 , the transistor T4 is turned on and the current is shunted through the resistor R. Further, an output current proportional to the voltage value of the input signal is generated at the output end of the amplitude absolute value detector 50. In either case, the output current of the detector 50 has the same polarity. The input current to detector 20 is supplied to transistor T5. Transistors T5 and T6 form a current mirror circuit such that a current equal to the current supplied to said transistor T5 also flows through said transistor T6. Transistor T7 is transition line 1
When deactivated by an inverted version of the pulse on 0, the current shunted through transistor T6 is supplied to the logic stage of detector 20 and the detector is energized. Transistors T8 and T9 are
A differential amplifier, which is the first logic stage of the detector 20, is formed. The reference signal 2 applied to the reference input 2 of the transistor T9 is selected such that the slope input signal applied to the input 2 can take either a value greater or smaller than the value of said reference signal 2. When the slope signal is greater than the reference signal 2, transistor T8 is activated and transistor T6 is activated.
The current flowing through is diverted to transistor T8.
Further, when the slope input signal is smaller than the reference signal 2, the transistor T9 is activated;
The current flowing through transistor T6 is
Transferred to 9. Both transistors T10, T11
And both transistors T12, T13 also form a second differential amplifier, which is the second logic stage of the detector 20. The current paths for different logical combinations of signals relative to the respective reference signals at both inputs 1, 2 are shown in FIG. In Figure 5, I ₁ ⁺ ,
I ₁ ^- , I ₂ ⁺ , I ₂ ^- are determined by the positive (I ₁ ⁺ , I ₂ ⁺ ) or negative (I ₁ ^- , I ₂ ^- ) signs of the relative signals at input terminals 1 and 2. Gives a logical value indicating the path. Further, FIG. 6 shows the relationship between the respective signals in FIG. 5. The absolute value input to the detector 20 is a positive triangular wave, which becomes zero when the detected lock signal is at relative zero (the level of reference signal 1). As the distance increases, the absolute value of the output signal increases. Both transistors T10,
The current through the current path of T12 produces an output signal at the output end. Further, the current in the current path of transistor T11 or T13 is
It flows through transistor T15, which together with 4 forms a current mirror circuit. This provides a current of opposite polarity to the output of the detector 20. The result is an output current that includes a series of pulses in response to the pulses in transition line 10, as implemented by the algorithm shown in Truth Table 1 above. The window margin detector is best explained by reference to the signal waveform diagram of FIG.
In the figure, a is the M ² encoded signal, b is the actual signal encoded according to "pulse crowding", and c is the "window" signal. The detected transition is stretched by a pulse stretcher and the fourth
A signal as shown in Figure d is obtained. This signal is
It is compared with the slope output signal of VCO 30. This transition period of the gradient output signal is a window in which the data transition must be correctly decoded. The stretched pulse duration then provides the minimum allowable margin in the window margin test.
The window margin test is performed by detecting transitions in the slope signal that occur during the duration of a stretched pulse. Transitions detected in this manner may cause errors during subsequent data retrieval operations since they are close to the boundaries of the window. Therefore, the detected pulse signals that the corresponding data interval is incomplete and does not support data storage. As described in detail above, by implementing the present invention, the oscillation frequency of the oscillator for data demodulation detection becomes about half that of the conventional technology, detects and notifies period deviations in data detection, and records defective data. This method is useful in practical use because it can prevent this.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram of the ^M2 encoded digital signal, and FIG. 2 is a waveform diagram of the phase lock signal. FIG. 3 is a block diagram showing an embodiment of the present invention, FIG. 5 is a detailed circuit diagram of a part thereof, and FIG. 6 is a waveform diagram of each part thereof. 20: Detector, 20: Voltage controlled oscillator,
50: amplitude absolute value detector; 70: filter.
FIG. 4 is a waveform diagram for explaining the window/margin detector.

Claims (1)

[Claims for Utility Model Registration] A synchronizing device for digital data detection consisting of the following (a) to (d): (a) A variable oscillator having an input terminal and first and second output terminals: supplied to the input terminal. A periodic triangular wave signal having a frequency corresponding to the output signal is applied to the first output terminal, and a signal having a first or second value corresponding to a positive or negative slope of the output signal of the first output terminal, respectively. is the second
are generated at the output terminals, respectively. (b) An amplitude detector comprising an input terminal and an output terminal: the input terminal is connected to the first output terminal of the variable oscillator, and the amplitude absolute value of the difference between the signal value at the input terminal and the reference value is detected. An output signal corresponding to the output voltage is generated at the output terminal. (c) first and second input terminals connected to the first and second output terminals of the variable oscillator, respectively, within the range of change of the input signal to each of the first and second input terminals; a third input terminal connected to the output terminal of the amplitude detector, a fourth input terminal into which a transition input pulse signal of the data signal is introduced, and a transition input of the data signal; A detector having an output terminal that outputs an output signal having the same absolute value as the input signal to the third input terminal only during the pulse period of the pulse signal: The polarity of the output signal is set to the first and second input terminals. When the polarities of the input signals measured from the respective reference signals are the same polarity, the polarity is the same as the input signal to the third input terminal, and when the polarity is opposite, the polarity is opposite to the input signal to the third input terminal. Becomes polar. (d) A filter having an input terminal connected to the detector and an output terminal connected to the input terminal of the variable oscillator, and generating a corresponding output signal after low-pass filtering the signal.