JPS6248853B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention samples audio input at regular time intervals, writes the audio input data to a memory, and when the amount of data reaches a set value, a processing unit (CPU) Relating to a speech recognition preprocessing unit that reads voice input data within a predetermined time, if the voice input data is not read within a predetermined time, it notifies the processing device to that effect and prohibits writing to the memory, The present invention relates to a voice input data control method that maintains a memory in a readable state.

[Prior art and problems]

Audio input is sampled at fixed time intervals through an audio input device such as a microphone, the sampled audio input data is written to memory, and when the amount of audio input data reaches a predetermined amount, the processing unit (CPU) outputs the audio within a predetermined time. In the speech recognition preprocessing section, which now reads input data,
Conventionally, when the sampling period is set to 10ms, for example, sampled audio input data is written to memory every 10ms, making it impossible for a processing device to read data from memory for more than 10ms. Ta. Therefore, such a conventional method has a problem in that only a processing device that can process within 10 ms can be used. Such restrictions also pose a problem when testing a filter board that performs speech analysis in a speech recognition preprocessing section, for example. That is, it is difficult to test the filter board within a 10 ms cycle using conventional test systems and methods.

[Purpose of the invention]

The present invention is based on the above considerations, and includes:
It is an object of the present invention to provide a voice input data control method that allows a voice recognition preprocessing section to read voice input data from a memory beyond the sampling period.

[Structure of the invention]

To this end, the audio input data control method of the present invention includes an audio input amplification means for inputting and amplifying audio, an audio analysis means for analyzing audio into audio input data of multiple channels, and an audio input data control method for converting audio input data of multiple channels into one.
A data selection/conversion means for selecting each channel and converting it into digital audio input data, a data storage means for storing a plurality of channels of audio input data converted by the data selection/conversion means, and an audio input data control means. , a voice recognition pre-processing unit that samples voice input at regular time intervals, stores the voice input data in the data storage means, and reads out the stored voice input data to a processing device that performs voice recognition processing; In the audio input data control method, the audio input data control means stores audio input data of a plurality of channels in the data storage means at each predetermined time interval,
Thereafter, a sampling control section that sets the data storage means in a read mode and supplies the read address from the processing device to the data storage means; an address detection section that detects the final address of the read address; The apparatus further includes a readout detection section that detects whether or not the readout mode is set, and the address detection section controls the sampling control section from the readout mode to the data storage means at the next fixed time interval on the condition that the address detection section detects the final address. on the condition that the readout detection unit detects the readout mode, the processing device controls the audio input data stored in the data storage means even after a certain period of time has elapsed. The present invention is characterized in that it is configured to notify that input data has not been read.

[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing one embodiment of the present invention, and FIG. 2 is a time diagram showing the timing of the signal when the processing device reads audio input data from the memory within a specified time.
FIG. 3 is a time chart showing the timing of signals when the processing device reads audio input data from the memory over a specified time. In Figure 1, 1 is a microphone, 2 is a preamplifier, 3 is a pre-emphasis, 4 is a BPF (band pass filter), 5 and 12 are multiplexers, 6 is a sample and hold circuit, 7 is an A/D converter, and 8 is buffer memory, 9 to 11
is a counter, 13 is a decoder, 14 and 15 are FF
(flip-flop circuit), 16 is a logic circuit, 1
7 is Nando Gate, 18 is Noah Gate, 19
is Noah Gate, 20 is And Gate, 21,
23 is an inverter, and 22 is a processing unit (CPU).

In Figure 1, audio input is through microphone 1, preamplifier 2, and preemphasis 3.
Sent to BPF4. Pre-emphasis 3 is designed to output the high-frequency range as the same as the low-frequency range, since the receiving sensitivity of the microphone 1 is low in the high range, and therefore the attenuation is particularly correct for voice input such as fricative sounds. It is intended to be compensated so that it can be obtained.
When the audio input signal is sent to BPF4, BPF4
Then, the 16 channels of audio input data are filter rectified and smoothed for each of the 16 channels of frequency bands, and sent to the multiplexer 5. In multiplexer 5,
An address is specified, and one channel of audio input data is selected from among the 16 channels of audio input data sent from the BPF 4 according to the specified address. The audio input data selected by the multiplexer 5 is sent to the sample/hold circuit 6.
and held at 12 by the A/D converter.
The data is converted into bit digital data and stored in the buffer memory 8. When all the audio input data of the 16 channels are similarly stored in the buffer memory 8, the audio input data is read out to the processing unit (CPU) 22. In the processing device 22,
Although not shown, it is provided with a storage device in which a dictionary corresponding to voice input data is stored, and when the voice input data is read from the buffer memory 8, voice recognition processing is performed with reference to the dictionary. The configuration up to the time when voice input data is read from the buffer memory 8 to the processing device 22 corresponds to the voice recognition processing section. In such a speech recognition preprocessing section, the address given to the multiplexer 5 is:
It is generated by the counter 11. counter 11
is to count the output 〓50μSW of the logic circuit 16, and the count value is sent to the multiplexer 5.
is supplied as an address to the multiplexer 12 as well as to the multiplexer 12. Addresses are provided from multiplexer 12 to buffer memory 8 . Further, the counter 11 sends a carry to the J terminal of the FF 14 when the time reaches 50 .mu.S.times.16, that is, when the audio input data of 16 channels is written into the buffer memory 8. The logic circuit 16 is a logic circuit having a NAND gate which receives the data ready negative logic signal DTRDY, the clock CLK, and the output of the counter 9, and the data ready negative logic signal DTRDY is logic "1". ”, the signal is activated by the output of the NOR gate 19 and becomes logic “0” when a carry is sent from the counter 9 every 50 μS〓50
Output μSW. This signal 50μSW is also supplied to the buffer memory 8 and the NAND gate 17, and in the buffer memory, the signal 50μSW is written at logic "0" and read at logic "1". In the logic circuit 16, the signal 〓50μSW
becomes logic "0" 16 times, the audio input data of 16 channels is written to buffer memory 8, and the negative logic signal of data ready = DTRDY becomes logic "0".
Then, from now on, the data ready negative logic signal 〓
When DTRDY becomes a logic "1" again, the signal 50μSW remains at a logic "1" until triggered by the output of NOR gate 19.
In addition, after the signal 〓50μSW of the logic circuit 16 becomes logic "0" 16 times and the audio input data is written to the buffer memory 8, the data ready DTRDY becomes logic "1" and the channel 15 (〓 If CH15) is not read, the buffer memory 8 is held in the read state. Counter 9 is clock CLK
It counts and sends out a carry every 50 μS, and in addition to being supplied to the logic circuit 16, the carry goes through the counter 10 and the inverter 23.
It is also supplied to Noah Gate 18. counter 10
counts the carries sent from the counter 9 and sends out a carry every 10ms. The carriers are Noah Gate 19 and And Gate 2.
0. In addition, the NOR gate 19 receives the reset signal RST from the processing device at its input terminal, and when the reset signal RST becomes logic "1" or when a carry of logic "1" is output from the counter 10. Logic "0", when both are logic "0", output signal of logic "1" is counter 1
It is supplied to the reset terminals 0 and 11, the input terminal of the inverter 23, and the start terminal of the logic circuit 16. The output terminal of inverter 23 is supplied to the input terminal of NOR gate 18. The output of NOR gate 18 is applied to the reset terminal of counter 9. The address signal from the processing device 22 is sent to the multiplexer 1
2 and the input terminal of the decoder 13. The multiplexer 12 is supplied with the data ready signal DTRDY as a selection signal, and the data ready signal DTRDY is supplied as a selection signal.
When the ready signal DTRDY is logic “0”, the buffer is set using the count value of the counter 11 as the address.
Supplied to memory 8, data ready signal DTRDY
When becomes logic "1", the address sent from the processing device 22 is supplied to the buffer memory 8.
The decoder 13 decodes the address sent from the processing device 22, and the address is assigned to the channel 15.
If so, the signal is logic “0”, otherwise it is logic “1” = CH15 is connected to NAND gate 17
Send to. The input terminal of the NAND gate 17 is supplied with the output 〓50μSW of the logic circuit 16, and the output of the NAND gate 17 is supplied to the C terminal of the FF 14 as a clock. The Q terminal of the FF 14 is connected to the K terminal, and its output is supplied as the data ready signal DTRDY to the input terminal of the AND gate 20, the select terminal of the multiplexer 12, and the processing device, and the output of the Q terminal is connected to the data ready signal DTRDY. The negative logic signal 〓DTRDY is supplied to the input terminal of the logic circuit 16. In FF15, the output of AND gate 20 is supplied to the J terminal, the clock CLK is supplied to the C terminal, the K terminal is grounded, and the Q
The output of the terminal is sent to the processing device 22 as a notification signal OVRN.
is supplied to The output of the inverter 21 is supplied to the reset terminals of FFs 14 and 15, and the reset signal of the processing device is supplied to the input terminal of the inverter 21.
RST is provided.

Next, a case in which the processing device reads audio input data from the memory within a specified time will be described with reference to FIG. When the reset signal RST of the processing device 22 changes from logic "1" to logic "0", the counter 9
1 to 11 and FFs 14 and 15 are reset, and the logic circuit 16 starts operating. As a result, the logic circuit 16 generates write pulses 50 μS at 50 μS intervals based on the carry and clock CLK sent from the counter 9 every 50 μS and the data ready negative logic signal DTRDY.
The write pulse 50μSW is sent to the buffer memory 8 as a write timing signal and also to the counter 11. The counter 11 counts write pulses = 50μSW, and the count value is used as an address for multi
multiplexer 5 and also multiplexer 12
It is also applied to the buffer memory 8 through the buffer memory 8. 50
When the audio input data (sample data A) of 16 channels of BPF 4 are sequentially converted into digital values through the multiplexer 5, sample hold circuit 6, and A/D converter 7 every μS and stored in the buffer memory 8, A carry is sent out from the counter 11. As a result, FF14's J
Since logic "1" is added to the terminal, data ready signal DTRDY becomes logic "1", and its negative logic signal = DTRDY becomes logic "0", and logic circuit 1
6 is stopped, the buffer memory 8 is placed in read mode, and the address sent from the multiplexer 12 to the buffer memory 8 is set to the processing unit 2.
The address can be switched to 2. Processing device 22
When it reads that the data ready signal DTRDY has become logic "1", it sequentially sends out the addresses and sequentially reads out the audio input data stored in the buffer memory 8. When the address of the processing device 22 specifies channel 15, the output of the decoder 13 becomes logic "0" and the output of the FF 14 is inverted.
As a result, the data ready signal DTRDY becomes logic "0" and its negative logic signal DTRDY becomes logic "1". In that state, the counter 10
continues counting, and when a 10 ms carry is sent out, the counters 9 to 11 are reset and the logic circuit 16 starts operating, and the next audio input data B is written to the buffer memory 8.

However, if the audio input data is read out over the specified time, the data ready signal DTRDY is still at logic "1" when a 10 ms carry is sent from the counter 10, as shown in FIG. Therefore, the AND condition of AND gate 20 is satisfied, and the output of Q terminal of FF15 is
OVRN is set to logic "1". That is, if the processing device 22 does not complete reading the audio input data from the buffer memory 8 within the specified time even though the data ready signal DTRDY has become a logic "1", the signal OVRN becomes a logic "1". 1'' and this is notified to the processing device 22. Also, in this case, since the data ready signal DTRDY remains at logic "1", the buffer memory 8 is connected to the logic circuit 16.
It is controlled to remain in the read mode by the output of , and is controlled to be given an address from the processing unit 22 by the multiplexer 12 .

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the read address is detected and the writing is prohibited until the read is completed, so even if the sampling period is exceeded, the audio is not stored in the memory of the speech recognition preprocessing section. It becomes possible to read input data. Therefore, the voice analysis filter board can also be tested over the sampling period, making it possible to test it using conventional test systems and methods.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIG. 2 is a time diagram showing the timing of the signal when the processing device reads audio input data from the memory within a specified time.
FIG. 3 is a time chart showing the timing of signals when the processing device reads audio input data from the memory over a specified time. In Figure 1, 1... Microphone, 2... Preamplifier, 3... Pre-emphasis, 4... BPF
(Band pass filter), 5 and 12...Multiplexer, 6...Sample and hold circuit, 7...
...A/D converter, 8...Buffer memory,
9 to 11...Counter, 13...Decoder,
14 and 15...FF (flip-flop circuit),
16...Logic circuit, 17...NAND gate, 1
8...Noah Gate, 19...Noah Gate, 2
0...and gate, 21...inverter, 2
2... Processing unit (CPU), 23... Inverter.

Claims (1)

[Claims] 1 voice input amplification means for inputting and amplifying voice, voice analysis means for analyzing voice into voice input data of multiple channels, and voice input data of multiple channels for 1
A data selection/conversion means for selecting each channel and converting it into digital audio input data, a data storage means for storing a plurality of channels of audio input data converted by the data selection/conversion means, and an audio input data control means. , a voice recognition pre-processing unit that samples voice input at regular time intervals, stores the voice input data in the data storage means, and reads out the stored voice input data to a processing device that performs voice recognition processing; In the audio input data control method, the audio input data control means stores audio input data of a plurality of channels in the data storage means at each predetermined time interval,
Thereafter, a sampling control section that sets the data storage means in a read mode and supplies the read address from the processing device to the data storage means; an address detection section that detects the final address of the read address; The apparatus further includes a readout detection section that detects whether or not the readout mode is set, and the address detection section controls the sampling control section from the readout mode to the data storage means at the next fixed time interval on the condition that the address detection section detects the final address. on the condition that the readout detection unit detects the readout mode, the processing device controls the audio input data stored in the data storage means even after a certain period of time has elapsed. 1. A voice input data control method, characterized in that it is configured to notify that input data has not been read.