JPS624859B2 - - Google Patents
Info
- Publication number
- JPS624859B2 JPS624859B2 JP17078281A JP17078281A JPS624859B2 JP S624859 B2 JPS624859 B2 JP S624859B2 JP 17078281 A JP17078281 A JP 17078281A JP 17078281 A JP17078281 A JP 17078281A JP S624859 B2 JPS624859 B2 JP S624859B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- heat sink
- recess
- heat
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 18
- 239000000919 ceramic Substances 0.000 claims description 8
- 230000005855 radiation Effects 0.000 claims description 3
- 230000017525 heat dissipation Effects 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Description
【発明の詳細な説明】
本発明は、マルチチツプLSIパツケージの構造
に関するもので、特にICチツプの発生する熱を
効率よく放散させることのできるLSIパツケージ
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a multi-chip LSI package, and particularly to an LSI package that can efficiently dissipate heat generated by IC chips.
第１図は、従来のマルチチツプLSIパツケージ
の一部断面を示した図である。図において、１は
多層セラミツク基板、２はICチツプ、３は外部
入出力端子、４は放熱器、５は放熱用ピストン、
６はピストン押えバネ、７はICチツプの端子バ
ンブである。図に示すように、ICチツプの放熱
を行なう際に、ICチツプ２が端子バンプ７によ
り基板１上に周知のフエースダウンボンデイング
されている場合には、ICチツプの裏面に放熱器
４内にうめこまれた放熱用ピストン５を接触さ
せ、さらにICチツプを破壊するおそれのある余
分な力が加わることなく、かつICチツプ２の裏
面にピストン５を確実に接触させるためにバネ６
を設けるといつたように、この種のLSIパツケー
ジでは構造的に極めて複雑になる欠点があつた。 FIG. 1 is a partial cross-sectional view of a conventional multi-chip LSI package. In the figure, 1 is a multilayer ceramic substrate, 2 is an IC chip, 3 is an external input/output terminal, 4 is a heat sink, 5 is a heat dissipation piston,
6 is a piston holding spring, and 7 is a terminal bump for the IC chip. As shown in the figure, when performing heat dissipation from an IC chip, if the IC chip 2 is bonded face-down to the substrate 1 using terminal bumps 7, a heat sink 4 is inserted into the back side of the IC chip. A spring 6 is used to ensure that the piston 5 contacts the back surface of the IC chip 2 without applying any extra force that may damage the IC chip.
As mentioned above, this type of LSI package had the disadvantage of becoming extremely complex in structure.
第２図は、他の従来のマルチチツプLSIパツケ
ージの一部断面を示した図である。図において、
１は多層セラミツク基板、２はICチツプ、３は
外部入出力端子、８はICチツプの端子リードで
ある。図に示すようなICチツプを周知のフエー
スアツプボンデイングで基板１に取付ける方法で
は、基板１のICチツプと反対の面から放熱する
必要があるが、通常反対面には外部接続用端子３
が設けられているため、放熱器が取付け不可能で
あり、放熱効果が良くないという欠点があつた。 FIG. 2 is a partial cross-sectional view of another conventional multi-chip LSI package. In the figure,
1 is a multilayer ceramic substrate, 2 is an IC chip, 3 is an external input/output terminal, and 8 is a terminal lead of the IC chip. In the method of attaching an IC chip to a board 1 using well-known face-up bonding as shown in the figure, it is necessary to dissipate heat from the side of the board 1 opposite to the IC chip.
Because of the provision of a radiator, it was impossible to attach a radiator, and the heat radiating effect was poor.
本発明の目的は、放熱特性の良好なLSIパツケ
ージを提供することにある。 An object of the present invention is to provide an LSI package with good heat dissipation characteristics.
本発明によるマルチチツプLSIパツケージは、
表面にICチツプの収納搭載の可能な凹みを複数
個持ち内部に多層配線を有する積層型多層セラミ
ツク基板と、この基板の凹みを覆いかつ該基板の
表面の凹んでいない部分に接着された放熱器と、
前記凹みの底部に接着されかつ周囲に前記放熱器
に接触する複数個の放熱用リードを有する放熱板
と、前記凹みの内部で前記放熱板上に個々に実装
された複数個のICチツプと、前記基板の前記凹
みとは反対側の他の表面に設けられた入出力端子
とを有することを特徴とする。 The multi-chip LSI package according to the present invention is
A laminated multilayer ceramic substrate that has multiple recesses on its surface that can accommodate IC chips and has multilayer wiring inside, and a heatsink that covers the recesses of this board and is bonded to the part of the surface of the board that is not recessed. and,
a heat sink having a plurality of heat radiation leads bonded to the bottom of the recess and in contact with the heat sink around the periphery; a plurality of IC chips individually mounted on the heat sink inside the recess; An input/output terminal is provided on another surface of the substrate opposite to the recess.
以下、本発明について図面を参照して詳細に説
明する。 Hereinafter, the present invention will be explained in detail with reference to the drawings.
第３図は、本発明の一実施例を示したマルチチ
ツプLSIパツケージの一部断面図である。図にお
いて、２はICチツプ、３は外部入出力端子、４
は放熱器、８は端子リード、９は第１の凹部、１
０は第２の凹部、１１はICチツプをボンデイン
グするためのダイパツド、１２は端子リードをボ
ンデイングするためのリードボンデイングパツ
ド、１３は積層型多層セラミツク基板、１４は放
熱板、１５は内部配線である。積層型多層セラミ
ツク基板１３は、周知のアルミナグリーンシート
積層法によつて作られたものである。すなわち、
第１の凹部９および第２の凹部１０は、穴の寸法
の異なるアルミナグリーンシート１３−１および
１３−２を基盤となるアルミナグリーンシート１
３−３の上に積層した後焼成して形成したもので
あり、さらに、内部には、多層内部配線１５が施
されている。 FIG. 3 is a partial sectional view of a multi-chip LSI package showing an embodiment of the present invention. In the figure, 2 is an IC chip, 3 is an external input/output terminal, and 4 is an external input/output terminal.
is a heat sink, 8 is a terminal lead, 9 is a first recess, 1
0 is a second recess, 11 is a die pad for bonding an IC chip, 12 is a lead bonding pad for bonding a terminal lead, 13 is a laminated multilayer ceramic substrate, 14 is a heat sink, and 15 is an internal wiring. be. The laminated multilayer ceramic substrate 13 is made by a well-known alumina green sheet lamination method. That is,
The first recess 9 and the second recess 10 are formed by alumina green sheets 1 that are made of alumina green sheets 13-1 and 13-2 having different hole sizes.
It is formed by laminating it on top of 3-3 and then firing it, and furthermore, multilayer internal wiring 15 is provided inside.
第３図に示すように、第１の凹部９の穴の寸法
はICチツプ２を埋めこむに十分な寸法にとら
れ、第２の凹部１０の穴の寸法は、ICチツプ２
の端子リード８をボンデイングパツド１２上でボ
ンデイングできるに十分な寸法にとられ、かつ第
１の凹部と第２の凹部の基板１３の表面からの合
計の深さは、端子リード８をボンデイングしたあ
とでもリード８が基板１３の表面から十分下にな
るような寸法に決められている。 As shown in FIG. 3, the dimensions of the hole in the first recess 9 are sufficient to embed the IC chip 2, and the dimensions of the hole in the second recess 10 are sufficient to embed the IC chip 2.
The dimensions are sufficient to bond the terminal lead 8 on the bonding pad 12, and the total depth of the first recess and the second recess from the surface of the substrate 13 is such that the terminal lead 8 can be bonded on the bonding pad 12. The dimensions are determined so that the leads 8 will be sufficiently below the surface of the substrate 13 even afterward.
また基板１３においてシート１３−２および１
３−３には複数個のICチツプの端子につながる
各々のボンデイングパツド１２間の接続配線およ
び複数個の入出力端子の各々との接続配線が収容
されており、第３図においては、この接続配線は
内部配線１５で代表的に示されている。 Also, in the substrate 13, sheets 13-2 and 1
3-3 accommodates connection wiring between each bonding pad 12 connected to the terminals of a plurality of IC chips and connection wiring with each of a plurality of input/output terminals. The connection wiring is typically shown as internal wiring 15.
さらに、シート１３−３上にはダイパツド１
１、シート１３−２上にはリードボンデイングパ
ツド１２が形成されている。 Furthermore, a die pad 1 is placed on the sheet 13-3.
1. A lead bonding pad 12 is formed on the sheet 13-2.
第４図は第３図の放熱板１４の取付け構造の詳
細を示した図である。図において、１４−１は放
熱板の平板部、１４−２は放熱用リードである。
図に示すように、放熱板１４は、ダイパツド１１
の上部に接着して設けられ、さらに放熱用リード
１４−２は第３図の放熱器４に接触するように取
付けられる。そして、ICチツプ２は放熱板の平
板部１４−１の上記に接着して設けられている。 FIG. 4 is a diagram showing details of the mounting structure of the heat sink 14 shown in FIG. 3. In the figure, 14-1 is a flat plate part of a heat sink, and 14-2 is a heat radiation lead.
As shown in the figure, the heat sink 14 is attached to the die pad 11.
The heat radiating lead 14-2 is attached so as to be in contact with the heat radiator 4 shown in FIG. 3. The IC chip 2 is attached to the upper part of the flat plate part 14-1 of the heat sink.
上記の構造により、ICチツプ２が発生した熱
は放熱板１４の放熱用リード１４−２を介して放
熱器に放散することが可能となり、特に放熱板に
例えば銅のような熱伝導率の良好な材料を使用す
れば、その効果はますます顕著なものとなる。さ
らに、基板１３はアルミナを主成分とするセラミ
ツク基板であるから、ICチツプ２→放熱板１４
→ダイパツド１１→基板１３と伝導した熱も、熱
伝導率の大きい基板１３内部を通つて表面に接着
された放熱器４に効率的に放熱することが可能で
あり、前記放熱板１４の効果と相まつて極めて熱
放散性の良好なマルチチツプLSIパツケージを構
成することが可能となる。 With the above structure, the heat generated by the IC chip 2 can be dissipated to the heat sink via the heat dissipation leads 14-2 of the heat sink 14. In particular, the heat sink is made of a material with good thermal conductivity such as copper. The effect will be even more pronounced if you use materials that are Furthermore, since the substrate 13 is a ceramic substrate mainly composed of alumina, the IC chip 2 → the heat sink 14
The heat conducted from the die pad 11 to the substrate 13 can also be efficiently radiated to the heat sink 4 bonded to the surface through the inside of the substrate 13, which has a high thermal conductivity. Together, it becomes possible to construct a multi-chip LSI package with extremely good heat dissipation properties.
本発明は、以上説明したように、基板内にIC
チツプと放熱板とを埋め込んで実装できる構造を
とることにより、基板のICチツプ実装面からの
効果的な放熱が可能となり、放熱散性の極めて良
好なマルチチツプLSIパツケージを実現できると
いう効果がある。 As explained above, the present invention has an IC in the substrate.
By adopting a structure in which the chip and the heat sink can be embedded and mounted, it is possible to effectively dissipate heat from the IC chip mounting surface of the board, and it is possible to realize a multi-chip LSI package with extremely good heat dissipation performance.
第１図は従来例の構造を示した一部断面図、第
２図は他の従来例の構造を示した一部断面図、第
３図は本発明の一実施例の構造を示した一部断面
図、第４図は第３図の放熱板の取付け構造の詳細
を示した斜視図である。
符号の説明：２はICチツプ、３は外部入出力
端子、４は放熱器、８は端子リード、１１はダイ
パツト、１２はリードボンデイングパツド、１３
は積層型多層セラミツク基板、１４は放熱板、１
５は内部配線をそれぞれあらわしている。
Fig. 1 is a partial sectional view showing the structure of a conventional example, Fig. 2 is a partial sectional view showing the structure of another conventional example, and Fig. 3 is a partial sectional view showing the structure of an embodiment of the present invention. A partial sectional view and FIG. 4 are perspective views showing details of the mounting structure of the heat sink of FIG. 3. Explanation of symbols: 2 is an IC chip, 3 is an external input/output terminal, 4 is a heat sink, 8 is a terminal lead, 11 is a die pad, 12 is a lead bonding pad, 13
is a laminated multilayer ceramic substrate, 14 is a heat sink, 1
5 represents internal wiring, respectively.
Claims (1)
複数個持ち内部に多層配線を有する積層型多層セ
ラミツク基板と、この基板の凹みを覆いかつ該基
板の表面の凹んでない部分に接着された放熱器
と、前記凹みの底部に接着されかつ周囲に前記放
熱器に接触する複数個の放熱用リードを有する放
熱板と、前記凹みの内部で前記放熱板上に個々に
実装された複数個のICチツプと、前記基板の前
記凹みとは反対側の他の表面に設けられた入出力
端子とを有するマルチチツプLSIパツケージ。1. A laminated multilayer ceramic substrate that has multiple recesses on its surface for storing and mounting IC chips and has multilayer wiring inside, and a heatsink that covers the recesses of this board and is bonded to the part of the surface of the board that is not recessed. a heat sink having a plurality of heat radiation leads bonded to the bottom of the recess and in contact with the heat sink around the periphery; and a plurality of IC chips individually mounted on the heat sink inside the recess. and an input/output terminal provided on another surface of the substrate opposite to the recess.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17078281A JPS5873141A (en) | 1981-10-27 | 1981-10-27 | Multichip lsi package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17078281A JPS5873141A (en) | 1981-10-27 | 1981-10-27 | Multichip lsi package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5873141A JPS5873141A (en) | 1983-05-02 |
| JPS624859B2 true JPS624859B2 (en) | 1987-02-02 |
Family
ID=15911267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17078281A Granted JPS5873141A (en) | 1981-10-27 | 1981-10-27 | Multichip lsi package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5873141A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62116440U (en) * | 1986-01-14 | 1987-07-24 |
-
1981
- 1981-10-27 JP JP17078281A patent/JPS5873141A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5873141A (en) | 1983-05-02 |
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