JPS6248377B2 - - Google Patents
Info
- Publication number
- JPS6248377B2 JPS6248377B2 JP5391883A JP5391883A JPS6248377B2 JP S6248377 B2 JPS6248377 B2 JP S6248377B2 JP 5391883 A JP5391883 A JP 5391883A JP 5391883 A JP5391883 A JP 5391883A JP S6248377 B2 JPS6248377 B2 JP S6248377B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- light
- eff
- lifetime
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 44
- 238000000034 method Methods 0.000 claims description 14
- 238000005215 recombination Methods 0.000 claims description 13
- 230000006798 recombination Effects 0.000 claims description 13
- 239000000969 carrier Substances 0.000 claims description 12
- 230000001678 irradiating effect Effects 0.000 claims description 5
- 235000012431 wafers Nutrition 0.000 description 37
- 238000005259 measurement Methods 0.000 description 9
- 239000013078 crystal Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000000691 measurement method Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000008151 electrolyte solution Substances 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Description
【発明の詳細な説明】
本発明は半導体ウエーハのライフタイムを測定
する方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for measuring the lifetime of semiconductor wafers.
周知の如く、半導体に光等の電磁波やα線等の
粒子流を照射して外部エネルギーを注入すると電
子と正孔の対が発生し、例えば半導体がＮ型であ
る場合には正孔が過剰少数キヤリヤとなり、そし
てこの過剰少数キヤリヤが電子と再結合して次々
と消滅してゆき、過剰少数キヤリヤの濃度は指数
関数的に減少する。過剰少数キヤリヤの濃度が
１／ｅに減少するまでの時間を半導体のライフタ
イムという。このライフタイムは半導体結晶中の
不純物原子、転位、格子欠陥等に著しく影響を受
けるので、ライフタイムの値を測定することは半
導体結晶の品質評価の手法のひとつとして重要視
されている。 As is well known, when external energy is injected into a semiconductor by irradiating electromagnetic waves such as light or particle streams such as alpha rays, pairs of electrons and holes are generated.For example, if the semiconductor is N-type, there will be an excess of holes. The excess minority carriers become minority carriers, and these excess minority carriers recombine with electrons and disappear one after another, and the concentration of excess minority carriers decreases exponentially. The time required for the concentration of excess minority carriers to decrease to 1/e is called the lifetime of a semiconductor. Since this lifetime is significantly affected by impurity atoms, dislocations, lattice defects, etc. in the semiconductor crystal, measuring the lifetime value is considered important as one of the methods for evaluating the quality of semiconductor crystals.
一般に半導体ウエーハのライフタイムを測定す
る場合、実測される実効ライフタイムτeffは半
導体結晶の純度や結晶欠陥等で決まるバルク（結
晶母体）のライフタイムτbだけでなく半導体ウ
エーハの汚れや表面加工層等によつて決まるライ
フタイム値成分τsが関与するもので、
１／τｅｆｆ＝１／τｂ＋１／τｓ
なる関係があり、τsは半導体ウエーハの表面近
傍で起る表面再結合の速度Ｓに関係する。ウエー
ハ状の半導体結晶のτeffを測定する場合、外部
エネルギーを注入して励起させた過剰少数キヤリ
ヤの濃度が再結合によつて時間と共に減少してゆ
く状況を示す光導電減衰曲線はτbとＳの関係と
して現われ、Ｓの値が大きいと励起させた過剰少
数キヤリヤが拡散して表面で再結合する割合が多
くなり、τeffの値が小さくなるため極端な場合
には測定不能となる。 Generally, when measuring the lifetime of a semiconductor wafer, the actually measured effective lifetime τ eff is not only determined by the purity of the semiconductor crystal, crystal defects, etc., but also the lifetime τ b of the bulk (crystal matrix), as well as contamination and surface processing of the semiconductor wafer. It involves the lifetime value component τ s determined by the layer, etc., and there is a relationship of 1/τ eff = 1/τ b + 1/τ s , where τ s is the surface recombination that occurs near the surface of the semiconductor wafer. It is related to the speed S of When measuring τ eff of a wafer-shaped semiconductor crystal, the photoconductive decay curve, which shows the situation in which the concentration of excess minority carriers excited by injecting external energy decreases over time due to recombination, is τ b . It appears as a relationship of S, and when the value of S is large, the ratio of excited excess minority carriers diffusing and recombining on the surface increases, and the value of τ eff becomes small, making measurement impossible in extreme cases.
そこで、半導体ウエーハのτeffを測定するに
あたつて、表面再結合の速度Ｓを低減する必要が
ある。そのために、従来、半導体ウエーハの表面
近傍で起る、電子と正孔の再結合を緩和する手段
として、例えば、Ｎ型の半導体ウエーハに対して
その表面に正の電荷膜をつける処理を施し、Ｐ型
の半導体ウエーハに対してその表面に負の電荷膜
をつける処理を施し、半導体ウエーハの表面近傍
にポテンシヤル・バリヤーを形成することによつ
て半導体ウエーハの表面再結合速度を減少させる
方法がとられていた（宇佐美、神立、工藤、応用
物理49（1980）1192−1197）。また、他の方法と
して半導体ウエーハに電極をつけて、電解液中で
電圧を印加することによつて半導体ウエーハの表
面近傍にポテンシヤル・バリヤーを形成する方法
が提案されている。しかし、電荷膜をつける方法
では、半導体ウエーハの表面が汚染されるのでラ
イフタイム測定後に洗浄する必要があり、電極を
つける方法では測定試料ウエーハを再利用するこ
とができないという欠点があつた。 Therefore, when measuring τ eff of a semiconductor wafer, it is necessary to reduce the surface recombination speed S. To this end, conventionally, as a means of mitigating the recombination of electrons and holes that occurs near the surface of a semiconductor wafer, for example, an N-type semiconductor wafer is treated with a positively charged film on its surface. One method is to reduce the surface recombination rate of a P-type semiconductor wafer by applying a negative charge film to its surface and forming a potential barrier near the surface of the semiconductor wafer. (Usami, Kandatsu, Kudo, Applied Physics 49 (1980) 1192-1197). Another method has been proposed in which a potential barrier is formed near the surface of the semiconductor wafer by attaching electrodes to the semiconductor wafer and applying a voltage in an electrolytic solution. However, the method of attaching a charge film contaminates the surface of the semiconductor wafer and requires cleaning after lifetime measurement, and the method of attaching an electrode has the disadvantage that the measurement sample wafer cannot be reused.
そこで本発明は、上記従来の方法の欠点に鑑
み、シリコン等の半導体ウエーハのτeffを測定
するにあつて、ウエーハ表面に電荷膜をつけた
り、電極をつけたりする直接的な加工を一切行わ
ないでＳを低減する、非接触の半導体ウエーハの
ライフタイム測定方法を提供することを目的とす
る。 In view of the drawbacks of the conventional methods described above, the present invention aims to measure τ eff of semiconductor wafers such as silicon without performing any direct processing such as attaching a charge film or electrodes to the wafer surface. An object of the present invention is to provide a non-contact semiconductor wafer lifetime measurement method that reduces S.
本発明により提供される半導体ウエーハのライ
フタイム測定方法は、半導体ウエーハに禁止帯幅
以上のエネルギーをもつ光を照射し、励起した少
数キヤリヤの再結合減衰曲線を検出して半導体ウ
エーハの実効ライフタイムτeffを測定する方法
に於て、半導体ウエーハの同一表面に、ふたつの
光源ＡおよびＢからそれぞれ光を照射し、光源Ｂ
から照射する光によつて半導体ウエーハの表面近
傍に電子と正孔の対を生成させながら、光源Ａか
ら照射するパルス光によつて励起した少数キヤリ
ヤの再結合減衰曲線を検出してτeffを測定する
ことからなる方法である。 The semiconductor wafer lifetime measurement method provided by the present invention irradiates the semiconductor wafer with light having an energy greater than the forbidden band width, and detects the recombination decay curve of the excited minority carriers to measure the effective lifetime of the semiconductor wafer. In the method of measuring τ eff , the same surface of a semiconductor wafer is irradiated with light from two light sources A and B, and light source B
While generating pairs of electrons and holes near the surface of the semiconductor wafer using light emitted from the light source A, the recombination attenuation curve of minority carriers excited by the pulsed light emitted from the light source A is detected to calculate τ eff . This method consists of measuring.
本発明は、半導体の表面近傍に電子と正孔の対
を生成させる光を照射することによつてＳを低減
させることができるということに着目したもので
ある。すなわち、半導体の表面再結合速度は次の
式で示される（A.S.Grove著、John Wiley and
Sons，Inc.発行，「Physics and Technology of
Semiconductor Devices」，p.139）。 The present invention focuses on the fact that S can be reduced by irradiating light that generates pairs of electrons and holes near the surface of a semiconductor. In other words, the surface recombination rate of a semiconductor is expressed by the following formula (ASGrove, John Wiley and
Published by Sons, Inc., “Physics and Technology of
"Semiconductor Devices", p. 139).
Ｓ＝ＳpＮＤ／ｎｓ＋ｐｓ＋２ｏｉ
Ｓ：表面再結合速度
Ｓp：表面空間電荷領域のない場合の表面再結
合速度
ＮD：ドナー濃度
ｎs：表面電子濃度
ｐs：表面正孔濃度
ｎi：イントリンシツクキヤリヤー濃度
したがつて、半導体表面での電子濃度ｎsと正
孔濃度ｐsを増加することが出来れば、Ｓの値は
少さくなる。本発明の方法は、光源Ｂから禁止帯
幅より大きいエネルギーをもつ適当な波長のバイ
アス光を測定中に半導体ウエーハ表面に照射し続
けることにより、該表面近傍におけるｎsとｐsを
増加させるのである。 S=S p ND /n s + p s +2 oi S: Surface recombination rate S p : Surface recombination rate in the absence of surface space charge region N D : Donor concentration n s : Surface electron concentration p s : Surface positive Hole concentration n i :intrinsic carrier concentration Therefore, if the electron concentration n s and hole concentration p s at the semiconductor surface can be increased, the value of S will be reduced. The method of the present invention increases n s and p s in the vicinity of the surface by continuously irradiating the semiconductor wafer surface with bias light of an appropriate wavelength having energy greater than the forbidden band width from light source B during measurement. be.
次に、実施例に即してさらに具体的に本発明を
説明するが、本発明の範囲をこれに限定するもの
ではない。 Next, the present invention will be explained in more detail with reference to Examples, but the scope of the present invention is not limited thereto.
第１図は、本発明の方法を実施するのに適した
ライフタイム測定装置の一例を示す模式図であ
る。図の半導体ウエーハ１の一方の表面に光源Ｂ
から禁止帯幅以上のエネルギーをもつバイアス光
４を照射しながら、光源Ａから禁止帯幅以上のエ
ネルギーをもつパルス光（測定光）５を照射し
て、ウエーハ１の他の表面に導波管２を通してマ
イクロ波３ａを送り、その反射信号３ｂによつて
現出する半導体ウエーハ１に励起した少数キヤリ
ヤの再結合減衰曲線からτeffを測定する。 FIG. 1 is a schematic diagram showing an example of a lifetime measuring device suitable for carrying out the method of the present invention. A light source B is placed on one surface of the semiconductor wafer 1 shown in the figure.
While irradiating bias light 4 with energy greater than the forbidden band width from the light source A, pulsed light (measurement light) 5 having energy greater than the forbidden band width is irradiated from the light source A, and a waveguide is formed on the other surface of the wafer 1. A microwave 3a is sent through the semiconductor wafer 2, and τ eff is measured from the recombination attenuation curve of the minority carriers excited in the semiconductor wafer 1 appearing by the reflected signal 3b.
バイアス光４の波長が短い程半導体ウエーハ１
に生成する電子と正孔濃度のウエーハ深さ方向の
分布の最大位置はウエーハの受光表面に近づく。
したがつてバイアス光の波長を適当に選択すれば
ｎsとｐsの値を、Ｓを低減させるのに適当な状態
に保つことができる。 The shorter the wavelength of the bias light 4, the more the semiconductor wafer 1
The maximum position of the distribution of electron and hole concentrations generated in the wafer depth direction approaches the light-receiving surface of the wafer.
Therefore, by appropriately selecting the wavelength of the bias light, the values of n s and p s can be maintained in a state appropriate for reducing S.
第１図に示す装置によつて、比抵抗10Ω・cm、
厚さ500μのＮ型シリコンウエーハを試料として
次に(イ)および(ロ)のそれぞれの条件でτeffを測定
した。 By using the apparatus shown in Figure 1, a specific resistance of 10Ω・cm,
Using an N-type silicon wafer with a thickness of 500 μm as a sample, τ eff was measured under each of the conditions (a) and (b).
(イ) バイアス光波長660nm（ウエーハの片面全面
に連続照射）。(a) Bias light wavelength 660nm (continuous irradiation over one side of the wafer).
測定光波長940nm、パルス幅100μsec（ウエ
ーハの同一面にスポツト照射）。 Measurement light wavelength 940nm, pulse width 100μsec (spot irradiation on the same side of the wafer).
(ロ) バイアス光照を射せずに、前記同様の測定光
を照射。(b) Irradiate the same measurement light as above without emitting bias light.
その結果(イ)の場合に於てτeff＝20μsec、(ロ)の
場合に於てτeff＝10μsecの値を得た。また上記
と同一シリコンウエーハの表面に正電荷膜を付け
る処理を施して従来法によりτeffの値を測定し
た結果τeff＝22μsecの値を得た。この値は(イ)の
場合の測定結果と良く一致し、本発明の信頼性が
裏づけられた。バイアス光を照射した結果τeff
の値が大きくなつたことはＳが低減されているこ
とを意味している。 As a result, we obtained values of τ eff =20 μsec in case (a) and τ eff =10 μsec in case (b). Furthermore, the value of τ eff was measured by a conventional method using the same silicon wafer as described above, which was treated with a positively charged film on its surface, and as a result, a value of τ eff =22 μsec was obtained. This value agreed well with the measurement results in case (a), supporting the reliability of the present invention. The result of irradiation with bias light is τ eff
An increase in the value of S means that S is reduced.
前記と同一シリコンウエーハについて、光導電
減衰曲線の指数関数的な変化からのずれをもとに
Ｓを算出する方法（字佐美、神立、工藤、応用物
理49（1980）1192〜1197）によつて、Ｓの値を求
めた結果、(イ)の場合に於てＳ＝974cm／sec、(ロ)の
場合に於てＳ＝2207cm／secを得た。バイアス光
照射によりＳの値が約1/2に低減されている。 For the same silicon wafer as above, S was calculated based on the deviation from the exponential change in the photoconductivity decay curve (Azasami, Kandatsu, Kudo, Applied Physics 49 (1980) 1192-1197). As a result of determining the values of , S, in case (a), S = 974 cm/sec, and in case (b), S = 2207 cm/sec. The value of S is reduced to about 1/2 by bias light irradiation.
本発明は以上のような方法であるから、半導体
ウエーハの表面に電荷膜をつけたり、電極をつけ
る直接加工なしに、非接触でＳの値を低減するこ
とができるので便利であり、半導体ウエーハ製造
工程のみならず、集積回路等の半導体デバイス製
造工程に於ける、非接触、インライン評価方法と
して効果のある半導体ウエーハのライフタイム測
定方法である。 Since the present invention is a method as described above, it is convenient because it can reduce the value of S in a non-contact manner without applying a charge film or attaching electrodes to the surface of a semiconductor wafer. This is a semiconductor wafer lifetime measurement method that is effective as a non-contact, in-line evaluation method not only in manufacturing processes but also in the manufacturing process of semiconductor devices such as integrated circuits.
第１図は、本発明の方法を実施するのに適した
ライフタイム測定装置の一例を示す模式図であ
る。
１……半導体ウエーハ、２……導波管、３ａ…
…マイクロ波、３ｂ……マイクロ波反射信号、４
……バイアス光、５……パルス光（測定光）Ａ…
…光源、Ｂ……光源。
FIG. 1 is a schematic diagram showing an example of a lifetime measuring device suitable for carrying out the method of the present invention. 1... Semiconductor wafer, 2... Waveguide, 3a...
...Microwave, 3b...Microwave reflected signal, 4
...Bias light, 5...Pulsed light (measurement light) A...
...Light source, B...Light source.
Claims (1)
をもつ光を照射し、励起した少数キヤリヤの再結
合減衰曲線を検出して半導体ウエーハの実効ライ
フタイムτeffを測定する方法に於て、半導体ウ
エーハの同一表面に、ふたつの光源ＡおよびＢか
らそれぞれ光を照射し、光源Ｂから照射する光に
よつて半導体ウエーハの表面近傍に電子と正孔の
対を生成させながら、光源Ａから照射するパルス
光によつて励起した少数キヤリヤの再結合減衰曲
線を検出してτeffを測定することからなる半導
体ウエーハのライフタイム測定方法。1. In the method of measuring the effective lifetime τ eff of a semiconductor wafer by irradiating the semiconductor wafer with light having energy exceeding the forbidden band width and detecting the recombination decay curve of the excited minority carriers, The surface is irradiated with light from two light sources A and B, respectively, and the light irradiated from light source B generates pairs of electrons and holes near the surface of the semiconductor wafer, while the pulsed light irradiated from light source A generates pairs of electrons and holes near the surface of the semiconductor wafer. A method for measuring the lifetime of a semiconductor wafer, which comprises detecting the recombination decay curve of the minority carriers thus excited and measuring τ eff .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5391883A JPS59181549A (en) | 1983-03-31 | 1983-03-31 | Life time measurement of semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5391883A JPS59181549A (en) | 1983-03-31 | 1983-03-31 | Life time measurement of semiconductor wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59181549A JPS59181549A (en) | 1984-10-16 |
| JPS6248377B2 true JPS6248377B2 (en) | 1987-10-13 |
Family
ID=12956087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5391883A Granted JPS59181549A (en) | 1983-03-31 | 1983-03-31 | Life time measurement of semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59181549A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0666368B2 (en) * | 1987-07-14 | 1994-08-24 | 工業技術院長 | Semiconductor evaluation equipment |
| JPS6437843A (en) * | 1987-08-03 | 1989-02-08 | Kyushu Electron Metal | Method and device for measuring lifetime of semiconductor |
-
1983
- 1983-03-31 JP JP5391883A patent/JPS59181549A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59181549A (en) | 1984-10-16 |
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