JPS61101045A - Method for evaluation of semiconductor - Google Patents
Method for evaluation of semiconductorInfo
- Publication number
- JPS61101045A JPS61101045A JP22205384A JP22205384A JPS61101045A JP S61101045 A JPS61101045 A JP S61101045A JP 22205384 A JP22205384 A JP 22205384A JP 22205384 A JP22205384 A JP 22205384A JP S61101045 A JPS61101045 A JP S61101045A
- Authority
- JP
- Japan
- Prior art keywords
- temperature
- microwaves
- semiconductor
- sample
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体の電気特性の評価に係り、特に半導体内
のキャリア捕獲準位測定に好適な評価方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the evaluation of electrical characteristics of semiconductors, and particularly to an evaluation method suitable for measuring carrier trapping levels in semiconductors.
従来、半導体内に存在するキャリア捕獲準位の測定には
ＤＬＴＳ法（Ｄｅｅｐ Ｌｅｖｅｌ Ｔｒａｎｓｉｅｎ
ｔＳｐｅｅｔｒｏｓｃｏｐｙ ： Ｄ、 Ｖ、 Ｌａｎ
ｇ、 Ｊ、 Ａｐｐｌ、 Ｐｈｙｓ、 ｉ互（１９７４
） ３０２３）が最も信頼度の高い方法として広く用い
られてきた。この方法は半導体内にｐｎ接合またはショ
ットキ接合を作成し、接合面に形成されるキャリア空乏
領域に電気的又は光学的に注入されたキャリアの寿命を
、半導体上に形成された電極を通じて測定するものであ
る。従って従来のｒ）ＬＴＳ法では、半導体に接合及び
電極を形成する工程を経なければ測定する事が不可能で
あり、半導体そのものの電気的性質を調べる事はできな
かった。Conventionally, the DLTS method (Deep Level Transient) has been used to measure carrier trapping levels existing in semiconductors.
tSpeetroscopy: D, V, Lan
G, J., Appl, Phys, I. (1974)
) 3023) has been widely used as the most reliable method. In this method, a pn junction or Schottky junction is created in a semiconductor, and the lifetime of carriers electrically or optically injected into a carrier depletion region formed at the junction surface is measured through an electrode formed on the semiconductor. It is. Therefore, with the conventional r)LTS method, it is impossible to measure without going through the process of forming a junction and an electrode on the semiconductor, and it has not been possible to investigate the electrical properties of the semiconductor itself.
本発明の目的は半導体内に存在するキャリア捕獲準位を
半導体の導伝率に係わりなく、 （１０”Ω・１以上
の高抵抗半導体をも含めて）非破壊に測定する方法を提
供することにある。The purpose of the present invention is to provide a method for non-destructively measuring carrier trapping levels existing in a semiconductor (including high resistance semiconductors of 10"Ω.1 or more), regardless of the conductivity of the semiconductor. It is in.
ＤＬＴＳ法の根本原理は半導体内に注入された自由キャ
リアの寿命を温度の関数として測定する事にある。The fundamental principle of the DLTS method is to measure the lifetime of free carriers injected into a semiconductor as a function of temperature.
一方半導体内のキャリア寿命を測定する方法として半導
体にマイクロ波を照射した時の自由キャリアによる吸収
率の過渡減衰を測る方法がある。On the other hand, there is a method of measuring the lifetime of carriers in a semiconductor by measuring the transient attenuation of the absorption rate due to free carriers when the semiconductor is irradiated with microwaves.
（宇佐美 品「非接触方式によるシリコンウェハライフ
タイム測定技術Ｊ、電子材料（１９８１年２月号）ｐ、
６７）この方法によれば、１０８Ω・■程度の高抵抗半
導体に対してもキャリア寿命の測定が、半導体を加工す
る事なく可能となる。(Shin Usami, “Silicon wafer lifetime measurement technology using non-contact method J, Electronic Materials (February 1981 issue), p.
67) According to this method, carrier life can be measured even for a high resistance semiconductor of about 10 8 Ω·■ without processing the semiconductor.
そこでマイクロ波を用いたキャリア寿命の測定を温度を
掃引しながら行なう事により、従来のＤＬＴＳ法と同じ
物理量を非破壊に求める事ができる。Therefore, by measuring the carrier lifetime using microwaves while sweeping the temperature, it is possible to non-destructively obtain the same physical quantity as the conventional DLTS method.
本発明はこの様な原理に基づく測定方法を提供するもの
で、特に真空容器中の温度可変試料台を用いる事により
液体窒素温度（７７Ｋ）程度の低温域においても試料表
面での水分の影響などを受けない高精度の測定が可能と
なる。The present invention provides a measurement method based on such a principle. In particular, by using a temperature-variable sample stage in a vacuum container, the influence of moisture on the sample surface can be avoided even in the low temperature range of liquid nitrogen temperature (77K). This enables highly accurate measurements that are free from interference.
さらに本発明によれば被測定試料をウェハ状の半導体と
する事により、吸収及び散乱されるマイクロ波の試料形
状依存性をほとんど無視する事ができる為、半導体の電
気特性のみを反映した再現性の高い評価が可能である。Furthermore, according to the present invention, by using a wafer-shaped semiconductor as the sample to be measured, it is possible to almost ignore the dependence of absorbed and scattered microwaves on the sample shape, thereby achieving reproducibility that reflects only the electrical characteristics of the semiconductor. A high evaluation is possible.
以下本発明の一実施例を第１図により説明する。 An embodiment of the present invention will be described below with reference to FIG.
第１図に本発明の測定法を実施する為の装置配置例を示
す。マイクロ波発生器１からのマイクロ波はサーキュレ
ータ３を介して真空容器５のボートから試料６に照射さ
れる。本実施例では試料はウェハ状の半導体結晶で、マ
イクロ波をウェハ面内の一部分にのみ照射する事により
吸収及び散乱されるマイクロ波の試料形状依存性を無視
できる様にしである。試料面内のマイクロ波照射部の一
部にレーザ１３からのビーム１１を照射し半導体内に自
由キャリアを励起する。温度可変の試料台７はマイクロ
波反射板を兼ねており、反射されたマイクロ波はサーキ
ュレータ３を経て検波器１０で検出される。本実施例で
は試料台７は７７に〜４００にの領域で温度可変で、温
度は熱電対８及び温度検出器１４で電気信号に変換され
る。１２は検波信号の増幅器で出力側はパルス状のレー
ザビーム１１と同期してオシロスコープ１５に接続され
信号の過渡減衰の時定数が測定される。温度及び検波信
号は信号処理部１６に送られ解析される。FIG. 1 shows an example of the arrangement of equipment for carrying out the measurement method of the present invention. Microwaves from the microwave generator 1 are irradiated onto the sample 6 from the boat of the vacuum container 5 via the circulator 3 . In this example, the sample is a wafer-shaped semiconductor crystal, and by irradiating microwaves only to a part of the wafer surface, the dependence of the microwaves absorbed and scattered on the sample shape can be ignored. A beam 11 from a laser 13 is irradiated onto a part of the microwave irradiation area within the sample surface to excite free carriers within the semiconductor. The temperature-variable sample stage 7 also serves as a microwave reflector, and the reflected microwaves are detected by the detector 10 via the circulator 3. In this embodiment, the temperature of the sample stage 7 is variable in a range from 77 to 400 degrees, and the temperature is converted into an electrical signal by a thermocouple 8 and a temperature detector 14. Reference numeral 12 denotes a detection signal amplifier, and its output side is connected to an oscilloscope 15 in synchronization with the pulsed laser beam 11 to measure the time constant of transient attenuation of the signal. The temperature and detection signals are sent to the signal processing section 16 and analyzed.
第２図、第３図は試料として半絶縁性ガリウムヒ素ウェ
ハを用いた評価結果の一例である。第２図はオシロスコ
ープ出力例で、１ｏは光パルスが照射された時刻でては
１ ／ ｅ減衰点で定義した時定数である。このτの温
度依存性を測定した結果が第３図で、横軸が試料温度、
縦軸が時定数τである。この信号は通常のＤＬＴＳと同
様の解析手法で解析され、図中のピークはそれぞれＥＬ
６とＥＬ９という深い不純物準位（参照： Ｇ、 Ｍ、
Ｍａｒｔｉｎ、 Ａ。FIGS. 2 and 3 are examples of evaluation results using semi-insulating gallium arsenide wafers as samples. FIG. 2 shows an example of the oscilloscope output, where 1o is the time constant defined as 1/e attenuation point at the time when the light pulse is irradiated. Figure 3 shows the results of measuring the temperature dependence of τ, where the horizontal axis is the sample temperature and
The vertical axis is the time constant τ. This signal is analyzed using the same analysis method as normal DLTS, and the peaks in the figure are each EL.
6 and EL9 deep impurity levels (see: G, M,
Martin, A.
Ｍｉｔｏｎｎｅａｕ ａｎｄ Ａ、 Ｍｉｒｃｅａ ：
Ｅｌｅｃｔｒｏｎｉｃｓ Ｌｅｔｔｅｒｓ旦（１９７
７） １９１−１９３）である事が確かめられた。Mitonneau and A, Mircea:
Electronics Letters (197
7) It was confirmed that 191-193).
本実施例によれば従来ＤＬＴ’Ｓ法などの有効な評価法
が適応できなかった半絶縁性（１０’ Ω・ｌ程度の
高抵抗の）半導体の深さ不純物中位を非破壊に測定する
事が可能である。According to this embodiment, it is possible to non-destructively measure the intermediate depth of impurities in a semi-insulating (high resistance of about 10' Ω·l) semiconductor, to which effective evaluation methods such as the DLT'S method could not be applied. things are possible.
［発明の効果〕
本発明によれば、ＬＳＩ用のＧａＡｓなどの抵抗の高い
半導体の電気特性を非破壊に評価する事が可能である。[Effects of the Invention] According to the present invention, it is possible to nondestructively evaluate the electrical characteristics of a semiconductor with high resistance such as GaAs for LSI.
従らて従来、同一インボッ１−の素化の近いウェハを加
工して行なわれていたウェハ結晶の選別が全数に対して
可能となる。即ち従来数日の結晶加工工程の後行なわれ
た測定が、本発明によれば加工工程なしで直接実施する
事ができる。Therefore, the sorting of wafer crystals, which was conventionally carried out by processing wafers of similar quality from the same inboard, becomes possible for all the wafers. That is, measurements that were conventionally carried out after several days of crystal processing can be carried out directly without any processing according to the present invention.
またＧａＡｓなどのウェハ結晶の場合、その物理的特性
や電気的特性はウェハ面内及び同一インゴット内のウェ
ハ同士で大きくばらついている。例えば欠陥密度は通常
３ＸＩＣ）３〜ｌＸｌ０２（Ｊｌｌ−”の範囲内でウェ
ハ内分布があり、また残留１２Ｃや１４ｓｉなどもイン
ゴット縦方向で最大１０〜１００倍の比率で分布してい
る。従ってこの様な特性分布を考えた場合、従来の選択
方法では甚だ不十分であるといえる。これに対′し本発
明では素子として利用する領域を直接評価できるので、
従来にない適確なウェハ選別が可能となる。Further, in the case of a wafer crystal such as GaAs, its physical properties and electrical properties vary widely within the wafer plane and between wafers within the same ingot. For example, the defect density is normally distributed within the wafer within the range of 3XIC)3 to lXl02 (Jll-''), and residual 12C and 14si are also distributed at a maximum ratio of 10 to 100 times in the longitudinal direction of the ingot. When considering various characteristic distributions, it can be said that conventional selection methods are extremely insufficient.On the other hand, the present invention allows direct evaluation of the area to be used as an element.
This enables more accurate wafer sorting than ever before.
第１図は本発明の一実施例の装置構成図、第２図は第１
図中のオシロスコープで観測される信号例を示す図、第
３図は第１図の装置で測定された解析結果の一例を示す
図である。Figure 1 is a configuration diagram of an apparatus according to an embodiment of the present invention, and Figure 2 is a diagram of the configuration of an apparatus according to an embodiment of the present invention.
FIG. 3 is a diagram showing an example of a signal observed by the oscilloscope in the figure, and FIG. 3 is a diagram showing an example of an analysis result measured by the apparatus shown in FIG.
Claims (1)
の半導体にマイクロ波を照射し、更にマイクロ波照射領
域の一部分に光パルス又は電子ビームパルスを照射し、
これに起因するマイクロ波のインピーダンス変化量を測
定する事を特徴とする半導体評価方法。1. Irradiate a wafer-shaped semiconductor fixed on a temperature-variable sample stage in a vacuum container with microwaves, and further irradiate a part of the microwave irradiation area with a light pulse or an electron beam pulse,
A semiconductor evaluation method characterized by measuring the amount of microwave impedance change caused by this.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22205384A JPS61101045A (en) | 1984-10-24 | 1984-10-24 | Method for evaluation of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22205384A JPS61101045A (en) | 1984-10-24 | 1984-10-24 | Method for evaluation of semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61101045A true JPS61101045A (en) | 1986-05-19 |
Family
ID=16776356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22205384A Pending JPS61101045A (en) | 1984-10-24 | 1984-10-24 | Method for evaluation of semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61101045A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02248061A (en) * | 1989-03-20 | 1990-10-03 | Semitetsukusu:Kk | Lifetime measurement of semiconductor material |
| JPH0493043A (en) * | 1990-08-09 | 1992-03-25 | Semitetsukusu:Kk | Method and apparatus for measurement of deep impurity level in semiconductor |
| JPH07153809A (en) * | 1993-11-26 | 1995-06-16 | Nec Corp | Method and apparatus for impurity analysis of semiconductor substrate |
| JP2002151560A (en) * | 2000-11-07 | 2002-05-24 | Shin Etsu Handotai Co Ltd | Method and apparatus for measuring internal defect of semiconductor wafer as well as manufacturing method for semiconductor wafer |
| KR100536518B1 (en) * | 1999-09-29 | 2005-12-14 | 고등기술연구원연구조합 | Method for measuring thermal property of organic thin film |
-
1984
- 1984-10-24 JP JP22205384A patent/JPS61101045A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02248061A (en) * | 1989-03-20 | 1990-10-03 | Semitetsukusu:Kk | Lifetime measurement of semiconductor material |
| JPH0493043A (en) * | 1990-08-09 | 1992-03-25 | Semitetsukusu:Kk | Method and apparatus for measurement of deep impurity level in semiconductor |
| JPH07153809A (en) * | 1993-11-26 | 1995-06-16 | Nec Corp | Method and apparatus for impurity analysis of semiconductor substrate |
| KR100536518B1 (en) * | 1999-09-29 | 2005-12-14 | 고등기술연구원연구조합 | Method for measuring thermal property of organic thin film |
| JP2002151560A (en) * | 2000-11-07 | 2002-05-24 | Shin Etsu Handotai Co Ltd | Method and apparatus for measuring internal defect of semiconductor wafer as well as manufacturing method for semiconductor wafer |
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