JPS6247129A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To conduct accurate patterning by altering the exposing conditions by dividing one chip region into a plurality of regions to be exposed, and using a photomask having patterns of different correction values according to regions to be exposed. CONSTITUTION:Chip regions 2 are divided into A-C, and exposed under separate exposing conditions by reticles 1a-1c. The reticle 1a having a pattern of large correction value of 4mum is used, slightly excess exposing conditions are given to form an accurate resist pattern 41 on the region A. Similarly, the region B is exposed with the reticle 1b having a pattern 32 of approximately intermediate size of correction value of 3mum, and the region C is exposed with the reticle 1c having the most ultrafine pattern 33 of correction value of 2mum. According to this configuration, accurate various resist patterns can be formed on respective one unit regions having various sizes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A conventional unit exposure area is divided into a plurality of exposure areas, and each exposure area is exposed using a photomask having a pattern with a different correction value.

[Industrial Application Field] The present invention relates to a semiconductor device manufacturing method, and particularly to an exposure method in a photo process.

In the manufacturing method of semiconductor devices, one of the essential manufacturing steps is a so-called photo process in which fine patterns are formed by photolithography, and a photomask is very important in this photo process. In the past, emulsion masks were used as photomasks2, but recently, as ICs become more highly integrated and finer, hard masks, which are excellent in forming fine patterns, have become widely used.

A hard mask is a metal film with a light-shielding film pattern.

A mask formed of a metal oxide film, etc., and is generally a chromium (Cr) film or chromium oxide (C) film with a thickness of about 1000 mm.
r203) A pattern is formed by a film or a composite film of both.

On the other hand, semiconductor devices such as ICs have become significantly thinner by 1Iik.
In order to form fine patterns with high precision in highly integrated hard masks, a pattern is created by adding correction values to predetermined pattern dimensions, taking into account exposure conditions, and using such a mask. exposed. However, it is important to give appropriate correction values to the pattern.

[Problems to be solved by conventional technology and invention]
Bar 1 - There are two types of masks: a mask for close exposure and a reticle for reduced exposure.
An exposure method is used in which a 10x pattern is set up, and this is reduced to 115 to 1/10 using a lens system and exposed onto the semiconductor substrate.

This is a method that has become widely used as an alternative to contact exposure due to advances in optical equipment. Unlike contact exposure, it is not possible to expose the semiconductor substrate all at once, but for example, it is possible to repeatedly expose each chip area of the semiconductor substrate. This is a method that allows highly accurate patterning of layers. The present invention
A reticle will be described below as an example.

Figure 3 shows a schematic cross-section of a conventional exposure method using a reticle.
-1- reticle pattern, 2b chip area of semiconductor substrate, 21.22 reticle pattern 11.12 17
This is a positive type resist 1 pattern of the chip area 2-[ which is exposed in a reduced size to 10. Among them, reticle pattern 1
1 is a pattern for forming a resist 1-pattern with a size of approximately 1 (Ium) and 1 μm on the conductor plate, and the reticle pattern 12 is approximately 1 μm in size.
With a size of 0011m, the semiconductor substrate -1-δ IOit
This is a pattern for forming a resist pattern with a size of m.

However, in the exposure process, if the exposure is insufficient, a problem may easily occur in which the resist 1- remains even in unnecessary areas (removed areas of the resist 1) during development.
It is customary to completely remove unnecessary parts. For this reason, in L/Chikulbacoon 11.12, a slightly larger pattern is provided in anticipation of overexposure, for example, a pattern in which 4ttm is added as a correction value to the predetermined size is provided. If this is done, the reticle pattern 1 will have a size of 104 μm, and the reticle pattern 12 will have a size of 14 μm.

However, when these reticle patterns 11 and 12 are exposed, the resist pattern 21 formed by the reticle pattern 11 under certain exposure conditions becomes exactly 101! When the resist pattern 22 is formed with high precision as 1.m, the resist pattern 22 formed by one small reticle pattern I2 is 1.m.
1-1.2. +zm, which makes it easier to form a slightly larger pattern.

On the other hand, it is conceivable that a method of adding such a correction value not uniformly but at a constant ratio proportional to the size of the pattern,
Even in that case, since the exposure conditions are the same, a difference in precision between the large pattern and the small pattern is unavoidable, and it is difficult to form both patterns with high precision. Therefore, in order to pattern with high precision, it is most desirable to set exposure conditions suitable for the size of the pattern.

The present invention solves these problems and provides a fixed area having various sizes of patterns, for example, a chip area.
We propose an exposure method for patterning all with high precision.

[Means to Solve the Problem] The problem is a semiconductor device in which one unit area is divided into a plurality of exposure areas, and each exposure area is exposed using a photomask having a pattern with a different correction value. The problem is solved by the manufacturing method (exposure method).

[Function] That is, in the present invention, for example, one chip area is divided into a plurality of exposure areas, and exposure is performed by changing the exposure conditions using a photomask provided with a pattern with a different correction value for each exposure area.

This makes it possible to provide exposure conditions suitable for the size of the pattern in that region, resulting in highly accurate patterning.

[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a chip area 2 divided into a plurality of exposure areas according to the present invention, A and B in this example.

It is divided into three areas: C. Furthermore, assuming that there are large patterns in the AV4 area, medium patterns in the B area, and small patterns in the C area, this chip area is each divided by three reticles consisting of Ia, lb, and lc. Perform separate exposures with different exposure amounts.

As in this example, patterns with relatively different sizes are often formed in different areas within a chip.
In C, the gate circuit 1 peripheral circuit.

Power supply connection circuits, etc. are provided for each chip region.

FIG. 2 [al to fc) is a schematic cross-sectional view showing the exposure method of the above example, and +111 in the same figure shows the chip 2 by the reticle la.
It shows a cross section where the area is exposed, and the large reticle pattern 31 is 10477 m, of which the correction value L;
l: 4 t m. Then, by adding 11 slightly excessive exposure conditions (exposure amount, exposure time, etc.), the chip area 2
A highly accurate resist I-pattern 41 of 101 nm is formed thereon.

Next, as shown in FIG. 2 (hl), area B is exposed by the reticle 1b, and the medium-sized reticle pattern 32 is 53 μrn, of which the correction value is 3 pm.
Using this reticle pattern 32, excessive exposure conditions are applied to expose the BRJI area of the chip 2 to form a highly accurate resist pattern 42 of 5 μm.

Next, as shown in FIG. 2 (C1), area C is exposed using the reticle 1c, but the finest reticle pattern 33 is 1211 m, of which the correction value is 277 m, and this reticle pattern 33 further prevents excessive exposure. The C region of the chip 2 is exposed under certain conditions to form a fine hum resist pattern 43 with high precision.

In this way, it becomes possible to form various highly accurate resist 1-patterns in one unit area having patterns of various sizes.

Although the above embodiments have been described using a positive type resist, the present invention can be applied to a negative type resist as well, and can be applied not only to a reticle but also to a mask for contact exposure.

[Effects of the Invention] As is clear from the above description, according to the present invention, it is possible to form a resist pattern with even higher precision on a semiconductor substrate, thereby significantly contributing to the improvement of the quality of ICs. It is something.

[Brief explanation of drawings]

FIG. 1 is a divided diagram of a chip area according to the present invention, FIG. 2 is a schematic diagram of the exposure process sequence of the present invention, and FIG. 3 is a schematic cross-sectional diagram of conventional exposure. In the figure, ], la, Ih, Ic are reticle, 2 is chip area, 11, 12, 31, 32, 33 is reticle pattern, key 4 φ≦E111-?〉 Sina = 77', monk pear one zugo Gotogu G Town Figure 1 (G> / /(b)X \

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device, characterized in that one unit area is divided into a plurality of exposure areas, and each of the exposure areas is exposed using a photomask provided with a pattern having a different correction value.