JPS6028230A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To compensate the displacement of exposure regions by forming a connecting region between the exposure regions and directly drawing the connecting region by charged beams. CONSTITUTION:An Al film 13 as a wiring is applied on a Si substrate 11, to which a desired element is formed and at the predetermined position of the surface thereof a mark for aligning a mask is put, through a SiO2 film 12, and the upper section of the film 13 is coated with a crossed positive type resist film 14. Regions 17 and 17', 18 and 18', which are positioned at the left and right of a border m-m' and each hold wiring regions 19 and 20, are exposed while using the film 13 as a mask, and developed, and the films 13 in the regions are removed. The positions of the corner sections 21-24 of the residual crossed film 13 are detected, and regions 25 and 25' in the vicinity of the border m-m' are exposed, developed and removed when a cross is not displaced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device suitable for patterning large-area chips.

[Technical background of the invention and its problems]

In recent years, the development of LSI manufacturing technology has been remarkable, and the degree of integration has been increasing. This increase in the degree of integration is largely due to advances in exposure technology for forming resist patterns with minute dimensions.

Currently, the most widely used exposure device (LSI) is an exposure device called Wafer Stellar.
A method (step-and-repeat method) is adopted in which the image is reduced in size by 5 to 1/10 and transferred to a resist coated on a wafer, and then exposed to light by successively changing the position on the wafer.

With this type of light exposure technology, it is currently possible to accurately form a minimum line width of about 1 [μm], and efforts are being made to further achieve a minimum line width of 0.7 to 0.5 [μm]. Technology development is progressing.

However, while maintaining the size that can be exposed in one projection at the current size of 10 to 12 (tan) angles, the resolution has been increased from the current 1 [μm] to ~0.
It is extremely difficult to increase the thickness to 5 [μm]. Also, for example, with a resolution of 0.5 [μtn], 12 [: rmn
:] Even if a square exposure area can be obtained, the area of LSI chips tends to increase year by year, and it will no longer be possible to support chips as large as 12 mm or more. For this reason, L
Increasing the chip area of SI has been accompanied by great difficulties.

Therefore, recently, when the chip area is large, a method of dividing the chip area into a plurality of exposure areas and exposing each area separately to form one large chip has been studied.

FIG. 1 is a diagram illustrating this divided exposure.

In the figure, 41 is a reticle that can be moved in the X direction. 42 is a lens, and 43 is a wafer which is mechanically moved in the xyx directions. When the reticle is exposed to AP light, only the wafer 43 moves, and here 6 chips are exposed. When exposing reticle B, reticle 41 moves to the position of reticle A. The overlapping of the masks in area A on the wafer is done by looking through the marker already formed in area A and the reticle image to be exposed from above (for example, when looking through, only the vicinity of the marker is illuminated). There is no deviation at all.

However, a shift occurs between areas A and B on the wafer due to mechanical movement of the wafer. That is, this method has a problem in that inconveniences occur at the boundaries between the exposure areas due to relative positional deviations between the exposure areas.

The above problem will be explained below by taking M wiring pattern formation as an example. Figures 2 (,) to (c) are plan views showing an enlarged part of the vicinity of the boundary between the two exposure areas 1.2 (indicated by the broken line t-t' in the figure); 3 generated in wiring 3, 3'
This figure shows two examples of defects. Fig. 2(a) shows a state in which the At wirings 3, 3' are not connected because the two regions 1, 2 are shifted in the Y direction, and Fig. 2(b) shows a state in which the At wirings 3, 3' are not connected.
3' is shifted in the X and Y directions and is not connected.

Further, FIG. 2(c) shows a state in which regions 1 and 2 are slightly shifted in the Y direction and At wires 3 and 3' are connected, but there is a thin strip at the connection portion. In this case, the reliability of the wiring decreases, and if current continues to flow for a long time, disconnection will occur at the connection.

As a countermeasure to this problem, as shown in Figure 3, 74 turns 3
, the idea was to make the 3' end wider and make it protrude into the opponent's area. However, since the pitch of the pattern had to be greatly increased, there was a problem in increasing the density.

For the reasons mentioned above, it has been difficult to realize large LSI chips with fine patterns using current LSI manufacturing technology.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent the R-turn from becoming narrow or broken due to a shift in the exposure area, and can realize a large LSI chip with a fine pattern. be.

[Summary of the invention]

The gist of the present invention is to provide a connection area between the exposure areas and directly write the connection area with a charged beam to correct the deviation of the exposure areas.

In short, the present invention is a semiconductor device manufacturing method in which four turns formed on a reticle are reduced and projected onto a semiconductor wafer to form a desired turn, in which one chip in the wafer is exposed. At least two different patterns are exposed separately, and then a pattern indicating the exposure position is detected, and based on this detection information, a predetermined point in one exposure area and a predetermined point in the adjacent exposure area are exposed. This method uses direct drawing to form a pattern that connects points across both areas.

〔Effect of the invention〕

According to the present invention, since the chip area is divided into a plurality of exposure areas, an area of any size can be exposed while maintaining the dimensional accuracy of fine/4' turns with high accuracy. Furthermore, the connection part caused by the deviation of the exposure area
Problems such as thin lines and breakage of the setan can be prevented by forming the connection pattern by direct writing. Therefore, a large-area LSI chip with a significantly high degree of integration can be realized, and its usefulness in the future field of semiconductor manufacturing technology will be enormous.

[Embodiments of the invention]

FIGS. 4(,) to (c) show wiring and! according to an embodiment of the present invention. It is a figure which shows the turn formation process. First, Figure 4 (,
) As shown in the cross-sectional view, StO film 1 is placed on St substrate 11.
2, the At film 13 is deposited on the At film 13, and the I film 13 is further deposited on the At film 13.
A Z type resist 14 was applied. Here, it is assumed that the 81 substrate 11 has a desired element formed thereon, although not shown. Further, it is assumed that alignment marks (not shown) for mask alignment are formed at predetermined positions on the Sl substrate 11.

Next, the arbitrary chip area of the above-mentioned Ueno) 11 is shown in FIG.
As shown in b), the area 15.16 is divided into two exposure areas 15.16 using mm-m' as a boundary, and each area 15.16 is divided into two exposure areas 15.16.
16, separate patterns are exposed by reduction projection. In the figure, the shaded areas 17° and 17' are exposed by the first projection, and the shaded areas 18 and 18' are exposed by the second projection. In the case of this embodiment, since the resist 14 is positive type, the above regions 17, 17', 18°18'
will be removed during subsequent development. Note that the marks are previously formed in both of the exposure areas 15 and 16.

Next, the positions of the marks are detected using an electron beam exposure device, and the positions of the exposure areas 15 and 16 are recognized. For this mark position detection, a method of detecting secondary electrons emitted from the mark by electron beam irradiation, a method of using laser light, or the like may be selected as appropriate. Next, the coordinates of the corner positions 21, 22, and 23° 24 of the areas 19 and 20 that are to become wiring are calculated. After that, as shown in FIG. 4(C), in order to leave four openwork areas surrounded by corner positions 21, 22, 23, and 24, areas 25 and 25' (indicated by crossed diagonal lines in the figure)
Draw directly.

After this, the resist in the area irradiated with the light or electron beam is removed by development using the normal process.
, 27. Only the resists of 28 are left. Next, using the remaining resist as a mask, the At film 13 is selectively etched by, for example, reactive ion etching.
One At wiring is located in area 26, 27, and 28 in area 1.
It will be formed across 5.26.

Thus, according to the method of this embodiment, it is possible to prevent thin At wiring from breaking due to relative positional deviation of the respective regions 15 and 16 at the boundary m-m' between the exposure regions j5 and 16. Since this does not occur at all, it is possible to improve the reliability of wiring.

Therefore, it is possible to manufacture highly reliable LSIs. Further, in principle, the present invention can be applied in exactly the same way even when a large number of exposure regions are formed adjacent to each other, so it is possible to realize any large chip. Moreover, since the size of each exposure area can be arbitrarily selected so as to provide the best resolution, it is possible to manufacture highly reliable LSIs with fine grooves and large chip areas.

FIGS. 5(a) to 5(f) are diagrams showing manufacturing steps of other embodiments. Note that the same parts as in FIGS. 4(,) to (C) are given the same reference numerals, and detailed explanations thereof are omitted.

This embodiment differs from the previously described embodiments in that light exposure and electron beam writing are performed on separate AA films.

First, the chip area of the sample as shown in FIG. 4(a) is divided into two exposure areas 15 and 16 as in the previous example as shown in FIG. 6(a), and these areas are reduced. Expose by projection. In the figure, a shaded area 31 is a portion exposed by the first projection, and a shaded area 32 is a portion exposed by the second projection. Next, the resist 14 is developed and the resist in the regions 31 and 32 is removed, leaving the resist only on the regions 19 and 20 that are to become wirings.

Next, using the remaining resist as a mask,
), the At film 13 is selectively etched by reactive ion etching. Next, @Figure 5 (c
), a S102 film 33 is deposited on the entire surface, and this 5
Contact holes 34 and 35 are formed in the i02 film 33. Subsequently, as shown in FIG. 5(d), an At film 36 is deposited on the entire surface, and then a resist film (electron beam resist) is applied.
Apply 37.

Next, following the same procedure as in the previous embodiment, a pattern connecting the contact holes 34 and 35 is drawn by electron beam direct writing as shown in FIG. 5(e). Next, by developing the resist 37 and selectively etching the At film 36, a second layer of At wiring is formed as shown in FIG. 5(f).

Thus, according to this embodiment, as in the previous embodiment, area 2
6.27.28 A single wire is placed in the exposure area 15.
Therefore, the same effect as the previous embodiment can be obtained. Still, different resists can be used for light exposure and electron beam writing, so resist selection is extremely easy.

Further, since electron beam lithography is performed for A turning of the upper At film 36 after etching the lower At film 13, the A after etching of the lower At film 13? It is also possible to detect the turn corner and correct the deviation of the exposure area 15,16.

Note that the present invention is not limited to the embodiments described above. For example, the material to be formed with a turn is not limited to AA wiring, but may be a diffusion layer, silicide wiring such as 2S St or Mo5T, or any other layer constituting an LSI. In the examples shown in a) to (C), the resist was developed after completing light exposure and electron beam drawing, but this process is not limited in any way. ) After the steps shown in
Development and etching may be performed, then an electron beam resist may be applied, drawing may be performed in the same manner as shown in FIG. 4(c), and development and etching may be performed again. In this case, during electron beam writing, the At/mother turn formed by light exposure can be used as a pattern for detecting the position of each exposure area, so alignment between the pattern by electron beam drawing and the pattern by light exposure can be used. Accuracy can be increased. (6th
(Figure) Furthermore, the iR pattern indicating the exposure position may be a mark for mask alignment when performing light exposure,
It may also be one specially prepared for electron beam lithography. Further, the structure may be a groove formed on an Sl substrate, a predetermined lean structure formed of an insulator, a 7+9 layer, or a metal film. Furthermore, it goes without saying that not only a positive type resist but also a negative type resist can be used.

FIG. 7 shows a charged beam exposure apparatus used in the above embodiment. 51 is an electron gun, 51a is a cathode, 51b is an anode, 52a, 52b152c are electron lenses, 53 is a blanking circuit, 54 is a deflection circuit, 55 is an xy stage, 56 is a stage drive system, 57 is a wafer, 58 is a marker, 59 is an electron beam, 60 is a backscattered electron detector, 6
Reference numeral 1 represents a control circuit, and reference numeral 62 represents an information storage circuit.

When the wafer 57 is set, the electron beam 59 is applied to the marker 58 (not limited to the specially provided marker as described above) formed during each divisional exposure, and the position of each marker is detected by the backscattered electron detector 60. be done. On the other hand, the turn information storage circuit 62 stores at least each marker position corresponding to the areas A to D and the position of a point to be connected between the areas A to D. Therefore, by comparing this stored information with the above-mentioned detection information in the control circuit 61, the connection points of the wafers on the stage can be determined.
Then, the shape of the connection wiring is determined. Based on the information from the control circuit 61, the deflection system is controlled to perform direct writing. In addition, various modifications can be made without departing from the gist of the present invention.

[Brief explanation of the drawings] Fig. 1 is a diagram showing divided exposure, Figs. 2 (a) to (C) and Fig. 3 are plan views for explaining conventional problems, and Fig. 4 (a) - (C) are cross-sectional views and plan views showing the wiring A turn forming process according to an embodiment of the present invention, and Fig. 5 (a) - (
f) is a cross-sectional view and a plan view for explaining the process of another embodiment, FIG. 6 is a plan view for explaining another embodiment, and FIG.
The figure is a sectional view of the device used in this example. 11...Si substrate, 12...SiO□ film, 13.3
6... kA film, 14.37... resist, 15.1
6... exposure area, 26, 27.28... kl wiring area. Applicant's representative Patent attorney Takeshi Suzue Syllable 1 Figure 2
One wheel,] I L-----L----, J Figure 3 ■ ■ - Figure 4 Figure 5 Figure 5 Figure 6 Mum

Claims (3)

[Claims] (1) In a semiconductor device manufacturing method in which a desired pattern is formed by reducing and projecting a pattern formed on a reticle onto a semiconductor wafer, at least two different A process of separately exposing nine turns adjacent to each other, then detecting a pattern indicating the exposure position, and based on this detection information, a predetermined point in one exposure area and a predetermined point in the adjacent exposure area. 1. A method of manufacturing a semiconductor device, comprising forming a pattern by direct writing to connect the points in both regions. (2) As the pattern indicating the exposure position, an alignment mark formed in advance on the chip before the exposure of the four different turns is used. A method for manufacturing a semiconductor device. (3) The method of manufacturing a semiconductor device according to claim 1, wherein a pattern formed by etching after exposure of the different pattern is used as the nine turns indicating the exposure position.