JPS6247119A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS6247119A
JPS6247119A JP60187865A JP18786585A JPS6247119A JP S6247119 A JPS6247119 A JP S6247119A JP 60187865 A JP60187865 A JP 60187865A JP 18786585 A JP18786585 A JP 18786585A JP S6247119 A JPS6247119 A JP S6247119A
Authority
JP
Japan
Prior art keywords
layer
crystal
substrate
grown
lpe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60187865A
Other languages
Japanese (ja)
Inventor
Nobuyuki Takagi
高木 信行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60187865A priority Critical patent/JPS6247119A/en
Publication of JPS6247119A publication Critical patent/JPS6247119A/en
Pending legal-status Critical Current

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  • Led Devices (AREA)
  • Light Receiving Elements (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To grow a crystalline layer parallel to a true crystal surface on a crystal substrate even if the crystal surface is displaced by growing a crystal layer on the substrate formed with a projection on the surface, and forming an element on the layer which includes a region on the projection. CONSTITUTION:A projection 2 is formed on a crystal substrate 1 such as an InP substrate. Then, an n-type InP layer 31 as a buffer layer, an n-type In1-xGaxAs layer 32 as a photoreceiving layer and an n-type InP layer 33 as a multiplying layer are sequentially grown by the first liquid-phase epitaxial growth LPE on the substrate 1. In this case, the surfaces of the respective grown layers become parallel to the true crystal surface. Then, a projection is formed on the layer 33. Then, an n<-> type InP layer 34 is grown as guard ring region layer over the projection by the second LPE. In this case, the surface of the layer grown by the first LPE and the surface of the layer grown by the second LPE become in parallel. Then, a P-type region 35 is formed to arrive at the layer 33 by the surface. A photoreceiving device thus formed as above has a region 35 necessary to form a photoreceptor in parallel at the front with the photoreceiving layer, thereby uniformizing the sensitivity distribution in the plane.

Description

【発明の詳細な説明】 〔概要〕 結晶基板の表面が真の面指数から多少ズしているため、
この上に成長した結晶層に形成された素子は素子特性が
悪い。その対策として基板に段差をつけることにより結
晶層を真の結晶面に平行に成長させ、ここに素子形成を
行う。
[Detailed Description of the Invention] [Summary] Since the surface of the crystal substrate deviates somewhat from the true plane index,
A device formed on a crystal layer grown on top of this has poor device characteristics. As a countermeasure, a crystal layer is grown parallel to the true crystal plane by forming a step on the substrate, and an element is formed here.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置、特に受発光素子の特性を向上させ
る製造方法に関する。
The present invention relates to a semiconductor device, and particularly to a manufacturing method for improving the characteristics of a light receiving/emitting element.

現在、混晶結晶で形成される半導体装置は高速集積回路
や、受発光素子等の光半導体装置に多用されている。
Currently, semiconductor devices formed of mixed crystals are widely used in high-speed integrated circuits and optical semiconductor devices such as light receiving and emitting elements.

このような半導体装置は、混晶よりなる結晶基板上に液
相エピタキシャル成長(LPIIりにより複数層よりな
る結晶層を成長して、ここに種々の素子を形成している
In such a semiconductor device, various elements are formed by growing a plurality of crystal layers on a crystal substrate made of a mixed crystal by liquid phase epitaxial growth (LPII).

この場合、結晶基板はスライス、ミラー加工等により作
成されるため、面指数は真の面より良くて±0.1°程
度ズしてしまう。このような基板上にLPEを行うと、
テラス模様のギザギザの表面をもつ結晶層が成長したり
、あるいは受光素子形成時のように第2のLPEで成長
した結晶層に凸部を形成して、その上に第2のLPEを
行うと結晶層表面がズしてしまうという障害を生じ、対
策が望まれている。
In this case, since the crystal substrate is created by slicing, mirror processing, etc., the plane index deviates from the true plane by about ±0.1° at most. When LPE is performed on such a substrate,
If a crystal layer with a jagged surface in a terrace pattern grows, or if a convex part is formed on the crystal layer grown by a second LPE and a second LPE is performed on it, as in the case of forming a light receiving element, A problem arises in that the surface of the crystal layer is distorted, and countermeasures are desired.

〔従来の技術〕[Conventional technology]

第2図(11〜(5)は従来例による受光素子の製造方
法を工程順に説明する断面図である。
FIGS. 2(11 to 5) are cross-sectional views illustrating a conventional method for manufacturing a light receiving element in the order of steps.

第2図(11において、21は結晶基板で、例えばイン
ジウム燐(InP)基板で、点線は真の結晶面、例えば
(100) 、あるいは(111)A面を示す。
In FIG. 2 (11), 21 is a crystal substrate, for example an indium phosphide (InP) substrate, and the dotted line indicates a true crystal plane, for example (100) or (111) A plane.

図では、真の結晶面の傾きを拡大してあられしている。In the figure, the true tilt of the crystal plane is enlarged.

第2図(2)において、1回目のLPHにより、バッフ
ァ層としてn型1nP (n−1nP)層231、受光
層としてn型インジウムガリウム砒素(n−In+−イ
GaえAs)層232、増倍層としてn−1nP層23
3を基板上に順次成長する。
In FIG. 2 (2), the first LPH results in an n-type 1nP (n-1nP) layer 231 as a buffer layer, an n-type indium gallium arsenide (n-In+-GaAs) layer 232 as a light-receiving layer, and an n-1nP layer 23 as double layer
3 are sequentially grown on the substrate.

この場合、各成長層の表面はテラス模様を発生するが、
面全体としては基板と平行になる。
In this case, the surface of each growth layer develops a terrace pattern;
The entire surface is parallel to the substrate.

第2図(3)において、受光領域のn−InP層233
に、メサエッチングにより凸部を形成する。
In FIG. 2(3), the n-InP layer 233 in the light receiving area
Then, a convex portion is formed by mesa etching.

第2図(4)において、2回目のLPHにより、前記凸
部を覆ってガードリング領域層としてn−InP層23
4を成長する。
In FIG. 2(4), by the second LPH, an n-InP layer 23 is formed as a guard ring region layer covering the convex portion.
Grow 4.

この場合、基板上に凸部を有するため、成長は真の結晶
面に垂直方向に行われ、1回目のLPEで成長させた層
の表面と2回目のLPEで成長させた層の表面が平行に
ならない。
In this case, since the substrate has a convex portion, growth is performed perpendicular to the true crystal plane, and the surface of the layer grown in the first LPE is parallel to the surface of the layer grown in the second LPE. do not become.

第2図(5)において、受光領域に表面より増倍層のn
−1nP層233に届くように亜鉛(Zn)を拡散して
p型頭域235を形成する。
In Fig. 2 (5), the n
Zinc (Zn) is diffused so as to reach the -1nP layer 233 to form a p-type head region 235.

以上で受光素子の要部の形成を終わり、この後電極を通
常の工程により形成する。
This completes the formation of the main parts of the light-receiving element, and then electrodes are formed by normal steps.

以」二のように、埋め込み型受光装置は平坦な基板上に
受光層、増倍層を含む多層を1回目のLPEで成長し、
表面に凸部を設けてその上にガードリング領域層を2回
目のLPEで成長させて作成している。この際、基板が
真の結晶面からズしていると1回目のLPEで成長させ
た層の表面と2回目のLPEで成長させた層の表面が平
行にならないため、受光素子を完成させるに必要なZn
拡散のフロントが受光層と平行にならず、面内感度分布
が不均一になりやすい。
As described in Part 2, an embedded photodetector is produced by growing multiple layers including a photodetection layer and a multiplication layer on a flat substrate in the first LPE.
A convex portion is provided on the surface, and a guard ring region layer is grown on the convex portion in a second LPE. At this time, if the substrate is deviated from the true crystal plane, the surface of the layer grown in the first LPE and the surface of the layer grown in the second LPE will not be parallel, making it difficult to complete the photodetector. Necessary Zn
The diffusion front is not parallel to the light-receiving layer, and the in-plane sensitivity distribution tends to be uneven.

第4図(11、(2)は従来例による発光素子の製造方
法を工程順に説明する断面図である。
FIGS. 4(11 and 2) are cross-sectional views illustrating a conventional method for manufacturing a light emitting device in the order of steps.

第4図(1)において、41は結晶基板で、例えばIn
P基板で、点線は真の結晶面、例えば(100)面を示
す。
In FIG. 4(1), 41 is a crystal substrate, for example, an In
For P substrates, the dotted line indicates the true crystal plane, for example the (100) plane.

第4図(2)において、LPEにより、クラッド層とし
てn−1nP層431、活性層としてインジウムガリウ
ム砒素燐(In+−xGaJs+−yPy)層432、
クラッド層としてp7InP層433を基板上に順次成
長する。
In FIG. 4(2), an n-1nP layer 431 is formed as a cladding layer, an indium gallium arsenide phosphorus (In+-xGaJs+-yPy) layer 432 is formed as an active layer, and
A p7InP layer 433 is sequentially grown on the substrate as a cladding layer.

以上で発光素子の要部の形成を終わり、この後紙面に平
行な面でへき関し、電極を通常の工程により形成する。
This completes the formation of the main parts of the light emitting element, after which it is separated in a plane parallel to the plane of the paper, and electrodes are formed by a normal process.

この場合、各成長層の表面はテラス模様を発生するが、
面全体としては基板と平行になる。活性層432のテラ
ス模様の谷には不純物の析出が起こり、最適不純物濃度
よりズして発光効率は落ち、発光が不均一になりやすい
In this case, the surface of each growth layer develops a terrace pattern;
The entire surface is parallel to the substrate. Impurities are precipitated in the valleys of the terrace pattern of the active layer 432, and as the impurity concentration deviates from the optimum impurity concentration, the luminous efficiency decreases and luminescence tends to become non-uniform.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

結晶基板の結晶面ズレにより、成長層にテラス模様が発
生し、′発光効率を低下させる。またメサエッチングを
はさんで2回成長する受光素子形成の場合は、それぞれ
の成長層の表面は平行にならないため受光感度が不均一
になる。
Due to the misalignment of the crystal plane of the crystal substrate, a terrace pattern occurs in the grown layer, reducing the luminous efficiency. Furthermore, in the case of forming a light-receiving element that is grown twice with mesa etching in between, the surfaces of the respective grown layers are not parallel, resulting in non-uniform light-receiving sensitivity.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点の解決は、表面に凸部(2)を設けた結晶基
板(1)上に結晶層(3)を成長し、該凸部(2)上の
領域を含んだ該結晶層(3)に素子を形成する本発明に
よる半導体装置の製造方法により達成される。
The above problem can be solved by growing a crystal layer (3) on a crystal substrate (1) having a convex portion (2) on its surface, and growing the crystal layer (3) including the region above the convex portion (2). ) is achieved by the method of manufacturing a semiconductor device according to the present invention.

前記素子が発受光素子である場合は特に効果がある。This is particularly effective when the element is a light emitting/receiving element.

〔作用〕 第5図は段差を有する基板上にLPEを行った場合の状
態を示す断面図である。
[Operation] FIG. 5 is a sectional view showing a state when LPE is performed on a substrate having a step.

、図において、第2図(4)で既に触れたように、基板
上に段差があると点線で示されたように最下層の真の面
上にまず成長して、その成長は段差で停止し、つぎに2
番目に低い層上に成長して、その成長は段差で停止し、
以下順次同様の成長を繰り返して真の面に垂直な方向に
成長が進む。
In the figure, as already mentioned in Figure 2 (4), if there is a step on the substrate, growth will first occur on the true surface of the bottom layer as shown by the dotted line, and the growth will stop at the step. and then 2
It grows on the lowest layer, and its growth stops at a step.
Thereafter, similar growth is repeated one after another, and growth progresses in the direction perpendicular to the true plane.

図において、Sは実際に得られた成長層の表面を示す。In the figure, S indicates the surface of the grown layer actually obtained.

本発明は、このようにして得られた成長層に素子を形成
して、素子特性の向上をはかるものである。
The present invention aims to improve device characteristics by forming an element on the growth layer thus obtained.

〔実施例〕〔Example〕

第1図(1)〜(5)は本発明による受光素子の製造方
法を工程順に説明する断面図である。
FIGS. 1(1) to 1(5) are cross-sectional views illustrating the method for manufacturing a light receiving element according to the present invention in the order of steps.

第1図(1)において、lは結晶基板で、例えばInP
基板で、点線は真の結晶面、例えば(100)、あるい
は(111)A面を示す。
In FIG. 1 (1), l is a crystal substrate, for example InP
In the substrate, the dotted line indicates the true crystal plane, such as the (100) or (111) A plane.

通常のフォトプロセスにより基板上に凸部2を形成する
Convex portions 2 are formed on the substrate by a normal photo process.

第1図(2)において、1回目のLPHにより、バッフ
ァ層としてキャリア濃度1〜2X10”、厚さ約3μm
のn−1nP層31、受光層としてキャリア濃度3〜1
0×1015、厚さ約2μmのn−In+−8GaXA
s層32、増倍層としてキャリア濃度1〜2 X 10
”、厚さ約3μmのn−TnP層33を基板上に順次成
長する。
In FIG. 1 (2), the buffer layer has a carrier concentration of 1 to 2×10” and a thickness of approximately 3 μm by the first LPH.
n-1nP layer 31 with a carrier concentration of 3 to 1 as a light-receiving layer.
0x1015, about 2μm thick n-In+-8GaXA
S layer 32, carrier concentration 1 to 2 x 10 as a multiplication layer
”, an n-TnP layer 33 with a thickness of about 3 μm is sequentially grown on the substrate.

この場合、各成長層の表面は真の結晶面に平行になる。In this case, the surface of each grown layer is parallel to the true crystal plane.

第1図(3)において、受光領域のn−1nP層33に
、メサエッチングにより直径約100μmφの凸部を形
成する。
In FIG. 1(3), a convex portion having a diameter of about 100 μmφ is formed in the n-1nP layer 33 in the light receiving region by mesa etching.

第1図(4)において、2回目のLPHにより、前記凸
部を覆ってガードリング領域層としてキャリア濃度0.
1〜8X1015、厚さ約3μmのn−InP層34を
成長する。
In FIG. 1(4), the second LPH is performed to cover the convex portion and form a guard ring region layer with a carrier concentration of 0.
An n-InP layer 34 having a size of 1 to 8×10 15 and a thickness of about 3 μm is grown.

この場合の成長も真の結晶面に垂直方向に行われ、1回
目のLPEで成長させた層の表面と2回目のLPEで成
長させた層の表面は平行になる。
Growth in this case is also performed in a direction perpendicular to the true crystal plane, and the surface of the layer grown in the first LPE is parallel to the surface of the layer grown in the second LPE.

第1図(5)において、受光領域に表面より増倍層のn
−1nP層33に届くようにZnを拡散してp型頭域3
5を形成する。
In Figure 1 (5), the n
−1 Diffuse Zn to reach the nP layer 33 to form the p-type head region 3
form 5.

結晶層3はそれぞれの成長層31〜34よりなり、ここ
に素子が形成されている。
The crystal layer 3 consists of growth layers 31 to 34, in which elements are formed.

以上で受光素子の要部の形成を終わり、この後電極を通
常の工程により形成する。
This completes the formation of the main parts of the light-receiving element, and then electrodes are formed by normal steps.

以上のように形成された埋め込み型受光装置は、基板が
真の結晶面からズしていても、1回目のLPEで成長さ
せた層の表面と2回目のLPEで成長させた層の表面が
平行になり、受光素子を完成させるに必要なZn拡散の
フロントが受光層と平行になり、面内感度分布が均一と
なる。
In the embedded photodetector formed as described above, even if the substrate is deviated from the true crystal plane, the surface of the layer grown in the first LPE and the surface of the layer grown in the second LPE are The Zn diffusion front required to complete the light receiving element becomes parallel to the light receiving layer, and the in-plane sensitivity distribution becomes uniform.

第3図(1)、(2)は本発明による発光素子の製造方
法を工程順に説明する断面図である。
FIGS. 3(1) and 3(2) are cross-sectional views illustrating the method for manufacturing a light emitting device according to the present invention in the order of steps.

第3図(1)において、1は結晶基板で、例えばInP
基板で、点線は真の結晶面、例えば(100)面を示す
In FIG. 3 (1), 1 is a crystal substrate, for example InP
On the substrate, the dotted line indicates the true crystal plane, for example the (100) plane.

通常のフォトプロセスにより基板上に凸部2を形成する
Convex portions 2 are formed on the substrate by a normal photo process.

第3図(2)において、LPHにより、クラッド層とし
てn−1nP層36、活性層として In+−)I GaJS+−yPy層37、クラッド層
としてp−1nP層38を基板上に順次成長する。
In FIG. 3(2), an n-1nP layer 36 as a cladding layer, an In+-)I GaJS+-yPy layer 37 as an active layer, and a p-1nP layer 38 as a cladding layer are successively grown on the substrate by LPH.

この場合、結晶層3はそれぞれの成長層36〜38より
なり、ここに素子が形成されている。
In this case, the crystal layer 3 consists of the respective growth layers 36 to 38, in which the elements are formed.

以上で発光素子の要部の形成を終わり、この後紙面に平
行な面でへき関し、電極を通常の工程により形成する。
This completes the formation of the main parts of the light emitting element, after which it is separated in a plane parallel to the plane of the paper, and electrodes are formed by a normal process.

この場合、各成長層の表面はテラス模様を発生すること
なく、従って活性層32には不純物が析出しないため、
発光の不均一を無くすることができる。
In this case, the surface of each growth layer does not have a terrace pattern, and therefore no impurities are deposited in the active layer 32.
Non-uniformity of light emission can be eliminated.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように本発明によれば、結晶基板に
結晶面のズレがあっても、真の結晶面に平行に結晶層を
成長でき、この結晶層に素子を形成することにより素子
特性を向上させることができる。
As explained in detail above, according to the present invention, even if there is a misalignment of crystal planes on a crystal substrate, a crystal layer can be grown parallel to the true crystal plane, and by forming an element on this crystal layer, the element characteristics can be improved. can be improved.

例えば、発光素子においては結晶層にテラス模様の発生
を抑制し、発光の不均一を無くすことができる。また受
光素子においては接合面と受光層を平行に形成でき、面
内感度分布を均一にすることができる。
For example, in a light emitting device, the formation of a terrace pattern in a crystal layer can be suppressed, and non-uniformity in light emission can be eliminated. Furthermore, in the light receiving element, the bonding surface and the light receiving layer can be formed in parallel, and the in-plane sensitivity distribution can be made uniform.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(1)〜(5)は本発明による受光素子の製造方
法を工程順に説明する断面図、 第2図(1)〜(5)は従来例による受光素子の製造方
法を工程順に説明する断面図、 第3図(1)、(2)は本発明による発光素子の製造方
法を工程順に説明する断面図、 第4図(1)、(2)は従来例による発光素子の製造方
法を工程順に説明する断面図、 第5図は段差を有する基板上にLPEを行った場合の状
態を示す断面図である。 図において、 1は結晶基板で、例えばInP基板、 2は凸部、 3は結晶層、 31はバッファ層で1−InpJW1 32は受光層でn−1nl−XGaXAs層、33は増
倍層でn−TnP層、 34はガードリング領域層でn−lnP層、35はp型
領域、 36はクラッド層でn−InP層、 37は活性層でInk−XGaJS+−yPv層、I N大− 〇〜) \ j (1)[121、InF 揉未骨1.f1唾光+羊勇断面図 第2 図 木りoR,)全り東!υ断面図 揺3図 (1)ロ]=コ柑IIルP
FIGS. 1 (1) to (5) are cross-sectional views explaining the method for manufacturing a light receiving element according to the present invention in the order of steps, and FIGS. 2 (1) to (5) show the method for manufacturing a light receiving element according to the conventional example in the order of steps. 3(1) and (2) are cross-sectional views illustrating the method for manufacturing a light emitting device according to the present invention step by step, and FIGS. 4(1) and (2) are a method for manufacturing a light emitting device according to a conventional example. FIG. 5 is a cross-sectional view showing a state when LPE is performed on a substrate having a step. In the figure, 1 is a crystal substrate, for example an InP substrate, 2 is a convex portion, 3 is a crystal layer, 31 is a buffer layer, 1-InpJW1, 32 is a light-receiving layer, an n-1nl-XGaXAs layer, and 33 is a multiplication layer, n -TnP layer, 34 is a guard ring region layer, n-lnP layer, 35 is a p-type region, 36 is a cladding layer, n-InP layer, 37 is an active layer, Ink-XGaJS+-yPv layer, IN large- 〇~ ) \ j (1) [121, InF 扉美bone 1. f1 spitting light + Hitsujiyu cross section 2nd figure tree oR,) All east! υ Cross-sectional diagram Figure 3 (1) B] = Kokan II P

Claims (3)

【特許請求の範囲】[Claims] (1)表面に凸部(2)を設けた結晶基板(1)上に結
晶層(3)を成長し、該凸部(2)上の領域を含んだ該
結晶層(3)に素子を形成することを特徴とする半導体
装置の製造方法。
(1) A crystal layer (3) is grown on a crystal substrate (1) having a convex portion (2) on its surface, and an element is attached to the crystal layer (3) including the region above the convex portion (2). 1. A method of manufacturing a semiconductor device, characterized by forming a semiconductor device.
(2)前記素子が受光素子であることを特徴とする特許
請求の範囲第1項記載の半導体装置の製造方法。
(2) The method of manufacturing a semiconductor device according to claim 1, wherein the element is a light receiving element.
(3)前記素子が発光素子であることを特徴とする特許
請求の範囲第1項記載の半導体装置の製造方法。
(3) The method for manufacturing a semiconductor device according to claim 1, wherein the element is a light emitting element.
JP60187865A 1985-08-27 1985-08-27 Manufacture of semiconductor device Pending JPS6247119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60187865A JPS6247119A (en) 1985-08-27 1985-08-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60187865A JPS6247119A (en) 1985-08-27 1985-08-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6247119A true JPS6247119A (en) 1987-02-28

Family

ID=16213566

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60187865A Pending JPS6247119A (en) 1985-08-27 1985-08-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6247119A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6422072A (en) * 1987-07-17 1989-01-25 Nec Corp Manufacture of pin type semiconductor photodetector
JPH01140780A (en) * 1987-11-27 1989-06-01 Hikari Gijutsu Kenkyu Kaihatsu Kk Semiconductor photodetector

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6422072A (en) * 1987-07-17 1989-01-25 Nec Corp Manufacture of pin type semiconductor photodetector
JPH01140780A (en) * 1987-11-27 1989-06-01 Hikari Gijutsu Kenkyu Kaihatsu Kk Semiconductor photodetector

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