JPS6246951U - - Google Patents

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Publication number
JPS6246951U
JPS6246951U JP13847885U JP13847885U JPS6246951U JP S6246951 U JPS6246951 U JP S6246951U JP 13847885 U JP13847885 U JP 13847885U JP 13847885 U JP13847885 U JP 13847885U JP S6246951 U JPS6246951 U JP S6246951U
Authority
JP
Japan
Prior art keywords
count value
counter
test program
timer
operating switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13847885U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13847885U priority Critical patent/JPS6246951U/ja
Publication of JPS6246951U publication Critical patent/JPS6246951U/ja
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係るセルフテストプログラム
の起動回路の一実施例の構成図、第2図は第1図
のタイマの動作説明用のタイムチヤート、第3図
は第1図の回路の動作説明図、第4図は本考案に
係るセルフテストプログラムの起動回路の他の実
施例の構成図である。 1……操作スイツチ、4……カウンタ、5……
タイマ、6……I/Oインタフエイス。
FIG. 1 is a configuration diagram of an embodiment of a self-test program startup circuit according to the present invention, FIG. 2 is a time chart for explaining the operation of the timer in FIG. 1, and FIG. 3 is an operation of the circuit in FIG. 1. The explanatory diagram, FIG. 4, is a configuration diagram of another embodiment of the self-test program starting circuit according to the present invention. 1...Operation switch, 4...Counter, 5...
Timer, 6...I/O interface.

Claims (1)

【実用新案登録請求の範囲】 操作スイツチのオン・オフ操作の回数をカウン
トするカウンタと、 前記操作スイツチの操作の度に駆動され、操作
後一定時間が経過したところでタイムアウト信号
を出力するリトリガブルなタイマと、 前記カウンタのカウント値とタイマの出力を監
視し、タイムアウト信号が発生した直後のカウン
ト値を読み取り、このカウント値に対応したセル
フテストプログラムを実行させるI/Oインタフ
エイス、 とを具備したセルフテストプログラムの起動回路
[Scope of Claim for Utility Model Registration] A counter that counts the number of on/off operations of the operating switch, and a retriggerable timer that is driven each time the operating switch is operated and outputs a timeout signal after a certain period of time has passed after the operation. and an I/O interface that monitors the count value of the counter and the output of the timer, reads the count value immediately after the timeout signal is generated, and executes a self-test program corresponding to this count value. Test program startup circuit.
JP13847885U 1985-09-10 1985-09-10 Pending JPS6246951U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13847885U JPS6246951U (en) 1985-09-10 1985-09-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13847885U JPS6246951U (en) 1985-09-10 1985-09-10

Publications (1)

Publication Number Publication Date
JPS6246951U true JPS6246951U (en) 1987-03-23

Family

ID=31043497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13847885U Pending JPS6246951U (en) 1985-09-10 1985-09-10

Country Status (1)

Country Link
JP (1) JPS6246951U (en)

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