JPS6246490A - Refresh control system for dynamic memory - Google Patents

Abstract

PURPOSE:To reduce a time required for refreshing and a consumed current of a system during refreshing by dividing a memory into plural blocks and performing the refresh operation every different time. CONSTITUTION:When a CPU does not select either of memory blocks 2, 9, refresh addresses 117, 118 are formed in counters 3, 8 by clock signals 115, 116 situated at positions separated for a fixed period since the blocks 2, 9 are not directly connected to an external part and the refresh addresses are given to the blocks 2, 9 through selectors 1, 7. Separate refresh operations are performed every fixed period to the blockse 2, 9 by memory activating signals 109, 110 generated through a control circuit 6 by control signals 113, 114 generated every fixed period.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] 1 The present invention relates to a dynamic memory refresh operation, and particularly relates to a method for distributing current consumption during refresh.

□ [Prior Art] Since the internal cells and peripheral circuits of a dynamic memory are composed of dynamic circuits, the dynamic memory must be recharged before the accumulated charge falls below a threshold value. That is, a refresh operation is required. For this reason, the memory row (RO) is
W) A method is used in which all address signals are selected and a refresh operation is performed.

[Problem that the invention seeks to solve]

As described above, when using a dynamic memory, seven retrieval operations are required in addition to normal read and write operations.

Refreshing methods in memory systems using dynamic memory can be roughly divided into centralized refresh and distributed refresh, but distributed refresh is generally used from the point of view of CPU efficiency. In this distributed refresh, the refresh period is divided by the number of ROW addresses in the entire system, and the ROW addresses are sequentially selected for each time period to perform the refresh operation, and the other method is to divide the refresh period by the number of ROW addresses in the entire system and perform a refresh operation. There is a method in which the refresh period is divided by the number of ROW addresses in one block, and the RO and W addresses of each block are sequentially selected for each time period to perform the refresh operation.

In the distributed refresh described above, although the time spent on the refresh operation increases in proportion to the address space, the current consumption in the system due to the refresh operation is small. In the latter case, the time spent on refresh operations is gradually reduced, but since multiple blocks of memory are refreshed at the same time, the current consumption at this time also increases.

[Means for solving problems]

The purpose of the present invention is to reduce the time spent on refresh in the system and to reduce the current consumption in the system during refresh.The feature of this invention is that the memory of the entire system does not operate at the same time during refresh. The memory is divided into a plurality of blocks and has circuits that perform refresh operations at different times. [Embodiment] Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the distributed refresh control system of the present invention. In FIG. 1, ROW address i number 102, COL
OMN address signal 103, fresh address signals 117, 118, and signals 104°109.110't for controlling these three types of addresses,
Selectors 1 and 7 output these addresses, memory blocks 2 and 9 have N parallel memories, and refresh address signals 117 and 118 are counted sequentially from different clock signals 115 and 116 at regular intervals. Counters 3 and 8 that output control signals 113 and 114t, latch circuit 4 that outputs memory block switching data 104 according to a control command from the CPU, and control signals 113 and 1 that are generated at regular intervals for refreshing.
14 and the memory block switching data 104, the selector circuit 5 outputs the interrupt signal 105, the read signal 106°, the write-in signal 1079, the interrupt enable signal 108, and the memory block switching data 104t. The control circuit 6 outputs signals 109 and 110t for activation, reading and writing.

Next, the operation will be explained. First, if the CPU has not selected either memory block, memory block 2
, 9 are not directly connected to the outside, so for a certain period of time, counters 3 and 8 create refresh addresses 117.11E1 using clock signals 115 and 116 at different positions, and selectors 1.7t and 2.7t pass through memory blocks 2. 9 is given a refresh address tube, and memory activation signals 109 and 110 are generated through the control circuit 6 by control signals 113 and 114 that are generated at regular intervals. has been done.

Next, a case will be described in which either memory block is used by an I10 instruction or the like from the CPU.

I10 instruction from tfcPV
Nick switching data is output and relatched by the nt latch circuit 4 to determine which memory block is to be used. If memory block 2 is selected at this time, the HlRUW and COLUMN addresses are switched by the selector 1 by the signal 109 which gives the memory block switching data 104° read and write in the normal read/write operation from the CPU to the memory. )-eU2. .

72°. Yo, 1, jヮ　　　1 signal.

At this time, if the read signal 106 becomes active, the data signal 101 is output from the memory block 2.
If the write signal 107 is active, the data signal 101 is input to the memory. , to 2°□. □Ah.
1. Also, the refresh address for the refresh operation of the memory block 2 is generated by the counter 3, given by the selector 1, and given by the selector 5.
An interrupt signal 105 is generated for U.

When the control circuit 6 detects this later engraving permission signal 106, the memory activation signal 1091C causes the memory block 2 to be refreshed every one period. In this case, the other memory block 91'! , since it is not connected to the outside, the clock signal 1 is
16, refresh is executed at regular intervals.

〔Effect of the invention〕

As explained above, in the present invention, memory writing is performed.

By limiting reading to always-blocks, blocks that are accessing memory receive normal distributed refresh, and blocks that do not access memory receive distributed refresh at different times, independent of the cPU. By doing so, it is possible to prevent the memory of the entire system from being refreshed simultaneously, thereby reducing the current consumption during refreshing and reducing the time spent on refreshing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the refresh method of the present invention. 1.7...Selector circuit, 2,9...
Memory block composed of n pieces, 3, 8... Counter circuit, 4... Latch circuit, 5...
- Selector circuit, 6... Control circuit.

Claims (1)

[Claims] A dynamic memory consisting of n pieces is divided into a plurality of blocks, each block is provided with a refresh circuit that outputs a refresh address, and
A dynamic memory refresh control method characterized by refreshing each block at different times.