JP3237703B2 - Multiple timer control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multiplex timer control circuit according to the present invention.

[0002]

2. Description of the Related Art Communication control LSIs for data exchanges that accommodate and process thousands of logical lines on one physical communication line by frame multiplexing or packet multiplexing are three to four types per logical line, even for only the part related to timer processing. Since the number of channels of the timer (the number of timers) is enormous and the required memory amount is far beyond the scale that can be implemented on one chip, the communication control LSI Is configured using a static RAM outside.

[0003]

In order to incorporate such an external static RAM into an LSI, it is necessary to use a DR.
Since the AM must be used, it is necessary to incorporate a refresh operation unique to the DRAM and to prevent a decrease in throughput due to the refresh.

An object of the present invention is to provide a multiplex timer control circuit which does not substantially require a refresh operation for a communication control LSI including a multiplex timer.

[0005]

[Means for Solving the Problems]

According to the multiplex timer control circuit of the present invention, the storage area of the information required by each timer constituting the multiplex timer is distributed to the same column address in all the row addresses of the DRAM, and the count cycle is set to the DRAM. At the refresh cycle or less, the system clock signal is counted, a counter that outputs the row address and the column address of the entire DRAM area, and whether the column address of the counter matches the column address of the timer information storage area is detected. A timer address detection circuit that outputs an active selector switching signal when a match is detected, and a normal row address and a column address that are respectively selected when the selector switching signal is inactive, and the counter output when the selector switching signal becomes active. Row address,
It has a row decoder and a column selector for respectively selecting a column address and outputting to the row decoder, column decoder of the DRAM. The present invention provides a multiple timer
Is stored in a dynamic RAM (hereinafter DR)
Access is required periodically when configuring with AM)
The storage area of the timer control information to be
ー Distributed at regular intervals to address addresses
By accessing the DRAM, DRAM-specific resources are accessed.
No need for fresh operation.

[0007]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a DRA according to an embodiment of the present invention.
The memory allocation on M is shown. This memory allocation is based on information required by individual timers constituting the multiplex timer (details are not shown, for example, the activation / deactivation state of each timer is 1 bit per timer, and one word for a plurality of timers collectively). And used to control whether or not to execute the counting operation of the multiplex timer. For example, the timer value of each timer is set at the time of start-up, and is used as a calculation information recording area in a method of performing a calculation periodically). Is assigned to a specific in-row column of all row addresses.

At the time of normal access (read or write) of the DRAM, the entire specified row address is selected by inputting a row address, and then a column (ie, word) in the selected row is input by inputting a column address. ) Is performed, and it is known that a refresh equivalent operation is performed at the end. Therefore, if the access to the timer information storage area in FIG. 1 is positioned and executed as a part of the operation of the multiplex timer, the refresh of the DRAM is performed. This means that they can be used for both purposes.

FIG. 2 is a circuit diagram of a multiplex timer control circuit for accessing the timer information storage area of FIG. 1 as an embodiment of the present invention.

The counter 2 has a clock signal 2 of the system.
This is a counter that counts 0 synchronously.
1 is connected to the row selector 6 having the number of bits capable of displaying the total number of row addresses, and the lower order is connected to the column selector 7 and the timer address detection circuit 3 having the number of bits capable of displaying the total number of columns in one row address. The entire address information in the word direction of the entire DRAM area shown in FIG. 1 is supplied to the row selector 6 and the column selector 7 by making a complete circuit. The counting cycle of the counter 2 (0 to the time until the maximum value is counted = counter 2
The number of bits of the counter 2 is increased or decreased so that the number of bits × the number of clocks) is equal to or less than the refresh cycle of the DRAM 1.
Alternatively, it is assumed that the matching is performed by using a divided clock.

The timer address detection circuit 3 includes a counter 2
Is a circuit for detecting whether or not the lower bit information (column address) matches the column address in the timer information storage area of FIG. 1. When a match is detected, a selector switching signal 25 is output to the row selector 6 and the column selector 7. To output the output of the counter 2 to the DRAM 1, that is, instruct the DRAM 1 to access the timer information storage area. In addition,
When a mismatch is detected, the normal row input 23 and the normal column input 24 are input to the row selector 6 and the column selector 7, and the non-timer information storage area in FIG. 1 is selected.

The AND circuit 4 generates a clock indicating that the timer information storage area of FIG. 1 is being accessed, and the AND circuit 5 generates a clock indicating that the non-timer information storage area of FIG. 1 is being accessed. It is.

The internal structure of DRAM 1 shown in FIG. 2 is well known to those skilled in the art, and signal lines 23, 24, 2
The operations of the connection destinations 6 and 27 and the operation of the multiplex timer itself are not directly related to the present invention, and thus the detailed configuration is omitted.
Although the multiplex timer is not explicitly shown, the counter 2 and the timer address detection circuit 3 are included in the control part of the multiplex timer. The DRAM 1, the row selector 6, and the column selector 7 are positioned as a shared circuit for a multiplex timer and another device (for example, a processor in the case of a communication control device that performs protocol processing).

Next, the operation of this embodiment will be described.

The counter 2 sequentially outputs the word direction addresses on the DRAM 1 and repeats the operation of returning to 0 after counting the last address of the DRAM. When the counter 2 indicates the address of the timer information storage area, the input of the row selector 6 and the column selector 7 is output from the counter 2 by the timer address detection circuit 3 detecting a specific column address, that is, the input of the timer information storage area. Indicates the DRAM address, accesses information required by the multiplex timer, and refreshes the corresponding row address.

When the counter 2 indicates the address of the non-timer information storage area, the row selector 6 and the column selector 7 normally operate with the row input 23 and the normal row input because the timer address detection circuit 3 does not detect a specific column address. The column 24 is input, that is, an unspecified address indicated by a portion other than the multiplex timer is accessed, and the corresponding row address is refreshed.

When the counter 2 displays the specified column address of the row address 0 to the last row address in the process of counting the last address of the 0 to DRAM, the timer address detection circuit 3 detects and displays the row selector 6 and the column selector 7. To the counter 2 side and the DRAM
A refresh operation is performed after accessing the timer information storage area provided with at least one word in each row of
The operation similar to the distributed refresh of the DRAM 1 is performed while the count value of one rounds.

This operation is equivalent to the distributed refresh operation of the DRAM 1 and also serves to access the timer storage information storage area of the multiplex timer, so that the DRAM refresh operation is not required and the number of refresh-related elements in the hardware configuration can be reduced and reduced. The indirect effect of reducing power consumption due to the above, and the effect of improving the overall throughput by shortening the overall DRAM access time can be obtained.

[0020]

As described above, according to the present invention, the storage area of the multiplex timer information is distributed and arranged at equal intervals on the DRAM, and the multiplex timer side accesses the DRAM periodically and at a constant time interval, thereby distributing the DRAM. The same operation as refresh can be performed. As a result, the originally required DRAM refresh circuit is not required, and the effect of reducing the number of circuit elements and power consumption and the effect of improving the throughput by using both DRAM refresh and multiple timer access are achieved. is there.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a timer information storage area on a DRAM.

FIG. 2 is a circuit diagram of a multiplex timer control circuit.

[Explanation of symbols]

 Reference Signs List 1 DRAM 2 counter 3 timer address detection circuit 4, 5 AND circuit 6 row selector 7 column selector 11 row decoder 12 column decoder 13 memory array 20 system clock 21 upper bit output 22 lower bit output 23 normal row input 24 normal column input 25 selector Switching signal 26 Timer control clock 27 Non-timer control clock 28 Row selector output 29 Column selector output

Claims (2)

(57) [Claims] 1. A storage area for information required by individual timers constituting a multiplex timer is distributed to the same column address in all row addresses of a DRAM, and a count cycle is equal to or less than a refresh cycle of the DRAM. Counting the clock signal of the system;
A counter that outputs a row address and a column address of the entire area of M, and detects whether the column address of the counter matches the column address of the timer information storage area, and outputs an active selector switching signal when a match is detected. a timer address detection circuit, when the selector switching signal is inactive, normal row address, column address select respectively the previous SL <br/> selector switching signal is activated, a row address which is the output of the counter , A column address, and a multiplex timer control circuit having a row selector and a column selector which respectively output to the row decoder and the column decoder of the DRAM. 2. A first gate for inputting the system lock and the selector switching signal and outputting a clock indicating that the timer information storage area of the DRAM is being accessed when the selector switching signal is active. And a second gate circuit that inputs the system clock and the selector switching signal, and outputs a clock indicating that the non-timer information storage area of the DRAM is being accessed when the selector switching signal is inactive. further comprising multiplexing the timer control circuit of claim 1, wherein.