JPS6246488A - Controlling system for memory refreshing - Google Patents

Abstract

PURPOSE:To enhance the efficiency by memory access with a bus master and simplify circuit configuration by executing reading operation and hidden refreshing to a non-access memory in the state of bus separation. CONSTITUTION:Two bus masters, CPU A1, CPU B2, are provided, and the CPU A1 refreshes a common memory 5, and the CPU B2 refreshes a program memory 7 and a data memory 11. Memory controls 6, 10 operate as read access to a memroy controlled by the controls when the access is either read/write if the access is not access to a memory controlled by them, and separate the data bus of the memory controlled by them from the bus of the CPU B2. The memory 11 is refreshed by hidden refreshing accompanying access, and the memory 7 is refreshed by hidden refreshing accompanying dummy read. The memory 5 is refreshed by hidden refreshing that only accompanies access over the CPU A1.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a memory refresh control method, and in particular,
This invention relates to a memory refresh control method that has high access efficiency without competing with memory access.

[Background of the invention]

Dynamic memory (hereinafter referred to as DRAM) used as memory for microcomputers and the like requires periodic refreshing in order to retain its memory contents.

Intel's DR is the refresh control circuit method.
AM controller (hereinafter referred to as DRAMC) IC,i
The method adopted in 8203 is common. Detailed data on this IC is shown, for example, in the following document.

Intel Corporation [Microsystem Component Handbook Microprocessor & Peripheral Elements Volume 2 J
(Microsystem Components H
a-ndbook Microprocessors
and peripheralsvolumeI
) The 18203 has an internal timer for counting refresh cycles and a refresh/access conflict determination circuit, and refreshes the DRAM automatically at regular intervals. The bus master cannot access memory during this refresh operation.

Since the refresh operation is performed at a cycle of 12 μs to 16 μs, the access interval is 1 μs when the path master is busy.
If this is the case, when memory access is most frequent, the access efficiency will be reduced by 1/2 due to competition between memory access and refresh.
12-1-16 decrease. Furthermore, since it is a general-purpose LSI and has many functions, it is expensive. On the other hand, there is a drawback that the circuit scale becomes too large when assembled with discrete elements.

In order to prevent this decrease in access efficiency, a RAM capable of refreshing called hidden refresh has been announced. Hidden refresh is an attempt to eliminate the drop in access efficiency due to competition between memory access by the bus master and refresh by incorporating a refresh cycle into memory access by the path master.

However, if you perform a hidden refresh,
” contains “171/7'75”” (”)
・.

Therefore, the time required for memory access is longer, but
l□ Normal・l -E IJ (iD 71-k x time 1″
Mo/<2? Since the access interval between 2 p and 1 is longer, an increase in the access time 1: □ does not affect the access efficiency.
7. However, since hidden refresh refreshes the memory in conjunction with the path master's access, the memory must always be accessed by the bus master and has an independent memory block. ,yxf
"7 is used""'!""There is a problem 6.
1 [8”00 target]
: The purpose of the present invention is to improve the memory access efficiency of each path master and to develop an efficient riff v7-, y:s- control system that can simplify the circuit.
,.

The goal is to provide the following.

[Summary of the Invention] 1. When executing a program by the CPU, it is essential to retrieve the program from memory, and hidden refresh is performed in conjunction with memory access by the CPUK. Therefore, in the present invention, when one of the memories of a plurality of memory groups is being accessed, the path of the memory that is not being accessed is also disconnected.
We propose a method that refreshes all multiple memory groups without performing read operations and associated hidden refreshes.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4. FIG. 1 is a block diagram of this embodiment. In the figure, CPUAl and CPUB2 share a shared memory 5 via conflict determination 3 and shared memory control 411. C
The PUA 1 uses the shared memory 5 as a program area, and has input/output l10A8 and the like. The CPUB 2 has a program memory 7 as a program area and a program memory control 6 for it, a data memory 11 as a data area and a data memory control 10 for it, and input/output l.
10B9 etc. The shared memory is used as a program area for CPUA1, and also for CPUAl and C
It is also used to exchange data between PUB2. The DRAM used in this embodiment requires refreshing 256 times every 4 ms. ' Figure 2A and Figure 2B are diagrams showing memory access when normal memory access and hidden refresh are performed. The row address ■ is given at the falling edge of the signal, and the column address ■ is given at the falling edge of the column address strobe (CAS) signal.At this time,
For R and As signals, the RAS signal width is TR, and RA
If the S signal precharge width is tTp, the memory occupation time for one access is TC1=TR+TP.

On the other hand, in memory access for performing hidden refresh in Figure 2B, rotary address strobe (RAS)
) The rising edge of the signal gives the row address ■, the falling column address strobe (CAS) signal gives the column address ■, and while the CAs signal is at the low level, the RA
A refresh address (2) is given when the SAs signal is raised and then lowered again, and refresh is performed while reading data from the memory. However, at this time, the RAS signal width and RAS signal precharge time are required to be the same as in the case of FIG. 2A, so the memory occupation time for one access is TC2=TR+TP+TR+Tp''2Tcl.This embodiment In this case, by using a DRAM with a built-in refresh address counter, address switching is simplified by using only the lower address and column address.

Figure 3A shows refresh in the 18203, etc., where a refresh request to the memory is issued approximately every 12 μs, and when the refresh request and the memory access request by the bus master overlap, an access delay time Td for the bus master's memory access occurs, resulting in an access Reduce efficiency.

In contrast, in this embodiment, the relationship between the memory access interval TAC by the bus master and the memory occupation time TA is
As shown in FIG. B, since the system is configured so that TAC>TA', memory access efficiency does not decrease even if the memory occupation time of the bus master increases due to frequent refresh.

As mentioned earlier, the DRAM used in this example is 4
It requires 256 refreshes per ms. 5820
3 uses a built-in timer to manage time and ensure refresh conditions, but in this embodiment, the memory must be stored in conjunction with the bus master's memory access, and the CPU is prohibited from being in a halt state (stopped state).

This embodiment has two bus masters, CPUAl and CPUB2. The shared memory is refreshed by CPUAl, and the program memory and data memory are refreshed by CPUB2.

When CPUB 2 accesses memory, an access request is always made to program memory 7 or data memory 11 via program memory control 6 or data memory control 11. Each memory control has accesses that are not accesses to the memory it controls.
Whether the access is a read access or a write access, it operates as a read access to the memory it controls, and is further isolated from the data, JPA, and '4-CPUB2 buses of the memory it controls. (The memory is read in a dummy manner.) In this way, when a program is fetched, the program memory 7 is refreshed with a quick refresh that accompanies the memory access, and the data memory 11 is refreshed with a quick refresh that accompanies a dummy read. At the time of data memory access, the data memory 11 is refreshed with a quick refresh that accompanies the memory access, and the program memory 7 is refreshed with a quick refresh that accompanies a dummy read. When the shared memory 5 is accessed, both the program memory and the data memory are refreshed by a quick refresh that accompanies a dummy read.

Shared memory 5 is refreshed by hidden refresh only when CPUA1 accesses it, and CPUB2
This access is not accompanied by Hitokun Refresh.

FIG. 4 is an explanatory diagram showing the waiting time of each CPU when accesses to the shared memory between CPUAl and CPUB2 conflict. FIG. 4A shows CPU1. CPUB
4B shows a case where a quick refresh is performed only in the case of a memory access by CPUA1.

The memory access time is T. , refresh time? T
-t, the CPU when memory access by both CPUAl and CPUB2 involves hidden refresh.
Al, CPUB2 memory occupation time T-, Ta Fi
, both become (T-+T, t).

On the other hand, if hidden refresh is performed only in the case of CPUAl's memory access, then
The memory occupation time Th of l is (T,, +T1.), CPU
The memory occupation time TI of B2 becomes Tae and CPUB
The memory occupation time of 2 is short, and as a result, CPUAl
The waiting time of CPUA1 when accesses to the shared memory of CPUB2 and CPUB2 conflict is reduced. Since the CPUB2 is used for exchanging data with the shared memory 1J5t-cPUAl and has separate program memory and data memory, contention between CPUAl and CPUB2 in accessing the shared memory 5 can be minimized.

According to this embodiment, there is no need for a memory refresh/memory access conflict determination circuit and a refresh cycle counting timer, and the circuit is simplified.

Furthermore, since there is no competition between memory access and memory refresh, access efficiency is improved.

During shared memory access contention between CPUAl and CPUB2, the memory occupation time of CPUB2 is shortened, so CPU
The access efficiency of UAl is improved.

Further, by using the shared memory 4 seen from the CPUB2 for data exchange, the occurrence of shared memory access conflict between the CPUA1 and CPUB2 can be limited to only when data is exchanged. Furthermore, the shared memory 5 seen from the CPUAl can be used as a program memory and a memory for data exchange, so that the memory blocks can be integrated and the circuit can be simplified.

〔Effect of the invention〕

According to the present invention, it is possible to obtain an efficient memory refresh control method that can completely improve memory access efficiency by a bus master and simplify the circuit. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention; FIG. 2 is an explanatory diagram showing normal memory access; FIG. 2B is an explanatory diagram showing memory access when hidden refresh is performed; Figure 3 Memo on i8203 etc.+717
An explanatory diagram showing the access state when refreshing is performed,
Figure 3B is an explanatory diagram showing the access state when a hidden refresh is performed.
jJ who performed a hidden refresh of the shared memory of both parties in 2.
FIG. 4B is an explanatory diagram showing the access state of CPUA1.
FIG. 4 is an explanatory diagram showing an access state when only one user performs a hidden refresh of the shared memory. 1... CPUA, 2... CPUB, 3... Conflict determination, 4... Memory control, 5... Shared memory, 6...
・Program memory control, 7...Program memory,
8...l10A, 9...l10B, 10...data memory control, 11...data memory.

Claims (1)

[Claims] 1. In a microcomputer system equipped with a memory that requires refreshing, the memory is used as a memory that is constantly accessed by a bus master, and the refresh of the memory is made incidental to the bus master's access to the memory. A memory refresh control method characterized by a hidden refresh. 2. In a microcomputer system equipped with multiple memory groups that require refreshing, the memory selected by the bus master's memory access performs the read or write operation specified by that access and the accompanying hidden refresh. A memory refresh control system characterized in that unselected memory groups perform read operations while being separated from a data bus, and each memory performs a hidden refresh.