KR0145091B1 - Memory interface circuit - Google Patents

Abstract

The present invention relates to a memory access means in a computer system. In the related art, an interface for accessing a DRAM or an SRAM is provided in such a system. However, when using a memory such as Epyrom, a separate interface is not provided. As a result, there is a problem in that a PCI bus or an ISA bus must be used, and it is difficult to avoid the problem that the processing efficiency of the system is reduced.

The present invention is connected between the sipe oil 21 and a predetermined memory 22 that does not have a separate interface so as to improve the problems of the conventional art, and by using a DRAM control signal of the system sipe oil 21, a predetermined memory ( 22) a memory interface circuit comprising a memory access logic section (1) for generating a RAS * (Row Address Strode) signal, a CAS * (Column Address Strode), an address signal, and the like, for accessing To provide.

Description

Memory interface circuit

1 is an embodiment of a memory interface circuit according to the present invention

2 is a timing chart associated with FIG.

* Explanation of symbols for main parts of the drawings

1: Memory access logic section 11, 12: Address register

13: gate logic

The present invention relates to a memory system of a computer system and an interface means of the peripheral device, which is particularly limited to the memory interface (DRAM) and backup cache SRAM (CPU) of the system CPU (CPU) The present invention relates to a memory interface circuit that allows access to other types of memory or peripherals using signals for DRAM interface purposes, if any.

In the conventional case, when the system SPI is incorporating a memory controller and an I / O controller, the DRAM or SRAM interface is handled by the memory controller, and in the case of the I / O controller, the interface of the ISA bus or the PCI bus is mainstream. there was.

In this way, SIFIU can be used for all other types of memory except DRAM and SRAM, such as Flash Memory, EPROM, EEPROM and NVRAM. It has been used to either snap directly to the bus in charge, or attach it to a sub-bus subordinate to the bus under the I / O controller.

For example, the 21068 microprocessor of Digital Equipment's Alpha series of SI fluids contains a memory interface controller and a PCI I / O controller in addition to the SI fluid core. Cache SRAM interface signals were driven directly by Scipil, but other types of memory, I / O controllers, and peripherals would be located on the PCI bus or on the ISA bus below the PCI bus.

However, this conventional technique has the disadvantage of increasing the inefficiency and delay time of accessing the memory by arbitration of the PCI bus arbitration circuit even if the CPU is accessed by itself when attaching the memory to the PCI bus. In the case of a master, the bus utilization opportunities are reduced, resulting in a decrease in the efficiency of the PCI bus as a whole.

In addition, the memory used exclusively for Sipeil uses mediation of the Sipeu bus or the ISA bus, which increases the memory access time, and in terms of the efficiency of the PCI bus or the ISA bus, there is an opportunity for other Masters except Sipeu to use the bus. This will limit the bus usage efficiency.

An object of the present invention is to improve the processing efficiency of such a system by allowing the system to access the memory directly without mediation of the PCI bus or ISA bus to improve the problems of the prior art as described above. One memory interface circuit is provided.

In particular, the present invention provides a CAS and a RAS * (Row Address Strode) signal which is connected between the system medium and a predetermined memory that does not have a separate interface to access the predetermined memory under the control of the system. And a memory interface circuit having a memory access logic section for generating (Column Address Strode), read (rd *) and write (wr *) signals, address signals, and the like.

Hereinafter, by referring to this in more detail with the accompanying drawings will be understood more specific features of the present invention.

That is, FIG. 1 shows a system circuit with a memory interface circuit according to the present invention.

Here, a RAS * (Row Address Strode) signal is connected between the system sipe 21 and a predetermined memory 22 having no separate interface to access the predetermined memory 22 under the control of the system sipe 21. And a memory access logic section 1 for generating a column address strode (CAS) and an address signal.

The memory access logic unit 1 stores the RAS * (Row Address Strode) signal and the CAS * (Column Address Strode), read (re *) and write (wr *) signals in the system. (574) series) and the gate logic 13 for driving to the memory 22 side, and the address registers 11 and 12 connected to the inputs of the output of the gate logic 13 and the address port of the CP 21 as inputs. ), The gate logic 13 forms a combination circuit of an or gate 0, end gates A1 and A2, and inverters I1 and I2.

The present invention of such a configuration is as follows.

That is, the memory access logic unit 1 of the memory interface circuit according to the present invention may access all memories except DRAM or SRAM by using signals provided by a memory controller embedded in the system medium 21.

In this case, the system uses 12 addresses, RAS * signals, and CAS * signals provided for the DRAM interface.

Since the number of address lines provided by the system CPU 21 is 12, if the signal is used as it is, only the 4K region is accessible, and there may be a problem that the interface signal of the DRAM cannot be used as it is when using a larger range of memory. .

Therefore, in the present invention, the address registers 11 and 12 are used as 24 addresses so that 12 addresses when the RAS * signal is enabled and 12 addresses when the CAS * signal are enabled can be used. It increases the number of possible addresses and waits until the 24 addresses are stabilized, thereby enabling the address registers 11 and 12 by the gate logic 13.

That is, when the SI 21 starts a cycle, the RAS * signal is driven while enabling the rd * signal or the wr * signal, driving a row address, and converting the RAS * signal into the inverter of the gate logic 13. Passing through (I1, I2) generates an inverted RAS * signal as shown in FIG.

When this signal is put into the cp input of the address registers 11 and 12, a stable lower address is clocked and continuously generated as an output of the address register 11, and the column address is also inverted. When connected to an input, a memory address (Mem-Add11: 0) is generated at its output.

The memory 22 in the 16M area is made accessible via Mem-add11: 0 generated in the address register 11 in this way. The address generated by the inverted RAS * signal and the CAS * signal is continuously generated until the next clock rising edge, so the address is supplied stably.If the lower address is the same, only the column address is used. Since Mem-add11: 0 changes, the access time of the memory 22 can be appropriately adjusted only by the CAS * enable time.

If the address registers 11 and 12 use a '543' latch transceiver, the Add11: 0 signal may be latched using a level instead of cp (Clock Pulse).

In this case, only the latch method is different, and the other operations are the same.

The present invention has the advantage of reducing the access latency of such a system by allowing the system to directly access the memory when the computer system accesses the memory except DRAM or SRAM, without the bus arbitration of the PCI bus or the ISA bus. In terms of buses and ISA buses, other bus masters have more opportunities to use the bus, which can increase the overall bus efficiency.

Claims (3)

A memory access processing means of a computer system provided with a system sipe oil 21 and a DRAM and an SRAM connected thereto, the system sipe oil 21 being connected between the si siil oil 21 and a predetermined memory 22 having no separate interface. The memory access logic unit generates a RAS * (Row Address Strode) signal, a CAS * (Column Address Strode), an address signal, and the like, which can access a predetermined memory 22 using the DRAM control signal of the system sipe oil 21. A memory interface circuit, characterized in that the structure (1) is provided. The memory access logic unit 1 stores the RAS * (Row Address Strode) signal and the CAS * (Column Address Strode), read (rd *) and write (wr *) signals in the system. ) And a gate logic 13 for driving to the memory 22 side, and an address register 11 and 12 connected to an input of an output of the gate logic 13 and an address port of the CP oil 21. Memory interface circuit 3. The memory interface circuit according to claim 2, wherein the gate logic (13) comprises a combination circuit consisting of an or gate (O), an end gate (A1, A2), and an inverter (I1, I1).