JPS6245698B2 - - Google Patents
Info
- Publication number
- JPS6245698B2 JPS6245698B2 JP58027201A JP2720183A JPS6245698B2 JP S6245698 B2 JPS6245698 B2 JP S6245698B2 JP 58027201 A JP58027201 A JP 58027201A JP 2720183 A JP2720183 A JP 2720183A JP S6245698 B2 JPS6245698 B2 JP S6245698B2
- Authority
- JP
- Japan
- Prior art keywords
- dielectric layer
- sample
- electrode
- electrostatic chuck
- plastic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004033 plastic Substances 0.000 claims description 15
- 229920003023 plastic Polymers 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 12
- 238000007751 thermal spraying Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 8
- 238000005507 spraying Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 48
- 239000000463 material Substances 0.000 description 13
- 235000012431 wafers Nutrition 0.000 description 11
- 239000010408 film Substances 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 5
- 238000001179 sorption measurement Methods 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 3
- 229910002113 barium titanate Inorganic materials 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005470 impregnation Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000010407 anodic oxide Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000010445 mica Substances 0.000 description 1
- 229910052618 mica group Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012768 molten material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、導電材料や半導体材料等からなる試
料を加工或いは検査するにあたつて、これらの試
料を電気的に固定保持する静電チヤツク装置の製
造方法に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an electrostatic chuck device for electrically fixing and holding samples made of conductive materials, semiconductor materials, etc. when processing or inspecting these samples. Relating to a manufacturing method.
半導体ウエーハを加工或いは検査する工程にお
いては、ウエーハを加工機や検査機の所定部位に
固定保持することが必要となる。特に、ウエーハ
上に微細なパターンを描画し多数のトランジスタ
を形成する集積回路の製作においては、ウエーハ
を平坦な面に確実に固定することが必要である。
In the process of processing or inspecting a semiconductor wafer, it is necessary to securely hold the wafer at a predetermined location of a processing machine or an inspection machine. Particularly, in the production of integrated circuits in which a fine pattern is drawn on a wafer to form a large number of transistors, it is necessary to securely fix the wafer to a flat surface.
従来、このような場合の保持手段として機械
式、真空式（流体の圧力差を利用したもの）およ
び電気式のチヤツクが用いられている。これらの
チヤツクの中で電気式のものは、試料の平坦度を
良くして固定することができ、かつ取扱いが簡単
であるため半導体製造分野において特に有用であ
る。 Conventionally, mechanical, vacuum (using fluid pressure differences), and electric chucks have been used as holding means in such cases. Among these chucks, electric chucks are particularly useful in the field of semiconductor manufacturing because they can fix the sample with good flatness and are easy to handle.
電気式チヤツク、すなわち電気的に試料を保持
する静電チヤツク装置は、２つの互いに反対に荷
電されたコンデンサ板の吸引力を利用するもの
で、一般に第１図に示す如く電極１、誘電層２、
直流電源３および導電性（半導体も含む）の試料
４から構成される。なお、第１図中５は試料４と
の導通をとるための接点を示している。このよう
なチヤツク板における試料の吸着力Ｆは電極と試
料との間の誘電層に大きく影響され、一般に次式
で示される。 Electric chucks, ie, electrostatic chuck devices that electrically hold a sample, utilize the attractive force of two oppositely charged capacitor plates, generally consisting of an electrode 1 and a dielectric layer 2, as shown in FIG. ,
It consists of a DC power source 3 and a conductive (including semiconductor) sample 4. Note that 5 in FIG. 1 indicates a contact point for establishing electrical continuity with the sample 4. The adsorption force F of a sample on such a chuck plate is greatly influenced by the dielectric layer between the electrode and the sample, and is generally expressed by the following equation.
Ｆ＝１／２εp・εs・Ｓ（Ｖ／ｔ）２〔Ｎ〕………(1
)
ただし、εpは真空誘電率、εsは比誘電率、Ｓ
は面積、Ｖは電圧、ｔは誘電層の厚さである。上
記第１式から判るように誘電層の厚さｔが薄い
程、さらに誘電層の比誘電率εsが大きい程低電
圧で使用することが可能である。また、誘電層に
は試料が繰り返し固定されるため、耐摩耗性およ
び耐圧性が要求される。 F=1/2ε p・ε s・S (V/t) 2 [N]……(1
) However, ε p is the vacuum permittivity, ε s is the relative permittivity, and S
is the area, V is the voltage, and t is the thickness of the dielectric layer. As can be seen from the first equation above, the thinner the thickness t of the dielectric layer and the larger the dielectric constant ε s of the dielectric layer, the lower the voltage can be used. Furthermore, since samples are repeatedly fixed to the dielectric layer, wear resistance and pressure resistance are required.
公知の英国特許第144321号では、静電チヤツク
板としてマイカ、ポリエステル或いはチタン酸バ
リウムで作られた誘電層が示されているが、これ
らの材料は電極に付着させるために接着剤を使用
しなければならず、このため誘電層表面の滑らか
さが接着剤によつて大きく失われると云う欠点が
ある。 Known British Patent No. 144321 shows dielectric layers made of mica, polyester or barium titanate as electrostatic chuck plates, but these materials require the use of adhesives to adhere to the electrodes. However, this has the disadvantage that the smoothness of the surface of the dielectric layer is greatly reduced by the adhesive.
また、公知の日本特許、特開昭55−145351号公
報では、誘電層材料が電極材料の酸化物、特に陽
極酸化物で構成されていることが特徴となつてい
るが、この場合誘電層の厚さを500〔Å〕以下と
すると試料の繰り返し固定、製作時および使用時
の取り扱いによつて簡単に傷が入つてしまい、誘
電層の絶縁不良を招く。酸化膜誘電層を厚くする
ことによつてこれらのことを防止できるとして
も、酸化過程で表面層の粗さは悪化し、結果的に
試料との真実接触表面積が極端に減少する。すな
わち、前記第１式で示した面積Ｓが非常に小さく
なり、吸着力が低下し、時には加工や検査に必要
な保持力を発生しないこともある。さらに、ポー
ラスな部分の誘電率が略１となり、誘電層全体の
比誘電率も減少し、吸着力が目標より大幅に低下
する等の問題があつた。 Furthermore, a well-known Japanese patent, JP-A-55-145351, is characterized in that the dielectric layer material is composed of an oxide of an electrode material, particularly an anodic oxide; If the thickness is less than 500 Å, it will be easily scratched by repeated fixing of the sample and handling during manufacturing and use, resulting in poor insulation of the dielectric layer. Even if these problems can be prevented by increasing the thickness of the oxide dielectric layer, the roughness of the surface layer deteriorates during the oxidation process, resulting in an extreme reduction in the actual contact surface area with the sample. That is, the area S shown in the first equation becomes very small, the suction force decreases, and sometimes the holding force necessary for processing and inspection may not be generated. Further, the dielectric constant of the porous portion was approximately 1, and the relative dielectric constant of the entire dielectric layer was also reduced, causing problems such as the attraction force being significantly lower than the target.
本発明の目的は、電極材料と誘電層材料とを特
に一致させることなく高い比誘電率を有する誘電
層材料を自由に選択することができ、吸着力、機
構的強度および耐摩耗性の向上をはかり得、かつ
誘電層表面の平坦度を十分高くすることが可能な
静電チヤツク装置の製造方法を提供することにあ
る。
The purpose of the present invention is to enable the freedom to select a dielectric layer material having a high relative permittivity without having to specifically match the electrode material and the dielectric layer material, thereby improving adsorption force, mechanical strength, and wear resistance. It is an object of the present invention to provide a method for manufacturing an electrostatic chuck device that is measurable and that can sufficiently increase the flatness of the surface of a dielectric layer.
本発明の骨子は、誘電層を溶射により形成し、
その表面部をプラスチツクを含浸させて平坦化処
理を施すことにある。誘電層材料としてアルミナ
（Al2O3）、酸化チタン（TiO2）およびチタン酸バ
リウム（BaTiO3）等の無機材料或いはこれらの材
料を混合したものを使用することによつて、十分
に高い比誘電率を持つた誘電層を形成することが
できる。さらに、数種の誘電材料を混合して溶射
することにより、融点を下げ生産性および加工性
の良い誘電層の形成が可能である。また、溶射は
物理的に固定されているが、その固定力は十分に
強く、表面の平坦度を増すために行う研削やラツ
ピング等の機械加工に対しても十分耐え得る固定
力を持つている。また、電極を溶射或いは蒸着で
形成することによつて、基板との被着力が十分大
きな状態で薄い電極面を平坦度良く形成すること
が可能である。
The gist of the present invention is to form a dielectric layer by thermal spraying,
The purpose is to impregnate the surface with plastic and flatten it. A sufficiently high ratio can be achieved by using inorganic materials such as alumina (Al 2 O 3 ), titanium oxide (TiO 2 ), and barium titanate (BaTiO 3 ) or a mixture of these materials as the dielectric layer material. A dielectric layer having a dielectric constant can be formed. Furthermore, by thermal spraying a mixture of several types of dielectric materials, it is possible to lower the melting point and form a dielectric layer with good productivity and workability. In addition, thermal spraying is physically fixed, but its fixing force is strong enough to withstand mechanical processing such as grinding and lapping to increase the flatness of the surface. . Furthermore, by forming the electrode by thermal spraying or vapor deposition, it is possible to form a thin electrode surface with good flatness while maintaining a sufficiently strong adhesion to the substrate.
本発明はこのような点に着目し、表面平坦な基
板上に電極を被着し、その上面を誘電層で被覆し
てなり、誘電層上に配置される導電性若しくは半
導体試料を電気的に固定保持する静電チヤツク装
置を製造するに当り、誘電層を溶射により形成
し、その表面部にプラスチツクを含浸させた後、
これに平坦化加工を施すようにしたものである。 The present invention focuses on these points, and consists of depositing an electrode on a substrate with a flat surface, covering the upper surface with a dielectric layer, and electrically connecting a conductive or semiconductor sample placed on the dielectric layer. When manufacturing an electrostatic chuck device to be fixed and held, a dielectric layer is formed by thermal spraying, and after impregnating the surface with plastic,
This is then subjected to a flattening process.
本発明によれば、電極材料の酸化で誘電層を形
成する場合と異なり、誘電材料を自由に選択する
ことが可能であり、誘電層の比誘電率を十分に大
きくすることができる。また、接着剤を使用する
必要もなく長期の使用でも劣化することがない。
さらに、溶射する材料の選択により誘電層の機械
的強度および耐摩耗性を十分大きくすることがで
きる。すなわち、吸着力、機械的強度および耐摩
耗性の向上をはかり得、かつ誘電層表面の平坦度
を十分高くすることができる。また、基板材料と
溶射材料との選択で各材料の熱膨張係数を一致さ
せることにより、熱変形によるクラツクの発生や
平坦度の悪化を未然に防止することができる。
According to the present invention, unlike the case where a dielectric layer is formed by oxidizing an electrode material, it is possible to freely select a dielectric material, and the dielectric constant of the dielectric layer can be made sufficiently large. Furthermore, there is no need to use adhesives, and there is no deterioration even after long-term use.
Furthermore, the mechanical strength and wear resistance of the dielectric layer can be sufficiently increased by selecting the material to be thermally sprayed. That is, the adsorption force, mechanical strength, and wear resistance can be improved, and the flatness of the surface of the dielectric layer can be made sufficiently high. Further, by selecting the substrate material and the thermal spraying material so that the coefficients of thermal expansion of each material match, it is possible to prevent the occurrence of cracks and deterioration of flatness due to thermal deformation.
また本発明によれば、溶射により形成された多
孔質の誘電層にプラスチツクを含浸させ、その表
面に平坦化加工を施すことにより、強い吸着力を
発揮する良好な平坦面を容易に得ることができ
る。更にこのプラスチツクの含浸により誘電層の
比誘電率の増大が図られる。 Further, according to the present invention, by impregnating plastic into a porous dielectric layer formed by thermal spraying and flattening the surface, it is possible to easily obtain a good flat surface that exhibits strong adsorption force. can. Furthermore, this plastic impregnation increases the dielectric constant of the dielectric layer.
第２図は本発明の一実施例の概略構成を示す平
面図、第３図ａは第２図の矢視Ａ−Ａ断面図、第
３図ｂは第２図の矢視Ｂ−Ｂ断面図である。図中
１１は金属製の基板であり、この基板１１の上面
は平坦に加工され、基板１１上には絶縁層１２
が、例えばアルミナの溶射により形成されてい
る。絶縁層１２上には、アルミニウムの蒸着によ
り２つの電極１３ａ，１３ｂがそれぞれ形成され
ている。電極１３ａ，１３ｂは半円形状の薄膜か
らなるもので相互に線対称に配置されている。
Fig. 2 is a plan view showing a schematic configuration of an embodiment of the present invention, Fig. 3a is a sectional view taken along arrow A-A in Fig. 2, and Fig. 3b is a sectional view taken along arrow BB in Fig. 2. It is a diagram. In the figure, reference numeral 11 denotes a metal substrate.The upper surface of this substrate 11 is processed to be flat, and an insulating layer 12 is placed on the substrate 11.
is formed, for example, by thermal spraying of alumina. Two electrodes 13a and 13b are formed on the insulating layer 12 by aluminum vapor deposition. The electrodes 13a and 13b are made of semicircular thin films and are arranged line-symmetrically with respect to each other.
電極１３ａ，１３ｂおよび絶縁層１２上には、
アルミナを溶射してなる誘電層１４が形成されて
いる。ここで溶射とは、溶射材料を熱溶融したも
のを吹き付けることを云う。誘電層１４には、エ
ポキシ樹脂や弗素樹脂等の合成若しくは半合成さ
れた高分子材料を主成分とするプラスチツク１５
が含浸されている。そして、プラスチツク１５が
含浸された誘電層１４の表面は研摩、ラツピング
およびバフ等によつて平坦化加工されている。し
かして、誘電層１４の上面に半導体ウエーハ等の
試料１６が載置され、前記電極１３ａ，１３ｂ間
に直流電源１７が接続されるものとなつている。 On the electrodes 13a, 13b and the insulating layer 12,
A dielectric layer 14 is formed by spraying alumina. Thermal spraying here refers to spraying a thermally molten material. The dielectric layer 14 is made of plastic 15 whose main component is a synthetic or semi-synthetic polymeric material such as epoxy resin or fluororesin.
is impregnated. The surface of the dielectric layer 14 impregnated with the plastic 15 is planarized by polishing, lapping, buffing, or the like. A sample 16 such as a semiconductor wafer is placed on the upper surface of the dielectric layer 14, and a DC power source 17 is connected between the electrodes 13a and 13b.
このような構成であれば、電極１３ａから上方
向に出た電界は試料１６に入り、試料１６から下
方向に出た電界は電極１３ｂに入ることになり、
これにより試料１６を電極１３ａ，１３ｂ側に吸
引でき、試料１６を誘電層１４上に吸着せしめる
ことができる。そしてこの場合、誘電層１４をア
ルミナの溶射によつて形成しているので、誘電層
１４の比誘電率を自由に選択することができ、誘
電層１４の機械的強度および耐摩耗性の向上をは
かり得る。 With such a configuration, the electric field emitted upward from the electrode 13a will enter the sample 16, and the electric field emitted downward from the sample 16 will enter the electrode 13b.
Thereby, the sample 16 can be attracted to the electrodes 13a and 13b, and the sample 16 can be attracted onto the dielectric layer 14. In this case, since the dielectric layer 14 is formed by spraying alumina, the dielectric constant of the dielectric layer 14 can be freely selected, and the mechanical strength and wear resistance of the dielectric layer 14 can be improved. It can be measured.
また、試料１６と電源１７との導通をとる必要
がないことから次のような利点が得られる。すな
わち、半導体製造プロセスでのウエーハ（試料）
は、工程の途中でウエーハ全面に酸化膜や窒化膜
等の絶縁膜が形成される。このようなウエーハを
静電チヤツクにより吸着する場合には、ウエーハ
と電源との導通をとるため、上記絶縁膜を例えば
高電圧で破壊或いは削り落とす等して絶縁膜の一
部を取り除く必要がある。このため、工程の複雑
化を招く。また、高電圧による絶縁膜の破壊の際
には、絶縁膜やレジスト等が飛び散つてごみとな
り、ウエーハ表面を汚す等の問題が生じる。しか
るに、本装置では一対の電極１３ａ，１３ｂ間に
電圧を印加することによつて、試料との導通をと
ることなしに試料を誘電層上に吸着することがで
きる。つまり、試料１６と電源１７との導通をと
る必要がないことから、半導体ウエーハ表面に形
成された絶縁膜を取り除く等の面倒な工程が不要
となる。 Further, since there is no need to establish continuity between the sample 16 and the power source 17, the following advantages can be obtained. In other words, wafers (sample) in the semiconductor manufacturing process
During the process, an insulating film such as an oxide film or a nitride film is formed over the entire surface of the wafer. When such a wafer is to be attracted by an electrostatic chuck, it is necessary to remove a portion of the insulating film by, for example, destroying or scraping it off with a high voltage in order to establish continuity between the wafer and the power supply. . Therefore, the process becomes complicated. Further, when the insulating film is destroyed by high voltage, the insulating film, resist, etc. are scattered and become dust, causing problems such as contaminating the wafer surface. However, in this device, by applying a voltage between the pair of electrodes 13a and 13b, the sample can be adsorbed onto the dielectric layer without establishing electrical continuity with the sample. That is, since there is no need to establish electrical continuity between the sample 16 and the power source 17, there is no need for troublesome steps such as removing an insulating film formed on the surface of the semiconductor wafer.
また、本実施例のように誘電層１４に前記プラ
スチツク１５を含浸させることによつて、次のよ
うな効果が得られる。すなわち、溶射によつて形
成された誘電層１４は完全に気泡をなくすことが
できず、多孔質層となる。このため、前述したよ
うに吸着力が低下するが、上記プラスチツク１５
の含浸により多孔質部分を埋め比誘電率を増すこ
とができる。通常、チヤツク板の平坦度および表
面粗さを良くするために研削およびラツピング等
により加工を行うが、多孔質の場合表面粗さはあ
る程度しか良くならない。これに対し、プラスチ
ツク１５を含浸させた場合、非常に良い表面粗さ
を得ることができる。さらに、チヤツク板を真空
中で使用する場合、多孔質内の空気やガスをなか
なか放出できず真空度が上がらないことがある
が、プラスチツク１５の含浸により（この場合、
数ミクロンの空洞に流入するようプラスチツク１
５に適当な粘度、流動性を持たせる。含浸の割合
は誘電層１４の全体でも表面層のみでも良い。）、
ガス放出を少なくすることができる。 Further, by impregnating the dielectric layer 14 with the plastic 15 as in this embodiment, the following effects can be obtained. That is, the dielectric layer 14 formed by thermal spraying cannot completely eliminate bubbles and becomes a porous layer. For this reason, as mentioned above, the adsorption force decreases, but the plastic 15
The dielectric constant can be increased by impregnating the porous portions. Normally, processing such as grinding and lapping is performed to improve the flatness and surface roughness of the chuck plate, but in the case of porous materials, the surface roughness can only be improved to a certain extent. On the other hand, when the plastic 15 is impregnated, a very good surface roughness can be obtained. Furthermore, when the chuck plate is used in a vacuum, it may be difficult to release the air or gas inside the pores and the degree of vacuum may not increase.
plastic 1 so that it flows into a cavity of several microns.
5 to have appropriate viscosity and fluidity. The ratio of impregnation may be the entire dielectric layer 14 or only the surface layer. ),
Gas release can be reduced.
なお、本発明は上述した実施例に限定されるも
のではない。例えば、前記溶射する誘電層材料と
しては、アルミナに限らず酸化チタン、チタン酸
バリウム或いはセラミツクスの中で溶射可能なも
のを適当に選んで使用すればよい。さらに、前記
プラスチツクは、エポキシ樹脂や弗素樹脂等の高
分子材料に限るものではなく、その他のプラスチ
ツク類を種々目的に合わせて使用することができ
る。さらに、前記基板としてガラス等の絶縁基板
を用いる場合、前記絶縁層を設けなくてもよい。 Note that the present invention is not limited to the embodiments described above. For example, the material for the dielectric layer to be thermally sprayed is not limited to alumina, but may be appropriately selected from titanium oxide, barium titanate, or ceramics that can be thermally sprayed. Further, the plastic is not limited to polymer materials such as epoxy resin and fluororesin, and other plastics can be used depending on various purposes. Furthermore, when an insulating substrate such as glass is used as the substrate, the insulating layer may not be provided.
また、前記電極の数は２つに限るものではな
く、１個或いは2n（ｎは自然数）個の範囲で適
宜定めればよい。ここで、電極を１個とする場
合、電極と試料との間に電圧を印加するために試
料表面の絶縁膜を取り除く等の工程が必要となる
が、この場合であつても前述した本発明の目的は
十分達成される。さらに、電極間或いは電極と試
料との間に印加する電圧は一定電圧に限るもので
はなく、適当な周波数で変化する電圧であつても
よい。また、電極の形成手段として蒸着の代りに
溶射を用いることも可能である。その他、本発明
の要旨を逸脱しない範囲で、種々変形して実施す
ることができる。 Further, the number of the electrodes is not limited to two, and may be appropriately determined within the range of one or 2n (n is a natural number). Here, when using only one electrode, a process such as removing an insulating film on the surface of the sample is required in order to apply a voltage between the electrode and the sample, but even in this case, the present invention described above The purpose of is fully achieved. Furthermore, the voltage applied between the electrodes or between the electrode and the sample is not limited to a constant voltage, but may be a voltage that changes at an appropriate frequency. Moreover, it is also possible to use thermal spraying instead of vapor deposition as a means for forming the electrodes. In addition, various modifications can be made without departing from the gist of the present invention.
第１図は従来の静電チヤツク装置の概略構成を
示す断面図、第２図は本発明の一実施例の概略構
成を示す平面図、第３図ａは第２図の矢視Ａ−Ａ
断面図、第３図ｂは第２図の矢視Ｂ−Ｂ断面図で
ある。
１１……基板、１２……絶縁層、１３ａ，１３
ｂ……電極、１４……誘電層、１５……プラスチ
ツク、１６……試料、１７……電源。
FIG. 1 is a sectional view showing a schematic configuration of a conventional electrostatic chuck device, FIG. 2 is a plan view showing a schematic configuration of an embodiment of the present invention, and FIG. 3a is a view taken along arrow A-A in FIG.
The cross-sectional view, FIG. 3b, is a cross-sectional view taken along arrow B-B in FIG. 11...Substrate, 12...Insulating layer, 13a, 13
b...electrode, 14...dielectric layer, 15...plastic, 16...sample, 17...power supply.
Claims (1)
前記電極を覆うように溶射により誘電層を形成す
る工程と、前記誘電層表面部にプラスチツクを含
浸させる工程と、前記プラスチツクを含浸させた
誘電層表面部に平坦化加工を施す工程とを有する
ことを特徴とする静電チヤツク装置の製造方法。 ２ 前記電極として、少なくとも２つの電極膜を
形成することを特徴とする特許請求の範囲第１項
記載の静電チヤツク装置の製造方法。 ３ 前記基板は、絶縁物からなるものであること
を特徴とする特許請求の範囲第１項又は第２項記
載の静電チヤツク装置の製造方法。 ４ 前記基板は、表面平坦な金属板上に絶縁層を
溶射或いは蒸着してなるものであることを特徴と
する特許請求の範囲第１項記載又は第２項の静電
チヤツク装置の製造方法。[Claims] 1. A step of depositing an electrode on a substrate with a flat surface;
The method includes the steps of: forming a dielectric layer by thermal spraying so as to cover the electrode; impregnating the surface of the dielectric layer with plastic; and flattening the surface of the dielectric layer impregnated with the plastic. A method of manufacturing an electrostatic chuck device characterized by: 2. The method of manufacturing an electrostatic chuck device according to claim 1, characterized in that at least two electrode films are formed as the electrodes. 3. The method of manufacturing an electrostatic chuck device according to claim 1 or 2, wherein the substrate is made of an insulator. 4. The method of manufacturing an electrostatic chuck device according to claim 1 or 2, wherein the substrate is formed by thermally spraying or vapor depositing an insulating layer on a metal plate with a flat surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2720183A JPS59152636A (en) | 1983-02-21 | 1983-02-21 | Static chucking device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2720183A JPS59152636A (en) | 1983-02-21 | 1983-02-21 | Static chucking device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59152636A JPS59152636A (en) | 1984-08-31 |
| JPS6245698B2 true JPS6245698B2 (en) | 1987-09-28 |
Family
ID=12214475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2720183A Granted JPS59152636A (en) | 1983-02-21 | 1983-02-21 | Static chucking device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59152636A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62286248A (en) * | 1986-06-05 | 1987-12-12 | Toto Ltd | Electrostatic chuck plate and manufacture thereof |
| JPH0727961B2 (en) * | 1986-06-05 | 1995-03-29 | 東陶機器株式会社 | Method of manufacturing electrostatic chuck plate |
| JP2521471B2 (en) * | 1987-05-14 | 1996-08-07 | 富士通株式会社 | Electrostatic suction device |
| EP0339903B1 (en) * | 1988-04-26 | 1993-10-06 | Toto Ltd. | Method of making dielectric ceramics for electrostatic chucks |
| JP2600558Y2 (en) * | 1991-10-02 | 1999-10-12 | 住友金属工業株式会社 | Electrostatic chuck |
| KR100463782B1 (en) * | 1995-09-20 | 2005-04-28 | 가부시끼가이샤 히다치 세이사꾸쇼 | Electrostatic adsorption electrode and its manufacturing method |
| JP4268450B2 (en) * | 2003-05-23 | 2009-05-27 | キヤノン株式会社 | Large glass substrate adsorption device for display |
| EP3846334A4 (en) * | 2019-09-11 | 2021-12-08 | Creative Technology Corporation | Attachment/detachment device |
| JP7204009B2 (en) | 2019-12-13 | 2023-01-13 | 三井化学株式会社 | Pellicle demounting method and pellicle demounting device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57148356A (en) * | 1981-03-09 | 1982-09-13 | Hitachi Ltd | Sample holding device |
-
1983
- 1983-02-21 JP JP2720183A patent/JPS59152636A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57148356A (en) * | 1981-03-09 | 1982-09-13 | Hitachi Ltd | Sample holding device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59152636A (en) | 1984-08-31 |
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