JPS624342A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To relieve the complication in wiring, by providing word selection output terminals of a decoder circuit at a pitch corresponding to an integral multiple of that of word selection terminals of a standard cell of a storage device. CONSTITUTION:In a decoder 1, word selection output terminals 4 are provided at a pitch whose value is corresponding to an integral multiple of the value of a pitch of work selection terminals 3 in a RAM standard cell 2. It is thereby enabled to wire straightly all the word lines including those between the decoder 1 and the RAM 2. Accordingly, the utilization rate of transverse channels provided in the wiring zone between the standard cells is decreased and the complication in wiring in this zone can be relieved. Thus, the number of mounting gates can be prevented from being decreased due to the impossibility of wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device in which a RAM or ROM is effectively mounted within a master slice type gate array LSI. .

[Conventional technology]

Master slicing gate arrays are designed to efficiently develop integrated circuits with a high variety of products in small quantities, by designing a common mask pattern for each product type up to the diffusion process and manufacturing them using a common process. The pattern consists of standard cells arranged in a grid, and the space between cells is the wiring area. By designing and manufacturing only the wiring pattern in this wiring area for each type of LSI, it is possible to economically develop a wide variety of LSIs. It is something that can be done.

When trying to incorporate RAM or ROM (hereinafter referred to as a storage device) into such a master slice gate array, it is difficult to implement a storage device on the horizontally structured transistor rows in the gate array, and a logic circuit is required on the gate array chip. In addition to the area, a dedicated area for the storage device must be provided. For this reason, the size of the storage device you want to incorporate is limited by the size of the dedicated area.
Furthermore, when the size of the storage device is smaller than the size of the dedicated area, there is a drawback that the usage efficiency of the dedicated area becomes poor.

However, by configuring the memory device using standard cells in the gate array, RAM can be used without providing a dedicated area.
Alternatively, the applicant has already developed a device that can be equipped with a ROM and that can solve the above-mentioned problems.

FIG. 2 shows an example of a gate array LSI developed by the applicant that has a built-in RAM or ROM circuit. In Figure 0, which shows the arrangement of word RAM in L bits that make up the section,
1 indicates a standard cell that constitutes a decoder (hereinafter referred to as a decoder circuit standard cell), and in this example, the decoder is 1.
Although one decoder is composed of one standard cell, the same applies even if one decoder is composed of a plurality of standard cells. 2 is RA
There are L standard cells (hereinafter referred to as RAM standard cells) constituting M, each having a capacity of 1 bit)XK words. Further, 3 is a word selection terminal of each RAM standard cell 2, 4 is a word line selection signal output terminal (hereinafter also referred to as a word selection output terminal) of a decoder circuit, and 5 is a decoder circuit. This is word line wiring that connects the word selection output terminal of the standard cell and each word selection terminal of the RAM standard cell.

Further, FIGS. 3 to 5 show basic internal cells for configuring the logic circuit built into the gate array LSI,
In the figure, 301a to 301d are gates of P-channel MOS transistors made of polysilicon; 303a;
~303e is the source of the P channel MO3) transistor.
Drain region, 305 is N well diffusion region, 302a~
302d is an N-channel MOS made of polysilicon)
304a to 304e are N-channel MOS transistor gates, 304a to 304e are N channel MOS transistor source/drain regions, 200 is an isolation region, 201 is a PS
G (phospho 5ilicate glass
) on which aluminum wiring is formed. Further, 202 is a gate oxide film, and 203 is a P-type semiconductor substrate.

Furthermore, FIG. 6 shows a basic unit of a logic circuit called a standard cell, which is placed on a basic internal cell, and this standard cell has the same shape no matter where it is placed on the LSI.
In figure 0, which is the wiring shape of a logic circuit, 306
a, 306b, 308, 309, 310, and 311 are some aluminum wiring, 307 is a double layer aluminum wiring, 101 is a contact hole, and 102 is a through hole. Note that FIG. 6 shows a RAM standard cell constituting the RAM.

Next, the operation will be explained. The word selection output terminal 4 of the decoder 1 selects only one word line at a time, so that the word lines 5 between the L memory standard cells among the L memory cells 2 can be formed in a straight line. However, it is impossible to make all the wiring between the decoder 1 and the RAM 2 in a straight line.

[Problem that the invention seeks to solve]

The semiconductor integrated circuit device developed by the present applicant is configured as described above, and the RAM or ROM is configured using basic cells having the same shape as the logic circuit in the gate array. , gate + 2 internal CRAM'
Z Ruiha. Therefore, it is possible to incorporate RAM or ROM without being limited by the size of this dedicated area, and the size of the RAM or ROM to be built in is smaller than the size of the dedicated area. In this case, it is possible to improve the low usage efficiency of transistors (MOS) in the dedicated area, and it is possible to effectively incorporate RAM or ROM into the gate array LSI.

However, in this semiconductor integrated circuit device, since the wiring between the decoder circuit standard cell 1 and the RAM fl quasi-cell 2 is not in a straight line, between the decoder 1 and the RAM standard cell 2,
Some of the K word lines 5 will be bent. Generally, the bent horizontal wiring in Figure 2 is routed using the horizontal channel prepared within the wiring band between standard cells, which causes wiring congestion in this part, but such congestion occurs. Therefore, there is a problem in that the number of wires that can be used in the wire band between the decoder 1 and the memory section 2 is limited, and the number of gates that can be mounted on the entire gate array is reduced.

This invention was made to solve the above-mentioned problems, and its purpose is to provide a semiconductor integrated circuit device that can alleviate wiring congestion and prevent a reduction in the number of mounted gates due to the impossibility of wiring. do.

[Means for solving problems]

In the semiconductor integrated circuit device according to the present invention, the pitch of the word selection output terminals of the decoder circuit is arranged to be an integral multiple of the pitch of the word selection terminals of the standard cells of the storage device.

[Effect]

In this invention, since the pitch of the word selection output terminals of the decoder circuit is arranged to be an integral multiple of the pitch of the word selection terminals of the standard cells of the storage device, the decoder portion and the memory standard cell [Embodiment] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor integrated circuit device according to an embodiment of the present invention, in which 1 is a decoder circuit standard cell, 2 is an R
AM standard cell, 3 is a word selection terminal in the RAM standard cell, 4 is a word selection output terminal in the decoder circuit standard cell,
5 is 'word selection terminal 3 questions and word selection output terminal 4
This is a word line wiring that connects the word selection terminal 3 and the word selection terminal 3.

Conventional decoder circuits have been configured to simply minimize the number of transistors used in the decoder circuit, so as mentioned above, in the gate array,
The word selection terminal 3 of the RAM circuit section and the word selection output terminal 4 of the decoder were not formed in a straight line. In contrast, the decoder circuit of this embodiment is configured so that the word selection terminal 3 and the word selection output terminal 4 can be arranged in a straight line, rather than minimizing the number of transistors used. The word selection output terminals 4 are designed so that the pitch of the word selection output terminals 4 is an integral multiple of the pitch of the word selection terminals 3 of the RAM standard cell 2. For this reason, as shown in Figure 1, there are cases where it is impossible to configure a decoder circuit with only one decoder standard cell, and in such cases, for example, two decoder standard cells are connected every other cell. There may also be cases where the receiver is configured to have a word line. However, it goes without saying that the logic circuit is constructed so that only one word line of the two standard decoder cells is selected at a time.

Next, the effects will be explained. In this embodiment, the pitch of the word selection output terminals of the decoder is made an integral multiple of the pitch of the word selection terminals of the RAM, so that all word lines can be wired in a straight line, including between the decoder and the RAM. Therefore, the wiring usage rate of the horizontal channels prepared in the wiring band between standard cells is reduced, the congestion of wiring in this part is alleviated, and it is possible to prevent a reduction in the number of mounted gates due to impossible wiring.

In the above embodiment, a normal master slice type gate array has been described, but in particular, it is possible to create a target logic circuit on a chip in which internal basic cells are densely spread over the entire surface without sufficiently removing the wiring band area in advance. The present invention can also be applied to a master slice type gate array in which the internal basic cells are used simply as wiring bands or as standard cells, depending on the situation. In addition to the effect of increasing the number of gates to be mounted due to the reduction in , the number of gates that can be mounted on the same gate array can be further increased because the degree of integration of the memory circuit portion can be improved.

〔Effect of the invention〕

As described above, according to the semiconductor integrated circuit device of the present invention, all the word lines of the memory device in the gate array LSI are formed in a straight line, so that the wiring usage rate of the wiring band channel can be reduced. As a result, the number of gates that can be mounted on the same gate array can be increased.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the arrangement and wiring of a word RAM in L bits in a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 3 is a plan view showing the basic internal cell of FIG. 2, and FIGS. 4 and 5 are lines AA and B- of FIG. 3. A sectional view taken along the line B, and FIG. 6 is a plan view showing the RAM standard cell of FIG. 2. In the figure, 1 is a decoder circuit standard cell, 2 is a 1 bit x word RAM standard cell, 3 is a word selection terminal, and 4 is a standard cell for a decoder circuit.
is a word selection output terminal, and 5 is a word line. In the drawings, the same reference numerals indicate the same or equivalent parts. Figure 1 2: RAM$1tyi 3: MEμも4: /7-ME゜forceγlpel'i;77mp5:ME゛'
2nd JlJ fee Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Procedural amendment (voluntary) 1. Indication of the case Japanese Patent Application No. 60-143791 2. Name of the invention Semiconductor integrated circuit device 3. Amendment 5. Drawing subject to amendment (Figure 1) 6. Details of amendment (1) Figure 1 will be corrected as shown in the attached sheet. that's all

Claims (2)

[Claims] (1) A semiconductor integrated circuit device consisting of a master slice gate array constructed using standard cells as basic units, comprising a memory device constructed using the standard cells, and comprising a memory section and a decoder of the memory device, respectively. A semiconductor integrated circuit device characterized in that standard cells connected to each other are connected by straight wiring. (2) The semiconductor according to claim 1, wherein the wiring is a word line, and the pitch of the word line selection terminals of the decoder is an integral multiple of the pitch of the word line terminals of the storage device. Integrated circuit device.