JPS6243227A - Equalizer - Google Patents

Abstract

PURPOSE:To obtain an equalizer which can be suitably attached to a time- division signal transmitting circuit by using a coefficient load circuit that can be controlled at a high speed by the external voltage and varying the voltage applied from outside to set the compensating characteristics of the equalizer optionally and in time division. CONSTITUTION:The coefficient (k) of a coefficient load circuit 8 undergoes the time-division control as a time function. In other words a RAM 12 is set in a read mode by a hopping control circuit 13 and addresses 1-3 are designated successively and repetitively. Thus, the control voltage applied to the circuit 8 is varied periodically with the time lapse. Then, the amplitude characteristics of the output signal obtained at an output terminal 9 are changed with the time lapse as shown in the diagrams 31-33. In such a way, the amplitude characteristics of the transmission signal delivered from the terminal 9 can be changed in time division by changing periodically the read address of the RAM 12 through the circuit 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an equalizer, and particularly to time-separate control of a transparsal equalizer.

[Prior art] Figure 2 shows the -V
It is a block diagram showing A. In FIG. 2, 11j is an input terminal, 2 is a distributor, 3 and 4 are delay filters, 6.7 is a combiner, 8 is a coefficient loading circuit, and 9 is an output terminal.

The transmission signal input to input terminal 1 is 1 minute! [i! 32
It is divided into three parts. And 1m! The eye signal is given to the synthesizer 7 as a main signal delayed by 1 second by the delay line 3. Further, the second signal is delayed by 2T seconds by a delay 114 and is applied to the synthesizer 6. The third signal is provided to direct synthesis 2S6. Then, the composite signal of the second signal and the third signal combined by the combiner 6 is weighted with a predetermined coefficient in the coefficient rR selection circuit 8 including polarity reversal, and then combined 2! given to i7. Then, the main signal and the output of the IF+number transfer circuit 8 are combined and output from the output terminal 9 as an output signal.

Here, it is assumed that there is no signal increase/decrease (amplification or attenuation) except for the coefficient vJ multiplex circuit 8, and that there is no signal time delay except for delays II 3 and 4, and if the delay of the main signal is standardized to 0, the output signal is , can be expressed by the following equation.

A(ω)NOO3ωt+kcosω<t +T)+kc
osωft -T) Electricity (1+2kcosωT) CO3ωT However, k: Coefficient? Coefficient ω of l+i counterfeit circuit 8: Information frequency: Time T' delay between rI and 1, to ω) The layer width characteristic is GA (ω) −201ov (1+2k cosω
Ding). The change characteristic of this confusion (If! characteristic G, (r) with respect to the coefficient k is as shown in Fig. 143. As shown in Fig. 3, when the coefficient k is increased, the amplitude of the output signal changes in the direction of the arrow. In other words, it is an amplitude equalizer that can change the amplitude of the output signal by changing the coefficient k to '11.

[Problem to be Solved by the Invention 1] In the conventional equalizer as described above, the compensation characteristics of the output signal are determined by the coefficient k set in the coefficient loading circuit 8, and the characteristics of the output signal are independent of time. constant.

However, when such a conventional equalizer is used in a time division communication device such as a TDMA device, the compensation characteristics of the equalizer do not change as a function of time. The disadvantage is that equalizers are required for the number of routes, and the number of equalizers increases.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an equalizer that is optimal for installation in a time-division signal transmission circuit and can arbitrarily set the compensation characteristics of the equalizer in a time-division manner.

[Means for Solving the Problems 1] The present invention provides a method for storing setting coefficients of a coefficient load circuit for changing the characteristics of a transmission signal by using tlljtlD read from a storage means.
This is an equalizer that can be controlled based on the signal.

[Operation] The plurality of signals stored in the storage means are selectively read out by the successive output control means and applied to the coefficient loading circuit.

The coefficient loading circuit sets coefficients according to the applied signal and changes the characteristics of the transmitted signal.

If the successive barb means periodically specifies the leak address of the storage means at a predetermined control timing, the coefficient loading circuit changes the characteristics of the transmission signal in a time-division manner.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit block diagram showing one embodiment of the present invention. In Figure 1, 1 is an input terminal, 2 is a distributor, 3
．． 4 is a delay line, 6.7 is a synthesizer, 9 is an output terminal,
These are the same as the conventional equalizer (the equalizer explained in FIG. 2).The feature of the circuit of this embodiment is that the coefficient loading circuit 8 is
It is possible to change the time-division characteristics by using a device that is flexible and by varying the voltage applied from the outside. The circuit for voltage control includes a RAM 12 in which multiple voltage values are stored as digital values, and a RAM
The level to set the voltage value to enter 1! l! 1 device 10
．． a hopping control circuit 13 for controlling RAM write and read modes and write and subsequent addresses;
analog/digital (A,/D) converter 11,
It is composed of a digital/analog (D, /A) converter 14.

In the RAM 12, as shown in FIG.
data, and data of voltage value (C) are written in address 3, respectively. Data is written to the RAM 12 by setting the RAM 12 to write mode using the hopping control circuit 13, specifying a write address, and setting an arbitrary voltage (for example, voltage (A)) using the level adjuster 10. , the voltage may be converted into a digital value by the A/D converter 11 and provided. Through this operation, voltage values (A>, (B
), (C) can be loaded. Further, the data at each address 1.2.3 once corrupted can be changed to an arbitrary value by 1 by the above-mentioned operation.

FIG. vA4 is a waveform diagram for explaining the operation of the circuit of FIG. 1.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 4.

The transmission signal input to the input terminal 1 is divided into three signals by the distributor 2, and the signals are changed by the delay [3, delay va4, combiner 6, and coefficient loading circuit 8, respectively, and the signals are changed by the combiner 2S7.
are combined and output from output terminal 9. By changing the coefficient k of the coefficient loading circuit 8, desired characteristics of the output signal can be obtained. Such operation is similar to that of a conventional equalizer.

In this embodiment, the coefficient k of the coefficient loading circuit 8 is not constant regardless of time, but the coefficient fik is time-shared as a function of time! 11ItIll has been done. That is, the hopping control circuit 13 causes the RAM 12 to enter the successive output mode, and as shown in FIG.
At t+, address 1 of RAM12 is specified, and at time 11
! ! Address 2 is specified from t1 to t2, and from time t2 to
At t3, address 3 is designated. Further, from time t onwards, addresses 1 to 3 are sequentially and repeatedly designated in the same cycle as described above. Therefore, the control voltage applied to the coefficient loading circuit 8 changes periodically with time. That is, time t. -1, the voltage (A) is applied, and at time t, ~t2 the voltage (E) is applied,
(C) is given from time t2 to time t, and this is repeated thereafter. Therefore, the amplitude characteristic of the output signal obtained at the output terminal 9 becomes the characteristic shown in the rectangular frame 31 in FIG. 4 from time to to 1+, and at time t.

At ~t, the characteristics are shown in the square frame 32, and at time t2~
t, the characteristics shown in the rectangular frame 33 are obtained.

In this way, the hopping control circuit 13 controls the RAM1
By periodically changing the successive addresses of 2, the amplitude characteristics of the transmission signal output from the output terminal 9 can be changed in a time-division manner.

In the above embodiment, an amplitude equalizer was explained, but any variable equalizer having a coefficient loading circuit that can be switched at high speed can be used (for example, a variable group (Delay Equalizer) It is also possible to control a plurality of coefficient loading circuits 8a, 8b, 8c at the same time, as shown in FIG. Alternatively, as shown in FIG. 7, a plurality of RAMs 12a and 12t+ with different stored data may be provided, and a plurality of coefficients may be stored. :J heavy circuits 8a and 8b at the same time.

Control with different control voltages! If- is also possible.

In each of the above explanations, it is assumed that the level adjustment U device 10 sets an analog voltage, and the analog voltage is A, /'
It is converted into a digital value by the D converter 11 and stored in the RAM.
I tried to get 3 to 12, but the level! Il! If the device sets a digital value, A,/D converter 1
It goes without saying that 1 can be omitted.

Furthermore, as shown in Figure 8, hopping υJ! Instead of the i11 circuit 13, a switching signal from another device causes the RAM 12a. 62 or B11163
is input. In addition to the changeover switch 65, the changeover device 64 simultaneously controls address designation (switching) of the changeover switch 6G and the RAM 12. In other words, the changeover switches 65 and 66 and the RAM 12 are configured such that a predetermined contact point or address is simultaneously selected by the changeover device 1164. Therefore, the signal input to the AH11G2 passes through the changeover switch 66 and is input to the input terminal 1 of the equalizer. At this time, address 1 of the RAM 12 contains a preferable 1il corresponding to the characteristics of the A device 62.
l all level voltage is set. Also, RAM
The desired control level voltage corresponding to the B device v163 is set at address 2 of 12. Therefore, the signal applied to the input terminal 1 of the equalizer via Δ8iff62 is set at address 2 of RA It is controlled by the coefficient loading circuit 8 controlled by the set voltage of address 1 of ~112. On the contrary, the signal l given through BY4863, R△~
ri1 based on the voltage set at address 2 of 112
7I heavy circuit 8.

In this way, the addressing of RA to 112 can be controlled non-periodically by the intermediate circuit instead of being controlled periodically by the hopping control circuit 13.

[Effect of the invention 1 As described above, according to this invention, ? It is possible to provide an equalizer whose I11'f characteristic can be changed over time. As a result, it is possible to provide an equalizer that is particularly suitable for insertion into a time-division winter type signal transmission path.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of a small Zubbing type amplitude equalizer according to an embodiment of this explanation. FIG. 2 is a circuit block diagram showing an example of a conventional amplitude equalizer. FIG. 3 is a waveform diagram showing the characteristics of the amplitude equalizer. 40 is an explanatory diagram for explaining the operation and characteristics of an embodiment of the present invention. Figure w45 is a memory map of R△~112. FIG. 6 is a circuit block diagram showing an equalizer according to another embodiment of the invention. FIG. 7 is a circuit block diagram showing an equalizer according to an embodiment of the present invention. FIG. 8 is a circuit block diagram showing an equalizer according to yet another embodiment of this invention. In the figure, 1 is an input terminal, 3.4 is a delay line, 6.7 is a synthesizer, 8 is a coefficient loading circuit, 9 is an output terminal, 10 is a level adjuster, 12 is a RAM (storage means), 131: t-hopping control circuit is shown. In addition, each (21 (here, 9) is the same or t: indicates a corresponding circuit or element.

Claims (3)

[Claims] (1) An equalizer inserted into a signal transmission path to compensate for characteristic deterioration of the transmitted signal, which loads a coefficient in order to provide arbitrary compensation to the transmitted signal, and furthermore, the coefficient a coefficient loading circuit that can be changed by an external control signal, a storage means for storing a plurality of signals, and a reading device that reads out a predetermined signal stored in the storage means and supplies it to the coefficient loading circuit as an external control signal. and a control means. (2) A level adjuster capable of setting an arbitrary signal is connected to the storage means, and the signal stored in the storage means can be rewritten into a setting signal of the level adjuster, a patent An equalizer according to claim 1. (3) The readout control means is a hopping control circuit that sequentially specifies readout addresses of the storage means at a constant cycle so that the coefficient loading circuit can perform time-division processing. Equalizer according to item 2.