JPS6242604A - Operational amplifier integrated circuit - Google Patents

Abstract

PURPOSE:To attain an operational amplifier integrated circuit which is superior in high frequency characteristic and is strong against the process variation by providing a differential amplifier circuit consisting of a pair of dual gate FETs in the second stage of an operational amplifier. CONSTITUTION:A differential amplifier circuit 2 consisting of a pair of dual gate FETs Q1 and Q2 is connected in cascade as the second stage following a differential amplifier circuit 1 of the first stage. With respect to the high frequency characteristic, the input capacity due to the Miller effect viwed from input terminals 4 and 5 of the amplifier of the second stage is about 2(1+A)-fold input capacity for the use of single gate FETs because dual gate FETs are used as FETs Q1 and Q2. A is the gain of the amplifier of the second stage and is normally 10-50 times.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a field effect transistor (hereinafter abbreviated as FET).
The present invention relates to an operational amplifier integrated circuit.

Conventional integrated circuits using gallium arsenide FETs are expected to be faster in isolation than silicon, and are therefore being actively developed. Among these, operational amplifier integrated circuits are the most basic circuits of analog integrated circuits, and are extremely important circuits in areas where analog and digital signals are mixed, such as A/D converters and digital filters.

An example of a conventional operational amplifier integrated circuit will be described below. An operational amplifier integrated circuit consists of at least three stages. First, the first stage is a differential amplifier circuit, and the second stage is either the same differential amplifier circuit as the first stage or a cascode type amplifier circuit.

The width circuit performs differential amplification of two input signals from the DC region. The second stage further amplifies the signal amplified in the first stage. The third stage reduces the output impedance.

Problems to be Solved by the Invention However, in the above configuration, if a differential amplifier circuit similar to that in the first stage is used in the second stage, the gain at high frequencies will be significantly reduced by 7 due to the Miller effect. In addition, if a cascode circuit is used in the second stage, the Miller effect is reduced and excellent frequency characteristics are obtained. Maintaining the same level is strictly required. As a result, precise control of the threshold voltage of the FET is required in the integrated circuit manufacturing process, making it extremely difficult to obtain a high yield.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a wave multiplication integrated circuit which does not require precise threshold voltage control and has excellent high frequency characteristics.

The only means to solve the problem is to provide a differential amplifier circuit as a second stage amplifier.

Effects According to the present invention, the second stage is inputted to the differential amplifier circuit by the above-mentioned configurations 1 to 1, and is driven by the balanced output of the first stage, so it is not necessary to maintain an accurate DC level of the first stage output. , the manufacturing process becomes very easy and high yield can be obtained.

Furthermore, since the second stage uses a dual gate FET 1, the Miller effect is extremely small and good high frequency characteristics can be obtained.Example: Refer to all drawings for an operational amplifier semiconductor integrated circuit according to an example of the present invention. I will explain while doing so. The figure shows a circuit diagram of an operational amplifier integrated circuit in one embodiment of the present invention. In the figure, 1 is a first stage amplifier formed by a differential amplifier circuit, 2 is a second stage amplifier, and 3 is an output Banoff 7. 4,5
is the balanced output of the first stage amplifier 1 and is input to the second stage amplifier 2. 6°7 is the balanced output of the second stage amplifier 2, and the output
input to F3. 8 and 9 are positive and negative power supply terminals, respectively. The sources 7 of Q1 to Q5 are both connected to the common connection point 1o of the gallium arsenide FETs Q1 and Q2. The first gates of Ql and Q2 are connected to the balanced outputs 4, 5 of the first stage amplifier 1, respectively.

The second gates of Ql and 02 are both connected to the common connection point 10. The drains of Ql and Q2 become the balanced outputs 6 and 7 of the second stage amplifier, respectively. Q3 to Q5 are single gate type FETs. Q3゜Q4 are Ql and Q, respectively.
2, the drains of Q3,04 are both connected to the positive power supply terminal 8, and the drains of Q3. Both gates of Q4 are connected to the sources of their respective FETs. Q5 has its drain connected to the common connection point 1o, and its gate and source commonly connected to the negative power supply terminal 9.

Regarding the operational amplifier integrated circuit configured as above,
I will explain the entire operation. First, regarding high frequency characteristics, Ql
, by using a dual-gate FET for Q2, the input capacitance due to the Miller effect seen from the input terminal 4°6 of the second stage amplifier is approximately 2/(1+A) compared to when a single-gate FET is used. Double. Here, A is the gain of the second stage amplifier. A is usually 10 to 50 times. As a result, in the operational amplifier integrated circuit of this embodiment, the pole of the transfer function resulting from the product of the output resistance of the first-stage amplifier 1 and the Miller capacitance of the second-stage amplifier 2 moves outside the desired band, resulting in excellent high-frequency characteristics. An operational amplifier integrated circuit can be realized. Furthermore, since the first and second stages are coupled by a balanced signal, even if the threshold of the FET changes as a result of the manufacturing process and a predetermined DC level cannot be obtained, the performance degradation is very small. According to a computer simulation, when a cascode amplifier is used in the second stage and the second stage is driven by an unbalanced signal as in the conventional case, the threshold voltage of the FET is allowed to fluctuate only by □, 1v, but as in the present invention, Furthermore, it was confirmed that when a differential amplifier circuit is used in the second stage and the first stage and second stage are connected with a balanced signal, the threshold voltage of the FET can be up to ±0.4 V.

As described above, according to this embodiment, by providing a differential amplifier circuit consisting of a pair of dual gate FETs in the second stage of the operational amplifier, the Miller effect is extremely small and good high frequency characteristics are achieved. Moreover, it is possible to realize an operational amplifier integrated circuit that is resistant to fluctuations in the device process.

In this embodiment, the second stage amplifier consists of only a differential amplifier circuit, but a source follower circuit that also serves as a DC level shifter and a buffer is inserted between the full output terminal 6°7 and the output cover sofa 3 of the third stage. You can.

Further, in this embodiment, the gate terminals of Q3 and Q04 are each commonly connected to the source terminal, but they may also be commonly connected to the drain terminal. Also, Q3. Q4
A resistor may be used instead.

Further, although the gate terminal of Q5 is commonly connected to the source terminal, it may be connected to a power source having a fixed DC potential.

Further, in this embodiment, the second gates of Q1 and Q2 are connected to the common connection point 10, but the second gates of Q1 and Q2 may all be commonly connected to a power supply having a fixed DC potential.

Effects of the Invention As described above, the present invention provides excellent high frequency characteristics by providing a differential amplifier circuit consisting of 0 pairs of dual gate type FETs in the second stage of the operational amplifier.

Moreover, it is possible to realize an operational amplifier integrated circuit that is resistant to process variations.

[Brief explanation of the drawing]

The figure is a circuit diagram of an operational amplifier integrated circuit in one embodiment of the present invention.

Claims (1)

[Claims] 1. An operational amplifier integrated circuit characterized in that, after a first stage differential amplifier circuit, a second stage differential amplifier circuit consisting of a pair of dual gate FETs is connected in cascade.