JPS6242529A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a groove having a tapered angle and no undercut to an opening section in a substrate by shaping a groove having the tapered angle to an insulating film on the substrate and etching the groove in an anisotropic manner. CONSTITUTION:An SiO2 film 2 is formed onto an Si substrate 1, a resist is applied onto the film 2, and a pattern 3 having a predetermined tapered angle is shaped. The substrate 1 is etched in an anisotropic manner while using the pattern 3 as a mask. A groove 4 is formed to the substrate 1 through anisotropic etching while employing the film 2 as a mask. According to the method, the groove having the tapered angle in an opening section can be shaped to the substrate 1, thus preventing the generation of an undercut even when the opening section is formed in a submicron order size.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device with an isolation region between elements.

(Prior Art) Figures 2 rat to fdl are process charts showing a commonly used method of forming grooves in a silicon substrate. First, a silicon oxide film 1 is formed on a silicon substrate 1 using a thermal oxidation method.
2 (see the same figure (al)). Next, a resist 13 is applied onto the silicon oxide film 12, and the resist 13 is removed from the desired groove pattern portion on the silicon substrate 11 (see the same figure (bl # [ ).

After that, using the resist 13 as a mask, the silicon oxide film 12 is
is anisotropically etched using a fluorine-based gas, and the resist 13 is further removed (see c1 in the same figure).

Subsequently, using the silicon oxide film 12 as a mask, the silicon substrate 11 is anisotropically etched with a chlorine-based gas to form a groove 14 in the silicon substrate 11 (see FIG. 4(d)).

The above-mentioned method is also used, for example, in a semiconductor device disclosed in Japanese Patent Laid-Open No. 58-182, in which a polycrystalline semiconductor region and an insulator region are overlapped in a groove provided as an element isolation region. embedded in.

(Problem to be solved by the invention) However, when forming grooves in a silicon substrate using the above method,
As the opening width of the groove becomes narrower, undercuts, as shown in FIG. 3, become a problem. As shown in FIG. 4, this undercut phenomenon occurs when reactive ions 15 collide with the sidewalls or corners of the insulating film 12 that serves as an etching mask on the silicon substrate 11, and the direction of the ions' travel is bent, causing the (i) This phenomenon is said to occur when the grooves collide with [.This phenomenon becomes noticeable when the opening width of the groove becomes submicron.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which undercuts do not occur even when the opening width of the groove becomes submicron when forming a groove in a silicon substrate.

(Means for Solving the Problems) In the method of manufacturing a semiconductor device of the present invention, first, an insulated n film is formed on the silicon substrate to serve as an etching mask for the silicon substrate, and then the insulated n film is etched at a taper angle. forming a groove with
Thereafter, by etching the silicon substrate using anisotropic etching, a groove for an element isolation region having an opening having a tapered angle is formed in the silicon substrate.

(Function) In the present invention, since a groove with a taper angle is formed in the insulating film that serves as an etching mask on the silicon substrate, even if reactive ions hit the side walls or corners of the insulating film during anisotropic etching, It does not collide with the side walls in the trench that is being formed in the silicon substrate, thus preventing undercuts.

Furthermore, when forming grooves for element isolation regions having a taper angle as described above in a silicon substrate, there is a method in which etching is performed twice using chlorine-based gas under different conditions. This can be done with one etching.

(Example) Hereinafter, it will be explained based on the drawings. Figure 1 (al~(d)
1 is a process flow chart showing an embodiment of the present invention. First, a silicon oxide film 2 is formed on a silicon substrate 1 to a thickness of approximately 5 mm using a thermal oxidation method.
(see Figure 1).Next, a resist 3 is applied to the silicon oxide II!ll!2 to a thickness of 9000mm, and desired patterning is performed.At this time, the taper of the resist 3 is Adjust the angle to approximately 45 degrees (see fb in the same figure). Next, using the resist 3 as a mask, C
The silicon oxide film 2 is anisotropically etched using a mixed gas of F4+02 (5%) (see the same figure (C1)).Furthermore, using the silicon oxide M2 left after the etching as a mask, CCl4-02 is etched. Anisotropic etching is performed using a mixed gas of 20% to form a groove 4 in the silicon substrate 1 (see dl in the same figure). The groove has a taper angle of , and the groove has a substantially rectangular shape from the middle part to the bottom part.

(Effects of the Invention) As explained above, according to the present invention, when forming a groove for an element isolation region in a silicon substrate, a groove having a taper angle is formed in an insulating film serving as an etching mask, so that a chlorine-based gas is not used. A groove with a tapered opening can be formed in the silicon substrate with a single etching process, preventing undercuts even if the opening of the desired isolation region groove is submicron. This has a significant effect and greatly contributes to further miniaturization and precision of semiconductor devices.

[Brief explanation of drawings]

Figures 1 (a) to (di are process diagrams showing one embodiment of the present invention, Figures 2 fal to (dl are process diagrams showing a conventional method, Figure 3 is a sectional view showing an undercut, Fig. 4 is a cross-sectional view showing an undercut generation i structure. 1.11...Silicon substrate, 2,12...Silicon oxide film, 3.13...Resist, 4, 14 Groove for isolation region between elements. 15...Reactive ion.

Claims (1)

[Claims] An insulating film serving as an etching mask for the silicon substrate is formed on the silicon substrate, a groove having a tapered angle is formed in the insulating film, and then the silicon substrate is etched using anisotropic etching. A method for manufacturing a semiconductor device, comprising forming a trench for an element isolation region in the silicon substrate, the opening of which has a tapered angle.