JPS6242382Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a circuit whose purpose is to detect a singular state existing in a part of a signal and obtain a binary output.

Conventionally, there is a method of using a threshold as a means for detecting a singular state in which a portion of such a signal exists. This method compares a signal with a homogeneous signal (threshold) that has a certain critical value, and attempts to determine the existence of a singular state when the magnitude relationship between the signal and the threshold is reversed. It is something to do.

Such thresholds generally include fixed level thresholds and floating level thresholds. A fixed level threshold is one in which the threshold has a constant value regardless of the magnitude of the signal, as illustrated in FIG. 1.

FIG. 1 shows a case where the signal is, for example, a video signal from a television camera regarding an object, a singular part a of the signal corresponding to a flaw existing on the object is detected, and this is extracted as a binary output. ing. The threshold value in this case has a fixed constant value as shown in the figure. Such a detection method is capable of stably detecting a singular part when the signal level or threshold changes due to changes in the light intensity of the subject, changes in the characteristics of the sensor (TV camera) depending on the ambient temperature, variations in electrical characteristics between devices, etc. Not only is it impossible to do so, but in some cases the very existence of the signal
Undetectable results occur. Figures 2 to 4 illustrate such cases, with Figure 2 showing a case where the singular part cannot be detected, and Figures 3 and 4 showing a case where the signal itself cannot be detected. Indicates a case where this is not possible.

The method using a fixed level threshold has these drawbacks, and therefore, when using this method, not only is the threshold setting extremely delicate, but the ability to detect singular states itself is inevitably reduced. .

The floating level threshold method was devised to overcome these drawbacks of fixed level thresholds, as illustrated in FIG. A floating level threshold is a signal that is amplified or attenuated and then delayed.
This is used as a threshold value and is appropriately superimposed on the signal to detect the singular part b. In this case, the threshold is created based on the signal, so like a fixed level threshold,
It is characterized by the fact that there is little possibility that the detection ability will deteriorate due to changes in the amount of light of the object, temperature characteristics of the sensor, variations in electrical characteristics between devices, etc. However, even with a floating level threshold,
If the mutual relationship between the signal and the threshold value is not appropriate, good results cannot necessarily be obtained. For example, FIG. 6 shows a case where the signal and the threshold are too far apart, so that the singularity c cannot be detected. In addition, if the signal and threshold are too close together as shown in Figure 7, a phenomenon occurs in which chattering-like noise occurs in the binarized output due to noise in the signal and threshold at the end of the signal. occurs. A and C in FIG. 7 show this situation. Therefore, even when a floating level threshold is used, the signal and threshold must be set a certain distance apart, and therefore the ability to detect defects, etc. cannot be said to be sufficient.

In contrast, as shown in Fig. 8A, by setting a certain cutoff level and preventing the binary signal corresponding to the portion below this level from appearing, as shown in Fig. 8C, A method has been proposed that attempts to remove noise signals in low level parts such as a and b in FIG. However, even with this method, it is difficult to remove noise that is close to the signal as shown in c in FIG. 8B.

The present invention attempts to provide a floating level threshold binarization circuit that does not involve such chattering noise at the signal end and can improve the detection ability compared to the conventional floating level threshold. It is something.

FIG. 9 is a block diagram showing the configuration of an embodiment of the present invention. 11 is a circuit diagram showing a specific configuration of the embodiment shown in FIG. 9, and FIG. 12 is a time chart showing the operation of the binarization circuit of the present invention.

In the embodiment shown in FIG. 9, 1 and 2 are delay elements, 3 and 4 are fixed level binarization circuits, 5 is an AND gate, 6 is an attenuation circuit, 7 is an analog switch, and 8 is a comparison circuit. Referring to the time chart in FIG. 12, input signal A is appropriately delayed by delay element 1 to create first signal B. Signal B is further delayed in delay element 2 to produce signal C. Next, the signal A is sliced at a fixed level to obtain a binary signal D. Similarly, the signal C is sliced at a fixed level to obtain the binarized signal E. Next, a signal gate signal F, which is the logical product of the signal D and the signal E, is obtained by the AND gate 5. On the other hand, the input signal A is appropriately attenuated through an attenuation circuit 6. The analog switch 7 creates a signal in which the leading edge of the gate signal F rises with a long time constant and the trailing edge falls with a short time constant, and while this signal is at a high level, the analog switch 7 is conductive. The second signal H is obtained by passing the output of the attenuation circuit 6 and cutting it off when the level is low. The signal H is used as a threshold value for the signal B, and a comparator circuit 8 compares the two to obtain a binarized output G.
At this time, while the analog switch is closed, signal H is forced to a value higher than the low level of signal B by an appropriate value. This prevents noise from occurring in the low level portion of the signal.

FIG. 10 is a block diagram showing the structure of another embodiment of the present invention. Instead of the fixed level binarization circuits 3 and 4 in the embodiment of FIG.
Sample and hold circuits 9 and 11 and comparison circuit 1
0,12 are used. In the case of a video signal, a low level corresponds to a dark part and a high level corresponds to a bright part, so after sampling and holding the low level corresponding to the dark part, the signal A is obtained by adding a constant potential to the sampled and held potential. Alternatively, by slicing B, the signal D or E can be obtained more stably than in the binarization circuit using a fixed level in the embodiment of FIG. The other parts and the time charts between the signals are the same as in the embodiment shown in FIG.

FIG. 11 is a circuit diagram showing a specific circuit configuration of the embodiment shown in FIG. 9. In the same figure, 21,
22 and 23 are amplifiers, 24 and 25 are delay elements, 2
8, 33 are potentiometers, 29, 30, 31
is a comparator, 32 is a NAND gate, 34 is a transistor, and 35 and 36 are diodes.

After the input video signal is amplified by the amplifier 21, the synchronizing signal is removed by rectifying it by the diode 36, and only the video signal of the eye is amplified by the diode 3.
Take out from No. 6 anode. Next, this is AC amplified by amplifiers 22 and 23, and then connected to a delay element 24 and a potentiometer 33, respectively. The input of the delay element 24 is the waveform A in FIG. 12, the output of the delay element 24 is the same waveform B, and the delay element 25
The output also corresponds to waveform C. Since the output of the amplifier 23 is connected to the potentiometer 33, the output of the potentiometer 33 is an attenuated version of waveform A, which is compared with the ground potential by the comparator 29 and converted into a binary value as shown in FIG. A waveform D is formed. Further, the comparator 30 compares the output of the delay element 25, that is, the waveform C, and the ground potential to form a binarized waveform E shown in FIG. Next, the waveform D and waveform E mentioned above are
When the NAND output is determined, an output with a waveform that is an inversion of waveform F in FIG. 12 is obtained. When this is applied to an analog switch composed of a transistor 34 and a diode 35, when it is at a high level, the transistor 34 becomes conductive, and as a result, the attenuated signal A from the potentiometer 33 is grounded and input to the comparator 31. When the voltage level is low and the transistor 34 is cut off, the potentiometer 33
The attenuated signal A from is input to comparator 31.

Therefore, the waveform H shown in FIG. 12 is ultimately applied to one input of the comparator 31 as the output of the analog switch. At the same time, by adding the output of the delay element 24, that is, waveform B, to the other input of the comparator 31 and comparing both inputs, the binarized output waveform G shown in FIG.
is obtained at the output of comparator 31. Note that the potentiometer 28 is for adjusting the bias potential of the amplifiers 22 and 23, and is connected between the positive and negative power supplies, and is generally called centering. By adjusting 33, the high level and low level of waveform H can be set appropriately so that signal H can be adjusted to the most appropriate level state as the aforementioned floating level threshold.

Further, a time constant circuit consisting of a resistor R and a capacitor C is provided between the output side of the NAND gate 32 and the gate of the transistor 34, and a diode D is connected in parallel to both ends of the resistor R. Therefore, when the output of the NAND gate 32 changes from a high level to a low level, the diode D is cut off and the base input of the transistor 34 changes with a delay according to the time constant RC. Therefore, the analog switch does not open instantaneously and the time constant RC
Since the switch gradually becomes open according to , the leading edge of waveform H, which is the output of the analog switch, rises gradually. This state is shown in FIG. 13A. If there is no time constant circuit for R and C,
Depending on the phase relationship between the gate signal F and the input signal A in FIG. 12, the waveform H rises steeply as shown in FIG. As shown in FIG. 13C, an error signal S similar to the singular part may be generated at the leading edge of the comparator output binary signal C. To prevent this, the leading edge of the gate signal F may be delayed, but
This results in ignoring a significant portion of the input signal. Therefore, if the above-mentioned R and C time constant circuits are provided, the rise of the signal H becomes gradual as shown in FIG.
Generation of an erroneous singularity signal S is prevented. on the other hand
When the output of the NAND gate 32 changes from a low level to a high level, the diode D becomes conductive, so the time constant becomes sufficiently small, and the output waveform of the NAND gate 32 is input to the comparator 31 as is.

From the above explanation regarding the embodiment of FIG. 9, FIG. 10, or FIG. The front and rear ends are shortened, so chattering noise is less likely to occur at the input signal ends. Furthermore, the low level of the threshold H is selected to be sufficiently higher than the low level of the signal B, thereby preventing noise from occurring in the low level portion of the signal.
Therefore, according to the floating level threshold binarization circuit of the present invention, it is possible to prevent the generation of noise and to detect with high precision a peculiar part of a signal caused by a flaw or the like on the subject.

From what has been explained above, by using the floating level threshold binarization circuit of the present invention, it is possible to improve the detection sensitivity compared to the normal floating level threshold without generating chattering noise. It will be understood that erroneous binarization can be prevented by the phase relationship between the gate signal and the input signal. When an object is observed with a television camera, only about 10% of the defects on the object could be detected using a normal floating level threshold, but by using this invention, 80% of the defects could be detected.
It became possible to detect the extent of

The present invention can be widely applied to binarization circuits. For example, the color detection device is very effective in distinguishing between colors that have low contrast, such as yellow and white, black and gray, and blue and green. As a result of experiments, it was possible to detect defects close to the limit even when there were white defects on a yellow background, so it is thought that this method can be sufficiently applied to color detection devices, color identification devices, etc.

[Brief explanation of the drawing]

FIGS. 1, 2, 3, and 4 are explanatory diagrams showing the operation in the case of a fixed level threshold.
FIGS. 5, 6, 7 and 8 are explanatory diagrams showing the operation of conventional floating level thresholds. FIG. 9 is a block diagram showing the structure of one embodiment of the present invention, FIG. 10 is a block diagram showing the structure of another embodiment of the present invention, and FIG. 11 shows the specific structure of the embodiment of FIG. FIG. Further, FIG. 12 is a time chart showing the operation of the floating level threshold value binarization circuit of the present invention, and FIG. 13 is a time chart showing the operation when a time constant circuit is added to the gate signal generating means. 1, 2... Delay element, 3, 4... Fixed level threshold value binarization circuit, 5... AND gate, 6...
Attenuation circuit, 7... Analog switch, 8... Comparison circuit, 9, 11... Sample hold circuit, 1
0, 12... Comparison circuit, 21, 22, 23... Amplifier, 24, 25... Delay element, 28, 33...
Potentiometer, 29, 30, 31... Comparator, 32... NAND gate, 34... Transistor, 35... Diode, R... Resistor, C... Capacitor, D... Diode.

Claims (1)

[Scope of utility model registration request] means for creating a first signal delayed from the input signal; means for creating a second signal delayed from the first signal; and a logical product of the respective binary signals of the input signal and the second signal. attenuating means for attenuating the input signal so that it has appropriate high and low levels; and means for attenuating the input signal so that it has appropriate high and low levels. means for creating a third signal by controlling an analog switch into which the output from the attenuating means is input by a signal falling with a short time constant;
and means for comparing the first signal and the third signal and generating a binarized output corresponding to a period in which the level of the first signal exceeds the level of the third signal. Floating level threshold 2 characterized by
Value circuit.