JPS6242298B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to reading a document by a reading and sorting device to select the pocket into which the document is to be sorted, and in particular to defining fields of OCR, MICR and OMR data within the document. The reading and sorting device (reader sorter) is
It has multiple heads for reading information fields on documents such as checks that have MICR and OCR data fields. This information is read by the reader-sorter, processed by the controller, and sent to the central processing unit CPU, which selects pockets for sorting documents under software control. Information on a document is organized as multiple columns. One column contains control characters, followed by a group of data characters, and then other control characters. Have one reader/sorter on one subsystem
Prior art systems, such as Honeywell's H200 data processing system, transmit every character read from a document to a CPU via a controller. A time consuming software routine examines all of the characters received from the reader sorter, distinguishing control characters from data characters and defining each column. Accordingly, a primary object of the present invention is to provide improved performance to document classification systems. Another object of the present invention is to provide a document classification system with an improved apparatus for defining each column read from a document by a reader sorter. Yet another object of the present invention is to provide a document sorting system with an improved apparatus for translating queue symbols into queue column identifier characters. Another object of the present invention is to provide a document classification system with an improved apparatus for identifying queue symbols and pseudo-queue field identifiers to define fields read from a document. Three important terms used in the text above and below are defined below. “Queue symbol”: A character carried on a document that indicates the presence of a subsequent data field. “Queue field identifier”: A code recognizable by the CPU into which the code of the queue symbol is translated. “Pseudo-queue field identifier”: A code that can be identified by the CPU, into which the control signals generated by the reading device are interpreted, and that indicates when a document is being read, such as at the beginning of a document, at the end of a document, etc. Represents the status of the reader. The novel features which characterize the invention are pointed out in the appended claims. However, the invention itself may best be understood by reference to the following description of its structure and operation, taken together with the accompanying drawings. The document processing system includes a central processing unit CPU, a main memory, and a microprogrammed device controller MDC, all commonly coupled to a system bus. The reader sorter is also MDC
Reader Sorter Adapter RSA connected to
connected to. Character codes are generated within the reader/sorter,
Sent to RSA. This character code contains the information read from the document and indicates the active reading head and the position of the document relative to this reading head. This includes the start of document, end of document, reading area 2 (RA2) character code, and a character code that identifies the active head reading the document. The character codes read from the document are data characters and special symbol characters, which are translated in RSA to match the codes used by the CPU. The information on the document is organized into columns. Certain character codes read from the document are translated as queue field identifier QFI characters. The character code read from the document is also translated into a character identifier code, which typically represents an alphabetic letter, number, dash or space, or special symbol. The character code generated by the reader sorter is also translated into a character identifier code to represent the pseudo-queue field identifier PQFI character. The QFI and PQFI characters identify the boundaries of each column. The MDC includes a control store for storing firmware routines and operations for receiving translated character codes and character identification codes for selecting QFI characters from the translated character codes and PQFI characters from character identifier codes. Logical unit ALU
and a scratchpad memory for storing the QFI or PQFI character codes that begin and end each field in address storage locations. Additionally, the controller under control of the firmware generates a count of the number of positions from the PQFI character that identifies the active head that the character received following the QFI or PQFI start character. The controller also generates a count of the number of positions from the PQFI character that identifies the active head that the character was received immediately before the QFI or PQFI end character. These counts are scratch padded.
Stored in address storage locations in memory. Additionally, the controller inspects all translated character codes and character identifier codes for illegal character codes and stores them in the scratchpad memory address storage location along with the location in the field of the illegal character.
Remembers the count of illegal characters in the field. FIG. 1 shows a central processing unit CPU 2, a main memory 4, and a plurality of peripheral device controllers 12, all commonly coupled to a system bus 16.
and a plurality of microprogrammed device controllers MDC6. Connected to the MDC 6 is a reader/sorter adapter 1 (RSA1) 8 or a reader/sorter adapter 2 (RSA2) 18.
Reader/sorter device 1 (RSD-1) 10 is RSA1 8, which can be Honeywell's model DHU9840 device.
Connects to Honeywell Model 234-0 or 236
Reader/sorter device 2 (RSD-2) 2
0 is connected to RSA2 18. The MDC 6 is disclosed in U.S. Pat. No. 4,003,033, ``Architecture for a Microprogrammed Device Controller,'' which is incorporated herein by reference. The document processing system sequentially reads documents from up to four reading heads in a reader/sorter device 110. The first read head is MICR
(Magnetic Ink Character Recognition) reads the characters, the second read head reads the OMR (Optical Symbol Recognition) words, the third and fourth read heads read the OCR
(Optical Character Identification) Read characters. Information from the document is read into main memory 4 over system bus 16 via RSA 1 8 and MDC 6;
Processed by CPU2. The selected characters are stored in main memory 4 for further processing. CPU 2 processes the information under program control and sends return signals to reader sorter device 1 via system bus 16, MDC 6 and RSA1 8.
10, thereby displaying the pocket in which the document is stored. The MDC 6 is a microprogrammed peripheral controller that performs general purpose control functions such as executing system bus sequences, providing command storage, transmitting and editing data, and establishing the overall flow of execution of commands. RSA1 8 is reader/sorter device 1 10
Contains all the specialized hardware needed to interact with the In this embodiment, the relationship between the MDC6 and the RSA18 will be explained. RSA2 18 and reader/sorter device 2 20 are connected to MDC6 in the same way as RSA18.
It turns out that it works. In FIG. 2, RSA1 8 connects signals XLTDT0- to 512 addressable memory locations.
It includes a translation and queue marker table random access memory (RAM) 38 for storing character codes sent to multiplexer 42 as signal ADPDSO-7+02 and to MDC 6 as signal ADPDSO-7+02. Document character code signals are signals RSDAT1 to 7.
(7 bits) is applied to the receiver/multiplexer 32 of the RSA1 8 and applied to the address selection terminal of the RAM 38 to select the address storage location in which to store the equivalent character code for transfer to the MDC 6. A code identifying the particular head reading the document is stored in the translation eye register counter 34.
is memorized. The signals XLTQD2, 3+00 applied to the address selection terminals of RAM 38 indicate that the RAM 38 stores the corresponding character associated with a particular head.
128 address storage locations in 38 are selected.

[Table] RAM 38 is initially loaded with character codes used by CPU 2. These character codes include style characters, font selection characters, and data characters, and are modified as required by the classification application at hand.
It can be ASCII, EBCDIC, binary coded decimal, or any other suitable code. Load data register/counter 30 provides output signals LDDAT0-7-00 to receiver multiplexer 32. Counter 30 is initially set to hexadecimal zero and is then set to 128 under firmware control.
address location. Similarly, counter 34 is reset to binary zero and incremented once every 128 character transfer to write a 512 character code to RAM 38. The character code is MDC6 to signal ALUOT0-7
+00 to the status selection register counter 36, and the signal RSSEL0-7+00 to the RAM3.
given to 8. Therefore, RAM 38 is initially loaded with characters requested by CPU 2. During document reading, characters are translated into the required code by RAM 38. Signals LDDAT0-7+00 are applied to reader/sorter 10 to indicate the pocket in which the document is stored. Reader sorter adapter 1 8 is MDC
6 to the control logic 44.
ADPPLS+00, ADPENB-00, ADPCD1-3+
Controlled by 00 and LODAS1-10. Output signals PCDEC1, 3, 5 and 6 initiate the required cycles of loading, clearing, writing and boosting as shown in the timing diagram of FIG. The character code signal RSDAT1-7+00 and the translation representation eye signal XLTQD1-3+00 are applied to the address selection terminal of the character decoding index table 40. Output signal DATDC0-7+00 is encoded as RSA1
8 indicates the type of character received, ie, if it is a numeric character, alphabetic character, control character, or formatting character. Signals UPIRO4 and UPIRO5 are generated by MD6 and applied to select terminals of MUX 42 to send selected MUX 42 output signals to MDC6. Signal given to RCVR/MPX32
ATEST2+00 and ATEST2-00 are generated by control logic 44 to select either a load operation or a translation operation. According to Figure 3, the translation and queue marker table
RAM 38 is a random access memory RAM 106, 10, which is a 2101A type memory circuit described in Intel's Data Catalog 1978, pages 3 to 26.
Including 8,110,112. This catalog is published by Intel, 3015 Bowers Street, Santa Clara, California, USA. During the document reading operation, the character code signal is sent to the reader/sorter 10 on signal lines RSDAT1-7+OR.
received from the receiver/multiplexer 64,
68, 72, 78, 82, 86, 90. Control signal ATEST2-00 is a logical 1 for document reading operations. Output signal RSDAT1-7+00 is RAM
106, 108, 110, and 112 are applied to the address selection input sides. Counter 34 of translation representation eye register/counter 34 provides a signal XLTQD2+00 which enables RAMs 106 and 108 or RAMs 110 or 112. signal
XLTQD3+00 is address selection terminal 128
give to Address locations 000 through ₁₂₇₁₀ of RAMs 106 and 108 store characters that decode characters on documents read by head 1.
Address locations 12810 through ₂₅₅₁₀ of RAMs 106 and ₁₀₈ store characters that decode characters on documents read by head 2. Similarly,
RAM 110 and 112 address location 000
Address locations 128-10 through _255-10 are associated with head 3 and address locations _128-10 through _255-10 are associated with head 4. Signals that are the outputs of RAM106 and 108
XLTDT0-7+0A and RAM110 and 112 signals XLTDT0-7+0B are wired OR circuit 118
132. Output signal XLDT0-7
+00 is applied to input terminal 1 of MUX 42. First, RAM106, 108, 110, 11
2 is a data processing system of a document processing system;
That is, character codes compatible with the CPU 2, main memory 4, and MDC 6 are loaded. This character code includes data characters as well as control characters. This load operation requires a logic zero control signal.
Signal line with ADPENB-00 and LODAS1-10
It is started by MDC 6 sending hex 05 on ALUOT1-7+00 to control logic 44. Therefore, the decoder 54 is enabled and the clock
Output signal ASIDCO-00, which is forced to a logic zero value on the rising edge of strobe signal CLKSTB, enables loading of register 56. signal
Since ALUOT5+00 and ALUOT7+00 have a logical value of 1, the output signal ATEST2+00 has a logical value of 1. Signal ATEST2 which is the output of inverter 92
−00 is a logical zero. Therefore, the output signal
Receiver/Multiplexer 64, 68, 72, 78, 82, 86, 90 as RSDAT1-7+00
Inverter 62, 66, 70, 76, 8 via
Load signal which is output of 0, 84, 88
Select LDDAT1-7-00. This is shown in clock cycle A of the timing chart of FIG. In the next clock cycle (cycle B, Figure 4), hex 00 is the signal line.
ALUOT0-7+00 is a logic zero signal ADDENB
-00 and ADPPLS+00, thereby enabling the decoder 52. Signal ADPPLS
−00 becomes a logical value 1 as the output of the inverter 51. A logic zero output signal PCDEC6-01 is applied to the LOAD terminals of load data registers 58 and 60. Signal ADPCD1+00 has a logical value of zero, and signals ADPCD2+00 and ADPCD3+00 have a logical value of one. Since the signal ALUOT0-7+00 is a logical zero, the hexadecimal number 00 is in registers 58 and 6.
Set to 0. The signal ALUOT4-7+00 is the clock signal in Figure 4.
At a logic zero during cycle C, the signal from MDC6 forces the PCDEC1-01 output signal of decoder 52 to a logic zero. This is leader sorter 1
Translated character code read by head 1 of 0
Force counter 102 to hexadecimal zero to decode address locations in RAM 106 and 108. During cycle D of FIG. 4, control signal PCDEC5-01, which is the output of decoder 52, is forced to a logic zero value and counters 94 and 96 are connected to signal bus ALUOT0.
-7+00 to make it possible to store the first translated character code received from the MDC6. In the next clock cycle (cycle E in Figure 4), D-flop 104 outputs signal PCDEC3.
When −01 is a logic zero, it is set at the same time as the CLOLK signal rises, thereby causing the write pulse signal
Force WRTXLT−00 to logic zero. On the next clock cycle (cycle F in Figure 4), the data stored in status select registers 94 and 96 is transferred to RAMs 106 and 108 at address location 000 via signal lines RSSEL0-7+00.
written to. In the next cycle (cycle G in FIG. 4), the control signal ADPPLS+00 becomes a logic 1, thereby enabling the decoder 50 and causing the signal
PCDEC6-02 is forced to a logic zero, thereby incrementing loadator register 60 to 001;
In the next cycle (cycle H in FIG. 4), the next data character is loaded into registers 94 and 96 and cycles D, E, F, G are repeated until registers 58 and 60 store hexadecimal 7F. That is,
Signal LDDAT1-7-00 is a logical 1 indicating address location ₁₂₇₁₀ . On the next incremental load data register clock cycle (cycle G in Figure 4), register 60's shift signal LDDTCY-01 is forced to a logic zero;
The load data register 58 is incremented on the next rising edge of the CLOCK signal. For this reason, the signal
Force LDDAT0+00 to logic 1 and signal
Force LDDAT1-7+00 to logical zero. Also, the shift signal which is the output of the inverter 99
LDDTCY+01 is applied to NAND gate 98. Since the signal LDDAT1-3+00 is also a logic 1 during this cycle, the output signal is a logic zero.
LDDTCY-03 is applied to the PT terminal of counter 102. This increments the counter 102 and forces the output signal XLTQD3+00 to a logic one. This allows selection of address locations 128 ₁₀ to 255 ₁₀ in RAMs 106 and 108. This condition is shown in cycle I of FIG. The logic one signal LDDAT0+00 and the logic zero signal LDDAT1+00 indicate to MDC 6 that the head 1 character sequence is complete and registers 58 and 60 store address location 000. When the character sequence of head 2 is completed, counter 1 is
02 is NAND gate 98 and NOR gate 10
0 to force signal XLTQD2+00 to a logic one and signal XLTQD3+00 to a logic zero. On the next clock cycle, signals LDDAT0+00 and LDDAT1+00 go to logic zero, indicating to MDC 6 that the head 2 character sequence is complete. The logic 1 signal XLTQD2+00 selects RAMs 110 and 112, and the sequence selects heads 3 and 4.
Iterated over character sequences. When counter 102 is incremented, signal XLTQLD1+00
is forced to a logical value of 1. This indicates to MDC6 that the loading operation is complete and that the signal ATEST2+00 is output as shown in cycle J of Figure 4.
is forced to a logical zero in register 56. If signal XLTQD1+00 is a logic zero, in cycle J of FIG. 4, signal PCDEC3-01 is forced to a logic zero by MDC6, memory-write block 104 is set, and cycle It is a data cycle. PROMs 114 and 116 of character decoding lookup table 40 receive character code signals RSDAT1-7+00 and translation representation eye signals XLTQD1-3+00 and provide output signals DATDC0-7+00 as described above. FIG. 5 is a flowchart of the firmware routine in MDC6 that processes character codes received from RSA18. Firmware routine RSA1-QF1 200 analyzes character codes for control characters, queue field identification characters, or data characters. firmware routine 20
0 identifies the queue symbol along with the beginning of the document and the end of the document character, thereby defining the data column. The beginning and end of column characters are control characters or queue symbols. The queue symbol is RAM1 in Figure 3.
06, 108, 110, 112 are translated into queue column identifier characters as output. The firmware initially selects signals DATDC0-7+00, which are the outputs of MUXes 114 and 116, which are applied to input terminal 3 of MUX 42.
MUX42 output signal ADPDS0-7+02 is MDC
6 is given. Decision block 202 is a signal
ADPDS0+02 is checked and if this signal is a logic 1, it will display a control character. At this time, the firmware examines signals ADPDS1-7+02 in decision block 214 for end of document character (EOD). If the control character is an EOD character, then at block 216 a hexadecimal number 84 is stored in the end of column queue (FCQ) character address location of scratchpad memory 300 of FIG. Decision block 218 determines whether read head 2 (RA
2) Check the signal ADPDS1-7+02 for the control character. If an RA2 control character is detected,
At block 220, the hexadecimal number 82 is stored at the FCQ address location. RA2 is called with a pseudo-queue field identifier indicating that an area in the document was intentionally skipped and the read head was reactivated. Decision block 244 tests signal ADPDS1-7+02 for the beginning of the document (SOD) control character. If this control character is not an SOD character, then
This is the read head identification (HID) character and in block 222 the hexadecimal number 81 is stored in the FCQ address location. If decision block 244
If a SOD character is detected, firmware routine SIDQFIEXIT 206 is called. If decision block 202 indicates that the received character is not a control character, that is, the signal
If ADPDS0+02 is a logic zero, the firmware outputs MUX4 as signal XLTDT0-7+00.
RAM10 given to input terminal 1 of 2
Select outputs 6, 108, 110 and 112. Decision block 204 examines signal ADPDS0+02, where a logic one signal indicates a queue symbol and a logic zero indicates that an information character has been read. Once the information character is read, firmware routine SIDQFIEXIT 206 is called. Scratchpad memory 30 in Figure 6
The field data end position (FDEP) count, stored at zero, is incremented at block 208. FDEP stores a count of character positions, with the last character in this column starting from the first character. Decision block 210 tests whether the received character is an illegal character. If this is not an illegal character, then firmware subroutine SIDQFIEND 212 initiates a sequence in which this character is loaded into main memory 4 and RSA1 8 is ready to send the next character to MDC 6. After the control character has been identified and the appropriate code written to the FCQ address location, firmware routine SIDQFI 200, 224 is called which determines at decision block 226 that if the control character or queue field identifier character was already Check to see if it was received. If not,
Firmware routine SRSA1-QFIB230
is called to initialize the basic fields. Block 232 initializes a number of address locations in scratchpad memory.
The FDEP address location is initialized to hex FF, and the field data start position (FDSP) address location is initialized to hex 01. Also, read heads in operation are identified by the number of erroneous characters in the field (NECF) address location. The firmware subroutine SRSA1-QFIA 234 in block 236 stores the hexadecimal 81 contents of the FCQ address location in the field start queue (FOQ) address location if the first character is a HID character, and sets the FCQ address location to the start of field queue (FOQ) address location. Clear to hex 00. Also cleared are the first, second, and third erroneous character positions (ECPs) and address locations.
This is the lower bit position of the NECF address location. Block 238 sets an indication that the first control character of the document has been received and frees the queue field. Routine SIDQFIEXIT 206 then increments the FDEP address location to hex 00 at block 208. The decision block 204 is the RAM 10 in FIG.
Recognizing that a queue field identifier code from 6, 108, 110, 112 has been received, block 240 stores the character code at the FCQ address location and sets bit position 0 to a binary zero. Decision block 242 examines the queue field and
If this is open, routine SQFI -
Call WRT244. SQFI-WRT244 is
Scratchpad Memory 300 Address Locations FOQ, FCQ, FDSP, FDEP Completely Assembled Queue Field Identifier Blocks in Memory 4
This is a subroutine that is stored in Decision block 252 tests whether eight characters have been stored at the address location. If eight characters are stored, block 254 transfers the eight characters to memory 4, and block 258 causes the firmware to store block 246.
Return to If the result of decision block 252 is found to be negative, a data abort flag is set at block 256 to indicate that the QFI field was not sent to main memory 4. Block 25
8, the firmware is block 246.
Return to Here, the contents of FDEP are hexadecimal 2
is added, and this answer is stored in the address location of the field data start position (FDSP) in the scratchpad memory 300. This state is the next in the document.
Defines the position of the first data character in the QFI field. Firmware routine SRA1-QFIA23
4 is called and, in block 236, the contents of address location FCQ are stored in address location FSQ, and in block 208, the contents of address location FCQ are stored in address location FDEP.
The content of will be improved. Decision block 210 again checks for illegal characters. Legal queue field identifier characters are stored in main memory 4 in a firmware sequence beginning with routine SIDQFIEND 212. Subsequent data characters are read and increment address location FDEP of block 208 as described above, so that address location FDEP stores the count of this location and the current character in the data field is from the first identifying character. If decision block 202 detects a control character, such as an end-of-document (EOD) character code, hexadecimal 84 is loaded into address location FCQ of block 216 and firmware routine SIDQFI 200, 244 is called. Decision block 226 is a firmware routine.
Call SQFI-WRT244. Decision block 242 has already determined the address location.
It calls firmware routine SQFI-WRT 244 which sends the contents of FCQ, FSQ, TDEP, FDSP, error count and error character position to main memory 4 and returns to block 246. Here
The EOD character is firmware routine SQFI.
Initiating a call to WRT 244, this routine sends to main memory 4 the contents of the address locations FCQ, FSQ, FDEP, FDSP, as well as the error count and the error character location. Routine 244 returns to call firmware routine SRSA1-QFIB 230. Detection of an EOD from the device means that no more data characters from the document are transferred and therefore no more data characters are transferred from the document.
It also indicates that the formation of QFI is not suggested. If decision block 210 displays illegal characters, firmware subroutine SIDQFI
-510,264 is called. block 266
, the number of erroneous characters in a field (NECF) is increased. At decision block 268, the NECF is checked for eight or more errors. If there are eight or more errors in this field, the routine ends and firmware routine SIDQFIEND21
2 is called. If decision block 268 indicates eight or fewer errors, decision block 270 checks for four or fewer errors. If NECF displays four or fewer errors, decision block 27
4 checks for one or three errors, and decision block 276 checks for one error. Block 278 stores an indication of the first erroneous character position (FECP), block 280 stores an indication of the second erroneous character position, block 282 stores an indication of the third erroneous character position, and block 280 stores an indication of the third erroneous character position. The software routine SIDQFIEND 212 is called. FIG. 6 is a block diagram of the microprogrammed device controller 6. Character signals ADPDS0-7+02 are received from RSA18 via arithmetic logic unit (ALU) 304 and multiplexer (MUX) 302 and stored in scratchpad memory 300. Information from Scratchpad Memory 300 is MUXed
302 and ALU 304 to register 306. The information stored in register 306 is
It is sent onto system bus 16 via MUX 302 and bus interface register (BIR) 308. Signal ALUOT0-7+00 is system bus 16
From BIR308, MUX302 and ALU304
is sent to RSA18 via. Control signals ADPPLS, ADPPENB, ADPCD1−
3, LODAS1, UPIRO4, and UPIRO5 are generated from microwords read from microprogram control store 310, stored via registers 312, and decoded by UP code decode 314. clock generator 316
is the signal CLOCK and
Generate CLKSTB. Figure 7 shows the MICR column, OMR column, OCR1 column,
A typical string from a document with an OCR2 field is shown. The Start of Document (SOD), Start of Head (SOH), Reading Area 2 (RA2), and End of Document (EOD) characters are pseudo-queue field characters.
The queue symbol (QS) characters are translated into queue field identifier (QFI) characters in the translation and queue marker table 38 of FIG. The display SOH--QS indicates that the beginning of the head is stored at address location FOQ and the queue symbol is stored at address location in scratchpad memory 300. A SOH-QS indicates the beginning of the first reading area of this head. B QS-SOH indicates the end of the read area for this head. C QS-RA2 indicates the beginning of the first read area of this head. DRA2-QS indicates the beginning of reading area 2. E QS-EOD displays the first reading area of the document. F SOH - SOH indicates that QS characters and data have been detected for this head. G SOH-RA2 indicates that no data or QS characters were detected in the first read area of this head. H RA2-SOH indicates that no data or QS characters were detected in the second read area of this head. IRA2-EOD indicates that no data or QS characters were detected in the last reading area of the document. J SOH-EOD indicates that no QS characters were detected in the document or final reading head(s). Address location when examined by CPU2
FOQ and FCQ contents are reader sorter 10
Displays the status of document reading by. FIG. 8 shows the contents of PROMs 114 and 116.
Address locations are shown in hexadecimal form. Signal XLTQD1-3+ given to address terminal
00 and RSDAT1~7 are 12 shown in Figure 8.
Select the 10 least significant bits of the bit hex address location. The 11th and 12th bit positions are binary zeros. The 9th and 10th bit positions indicate the active read head and are an indication of the status of signals XLTQD1+00 and XLTQD2+00. The contents of the selected address location appear on eight signal lines DATDC0-7+00 and are shown in hexadecimal form in FIG. The chart below shows the bitwise interpretation of the contents of the selected address location.

[Table] As an example, the contents of address location hexadecimal number 17A are
It is hexadecimal C4. The hexadecimal number 17A, displayed as a binary number, is 0001 0111 1010. The 11th and 12th bit positions contain binary 00 and are ignored.
The 10th and 9th bit positions contain the binary number 01,
Each character indicates that it has been read by the reading head 3. Hexadecimal number C4, expressed as binary numbers 1100 0100, indicates the character of reading area 2 associated with head 4. This is an indication to the MDC 6 that head 3 has completed reading the OCR1 field and the document is sent to the reading station of read head 4 which reads the OCR2 field. Below is a table identifying the logic elements of this example.

Table: Having shown and described the preferred embodiments of this invention, those skilled in the art will be able to make many changes that affect the described invention but still fall within the scope of the following claims. It will turn out to be.

[Brief explanation of the drawing]

Figure 1 is an overall block diagram of this system, Figure 2 is a block diagram of the reader/sorter adapter, Figure 3 is a detailed logic circuit diagram of the reader/sorter adapter, and Figure 4 is the timing diagram for loading data operations. Figure 5 is a flow chart showing the firmware sequence in the microprogrammed element controller identifying each column.
Figure 7 is a block diagram showing the microprogrammed device controller;
A diagram illustrating the character sequences received by the adapter, and FIG. 8 is a diagram illustrating the contents of the programmable read-only memory. 2...Central processing unit (CPU), 4...Main storage device,
6...Multiple device controller (MDC), 8, 18...
Reader Sorter Adapter (RSA), 10,2
0...Reader sorter device (RSD), 12...Peripheral device controller, 14...Peripheral device, 30...Load data register/counter, 32...Receiver/
Multiplexer, 34...Translation representation register/counter, 36...Situation selection register/counter, 3
8... Translation queue marker table (RAM), 40... Character decoding index table, 42... Multiplexer (MUX), 4
4...Control logic.

Claims (1)

[Scope of Claims] 1. A data processing device CPU, a document character reader for providing a group of consecutive signals representing symbols on a line of a document, and a document character reading device for receiving the signal group and processing information on the document. A document processing device comprising an adapter device for translating into respective character codes recognizable by said CPU, and a controller for receiving and assembling said character codes for subsequent transfer to said CPU, said signal group (a) a data symbol; (b) a queue symbol that identifies the beginning and end of consecutive data symbols on said document; (a) the adapter comprises (i) (ii) said data symbol is a data character code; (ii) said queue symbol is a queue entry identifier QFI code; and (iii) said control signal is a queue entry identifier QFI code.
(b) the controller is configured to: , examines each character code as it is received from said adapter, and examines the pair of QFI and PQFI codes received consecutively.
to a particular memory location in the scratchpad storage device, regardless of the order in which it was received, thereby causing the contents of the two memory locations to be
Document processing characterized in that, upon transfer to a CPU, a specific code stored therein allows the CPU to immediately identify the type of data symbol on a document that the data character code represents. Device.