GB2064181A - Character Processing in Document Readers - Google Patents

Abstract

A document Reader and Sorter 10 reads characters including data and formatting symbol characters read from a document and control characters generated by the Reader Sorter and feeds the characters to an Adapter 8. Certain characters may be identified as queue field identifiers (QFI) by the user via software. These are usually the formatting characters. The control characters are identified as pseudo queue field identifiers (PQFI). QFI and PQFI characters are received by a Multiple Device Controller 6 and allow the firmware to identify the length of the data fields, the head from which the characters were received, and any special conditions associated with reading of a data field. The reader sorter adapter 8 includes a translation and queue marker table RAM and a character decode lookup table PROM, through which the characters are passed before being forwarded to the MDC 6. <IMAGE>

Description

SPECIFICATION Character Processing in Document Readers This invention relates generally to the reading of documents by a reader sorter, for selecting a pocket into which the document is sorted; and more specifically, to the defining of OCR (optical character recognition), MICR (magnetic ink character recognition) and OMR (optical mark recognition) data fields within the document.

A reader sorter has a number of heads for reading fields of information on documents, such as checks having MICR and OCR fields. The information is read by the reader sorter, processed by the controller, and transferred to a central processor unit which, under software control, selects a pocket for sorting the document. The information on the document is organized in fields. A field may include a control character followed by a group of data characters, followed by another control character. The prior art systems having a reader sorter on a subsystem transmit all of the characters read from the document through a controller to a central processor unit. Time consuming software routines examined all of the characters received from the reader sorter, differentiating control characters from data characters and defining the fields.

The object of the invention is thus to provide a document sorting system with improved performance.

Accordingly, the invention provides a document processing system comprising: a reader sorter device which reads a document and generates a sequence of character signals comprising information characters read from the document and control characters generated by the reader sorter device; an adapter coupled to the reader sorter device and responsive to the character signal sequence to generate translated character signals identifying queue field indentifier characters among the information characters and to generate character indentifier signals identifying the control characters as a pseudo queue field identifier characters; and a controller coupled to the adapter responsive to the translated character signals identifying queue field identifier characters and to the character identifier signals identifying pseudo queue field identifier characters to designate the boundaries of a field, for transfer to a main memory, and further responsive to the translated character signals to generate a start position character count and an end position character count in the queue field for transfer to the main memory.

A document processing system embodying the invention will now be described by way of example, with reference to the drawings, in which: Figure 1 is an overall block diagram of the system.

Figure 2 is a block diagram of the reader sorter adapter.

Figure 3 shows the character sequence received by the reader sorter adapter.

Figure 4 is a timing diagram showing load data operation.

Figure 5 is a flow diagram of the firmware sequence in the microprogrammed device controller which identifies the fields.

Figure 6 is a block diagram of the microprogrammed device controller.

Introductory Summary A document processing system includes a central processor unit (CPU), a main memory, and a microprogrammed device controller (MDC), all coupled in common to a system bus. A reader sorter is coupled to a reader sorter adapter (RSA) which, in turn, is coupled to the MDC.

Character codes are generated in the reader sorter and transferred to the RSA. The character codes include information read from the document and also indicate the active read head and the position of the document relative to the read head. Included are start of document, end of document, read area 2 (RA2) character codes as well as character codes identifying the active head reading the document.

The character codes read from the document are data characters and special symbol characters, and are translated in the RSA to conform to the codes used in the CPU.

The information on the document is organized in fields. Certain character codes read from the document are translated in the RSA as queue field identifier (QFI) characters. The character codes read from the document are also translated into character identifier codes which indicate typically, an alphabetic character, a numeric character, a dash or space, or a special symbol. The character codes generated by the reader sorter are also translated into certain character identifier codes designating pseudo queue field identifier (PQFI) characters.

The QFI characters and PQFI characters identify the boundaries of the field.

The MDC includes a control store for storing firmware routines; an arithmetic logic unit (ALU) receiving the translated character codes and the character identifier codes for selecting the QFI characters from the translated character codes and the PQFI characters from the character identifier codes, and a scratch pad memory for storing the QFI or PQFI character codes starting and closing the fields.

In addition, the controller, under firmware control, generates a count of the number of positions the character received, following the QFI or PQFI starting character, is from the PQFI character identifying the active head.

The controller also generates a count of the number of positions the character received, immediately preceding the OFI or PQFI closing character, is from the PQFI character identifying the active head. These counts are stored in the scratch pad memory.

In addition, the controller checks all translated character codes and character identifier codes for illegal character codes and stores, in address locations in scratch pad memory, a count of the number of illegal characters in the field with the location in the field of the illegal characters.

Detailed Description Figure 1 shows the Document Processing System, which includes a central processor unit (CPU) 2, a main memory 4, a plurality of peripheral controllers 12, and a plurality of microprogrammed multiple device controllers (MDC) 6, all coupled in common to a system bus 16.

A Reader Sorter Adapter 1 (RSA1 ) 8 or a Reader Sorter Adapter 2 (RSA2) 18 are coupled to the MDC 6. A Reader Sorter Device-1 (RSD-1) 10 is coupled to the RSA1 8, and a Reader Sorter Device-2 (RSD-2) 20 is coupled to the RSA2 18.

The Document Processing System reads documents in the Reader Sorter Device-1 10 sequentially from up to four read heads. A first read head reads MICR (Magnetic Ink Character Recognition) characters, a second read head reads OMR words (Optical Mark Recognition) and third and fourth read heads read OCR (Optical Character Recognition) characters. The information from the document is read through the RSA1 8 and MDC 6 onto the system bus 16 to main memory 4, and is processed by the CPU 2. Selected characters may be stored in main memory 4 for further processing.

The CPU 2 processes the information under program control and sends return signals via the system bus 16, the MDC 6, and the RSA1 8 to the Reader Sorter Device-1 10, thereby indicating the pocket into which the document is sorted.

The MDC 6 is a microprogrammed peripheral controller which performs general purpose control functions such as executing system bus sequences, providing command storage, transferring and editing data, and establishing the general flow of command execution. The RSA1 8 contains all the hardware necessary to dialogue with the Reader Sorter Device-1 10. The RSA2 18 and Reader Sorter Device-2 20 operate similarly.

Referring to Figure 2, the RSA1 8 includes a Translation and Queue Marker Table Random Access Memory (RAM) 38 for storing, in 512 addressable locations, character codes which are transferred to a multiplexer 42 as 8-bit signals XLTDT0-7+00, and, in turn, to the MDC 6 as signals ADPDS0- 7+02.

Document character code signals are applied to a receiver/multiplexer 32 of RSA1 8 as 7-bit signals RSDAT 1-7 and are applied to the address select terminals of RAM 38 to select the address locations storing the equivalent character code for transfer to MDC 6. A code identifying the particular head reading the document is stored in a Translation Table Quadrant Register Counter 34. Signals XLTQD 2, 3+00, applied to the address select terminals of RAM 38, select a quadrant of 128 address locations in RAM 38 storing corresponding characters associated with a particular head, thus: Head Character XLTQD Number Field 2 3 1 MICR O 0 2 OMR O 1 3 OCR 1 0 4 OCR 1 1 The RAM 38 is loaded initially with character codes that will be used by the CPU 2.These character codes include format characters, front select characters and data characters, and may be ASCII, EBCDIC, binary coded decimal, or any other appropriate code as required for the current sorting application.

A Load Data Register/Counter 30 feeds signals LDDATO~7+00 to receiver multiplexer 32. The Counter 30 is initially set to ZERO and incremented through 128 address locations under firmware control. Similarly, Counter 34 is reset to ZERO and incremented once every 128 character transfers for writing the 512 character codes into RAM 38.

The character code is applied to a Status Select Register Counter 36 from the MDC 6 via signals ALUOTO~7+00 and applied to RAM 38 as signals RSSEL0-7+00.

RAM 38, therefore, is loaded initially with character codes compatible with the data processing system of the Document Processing System, namely, the CPU 2, main memory 4, and MDC 6. The character codes include data characters as well as control characters.

During the reading of the document, the characters are translated into the required code by RAM 38. Signals LDDAT 0--7+00 are applied to the Reader Sorter 10 and indicate the pocket into which the document is to be sorted.

The Reader Sorter Adapter~1 8 is controlled by logic signals ADPPLS+OO, ADPENB-00, ADPCD1~3+00, and LADAS1-1 0, which are applied to control logic 44 from MDC 6. Output signals PCDEC 1, 3, 5 and 6 initiate the required cycles of loading, clearing, writing and incrementing as shown in the timing diagram of Figure 4.

Character code signals RSDAT 1-7+00 and translation table quadrant signals XLTOD 1-3+00 are applied to the address selection terminals of a character decode lookup Table 40. Output signals DATDC0~7+00 are coded to indicate the type of character received by RSA1 8; that is, if it is a numeric, an alphabetic, a control, or a formatting character.

Signals UP 1 RO4 and UP 1 ROS are generated by MDC 6 and applied to the select terminals of MUX 42 to transfer the selected signals to MDC 6. Signals ATEST2+00 and ATEST2~00, applied to RCVR/MPX 32, are generated by control logic 44 to select either the load operation of the translate operation.

The load operation is initiated by MDC 6 sending hexadecimal 05 over signal lines ALUOT1~ 7+00 with control signals ADPENB-00 and LODAS1-1 0 at logical zero to control logic 44. The two control signals are combined with signals ALUOT1~6+00 to form an enable signal for a storage device (not shown) which thereupon stores the signal ALUOT7+00 and produces the signal ATEST2+00. Since signal ALUOT7+00 is at logical ONE, output signal ATEST2+00 is at logical ONE.

This selects the load signals LDDAT1~7+00, through receiver/multiplexers 32, as output signals RSDAT1~7+00. This is shown in clock cycle A of the timing chart of Figure 4. On the next clock cycle (cycle B, Figure 4), hexadecimal 00 is sent over signal lines ALUOT0~7+00 along with control signals ADPENB-00 and ADPPLS+00 at logical ZERO. This combination of signals is decoded to produce an output signal PCDEC6~01 (PCDEC6 in Figure 2) at logical ZERO, which is applied to the LOAD terminals of load data register 30. Signal ADPCD1 +00 is at logical ZERO and signals ADPCD2+00 and ADPCD3+00 are at logical ONE. Hexidecimal 00 is set into register 30 since signals ALUOT0~7+00 are at logical ZERO.

Signals ALUOT1 7+00 are at logical ZERO during clock cycle C, Figure 4, and MDC6 sends control signals which are decoded to produce PCDEC1~01 output signal (PCDEC1 in Figure 2) at logical ZERO. This forces counter 34 to hexadecimal ZERO for decoding the address locations of RAM 38 with translated character codes read by head 1 of Reader Sorter 10.

During cycle D, Figure 4, control signals from the MDC6 are decoded to produce an output signal PCDEC5~01 1 (PCDEC5 in Figure 2) at logical ZERO, enabling counter 36 to store the first translated character code received over signal bus ALUOT0-7+00 from MDC 6.

The translation and queue marker table 38 includes a flip-flop (not shown) which controls whether a read or a write operation is performed. On the next clock cycle (cycle E, Figure 4), this flip flop is set on the rise of the CLOCK signal when an output signal PCDEC3~01 1 (decoded from control signals from MDC6) is at logical ZERO, thereby forcing the write pulse signal WRTXLT-00 to logical ZERO.

On the next clock cycle (cycle F, Figure 4), the data stored in the status select register 36 is written into address location 000 of RAM table 38 via signal lines RSSEL0-7+00.

On the next cycle (cycle G, Figure 4), control signal ADPPLS+00 is at logical ONE, thereby enabling a decoder 50, and signal OCDEC6-02 is forced to logical ZERO, thereby incrementing load data register 30 to 001; and, on the next cycle (cycle H, Figure 4), the next data character is loaded into register 36, and cycles D, E, F and G are repeated until the register 30 stores hexadecimal 7F. That is, signals LDDAT1~7+00 are at logical ONE, indicating address location 127iso. On the next increment load data register clock cycle (cycle G, Figure 4), the contents of the load data register 30 cycles to ZERO, setting signals LDDAT1~7+00 to logical ZERO.

Also, the carry signal generated during this cycling back to ZERO of counter 36 is applied to the counter 34 to increment this counter. This enables the selection of address locations 128,0 to 255to of RAM 38. This is shown in cycle I, Figure 4.

Signals LDDAT0+00 at logical ONE and LDDAT1 +00 at logical ZERO indicate to MDC 6 that the head 1 character sequence is completed and register 30 stores address location 000. When the head 2 character sequence is completed, counter 34 is incremented as just described, forcing signal XLTQD2+00 to logical ONE and XLTQD3+00 to logical ZERO. On the next clock cycle, signals LDDAT0+00 and LDDAT1 +00 are at logical ZERO, indicating to the MDC 6 that the head 2 character sequence is completed.

Signal XLTQD2+00 at logical ONE selects the third and fourth quadrants in RAM 38, and the above sequence is repeated for the heads 3 and 4 character sequences. This time, when counter 34 is incremented, signal XLTQD1 +00 is forced to logical ONE. This indicates to MDC 6 that the load operation is completed and, as shown in cycle J. Figure 4, signal ATEST2+00 is forced to logical ZERO in control logic 44. If signal XLTQD1+00 is at logical ZERO, then in cycle j, Figure 4, signal PCDEC3~ 01 is forced to logical ZERO by MDC 6 and the memory write flop is set and cycle K is a write data cycle as in cycle E.

Character decode lookup table 40, which is formed by a pair of PROMs, receives character code signal RSDAT1~7+00 and translation table quadrant signals XLTQD1-3+00, and provides output signals DATDC0-7+00, as described supra.

Figure 6 is a block diagram of the microprogrammed device controller 6.

Character signals ADPDSO--7 +02 are received from the RSA1 8 through an arithmetic logic unit (ALU) operand multiplexer (MUX) 302 and stored in a scratch pad memory 300. Information from scratch pad memory 300 is transferred to a register 306 via MUX 302 and an ALU 304. The information stored in register 306 is transferred out on system bus 16 via MUX 302 and a bus interface register (BIR) 308.

Signals ALUOTO-7+00 are sent to the RSA1 8 from the system bus 1 6 via BIR 308, MUX 302 and ALU 304.

The control signals ADPPLS, ADPPENB, ADPCD1~3, LODAS1, UP1 R04 and UP1 ROS are generated from microwords read from a microprogram control store 310, stored via register 312 and decoded by an opcode decoder 314. A clock generator 316 develops the CLOCK and CLKSTB signals which are applied to RSA1 8.

Figure 3 shows a typical stream of characters from a document having an MICR field, an OMR field, an OCR1 field and an OCR2 field. The start of document (SOD), start of head (SOH), read area 2 (RA2), and end of document (EOD) characters are the pseudo queue field characters. Queue symbol (QS) characters are translated to queue field identifier (OFT) characters in the translation and queue marker table 38, Figure 2.

The notation SOH-QS indicates that the start of head is stored in address location FOQ and the queue symbol is stored in address location FCQ of scratch pad memory 300.

A. SOH-QS indicates the start of the first read area of a head.

B. QS-SOH indicates the end of a read area of a head.

C. QS-RA2 indicates the end of the first read area of a head.

D. RA2-QS indicates the start of read area 2.

E. QS-EOD indicates the last read area of the document.

F. SOH-SOH indicates that no QS characters and data were detected for a head.

G. SOH-RA2 indicates that no data and no OS characters were detected in the first read area of a head.

H. RA2-SOH indicates that no data and no QS characters were detected in the second read area of a head.

I. RA2-EOD indicates that no data and no QS characters were detected in the last read area of the document.

J. SOH--EOD indicates that no QS characters were detected in either the document or the last read head or read heads.

Figure 5 is a flow chart of the firmware routines in the MDC 6 that process character codes received from the RSA1 8. A firmware routine RSA1-QF1 200 analyzes the character code for a control character, a queue field identifier character or a data character. Firmware routine 200 identifies the start of document and the end of document characters as well as the queue symbols, thereby defining the data field. The start and end of field characters may be control characters or queue symbols. Queue symbols are translated into queue field identifier characters as the output of RAM 38.

The firmware initially selects the output of PROM table 40, signals DATDCO#7+00, which are applied to MUX 42. The output of MUX 42, signals ADPDS0-7+02, are applied to MDC 6. Decision block 202 examines signal ADPDS0+02 which, if at logical ONE, indicates a control character. The firmware then tests signals ADPDS 1-7+02 in decision block 214 for the end of document character (EOD). If the control character is an EOD character, then in block 216, a hexadecimal 84 is stored in the field closing queue (FCQ) character address location in scratch pad memory 300, Figure 6.

Decision block 218 tests signals ADPDS 1-7+02 for a read area 2 (RA2) control character. If the RA2 control character is sensed, then in block 220 a hexadecimal 82 is stored in the FCQ address location. RA2 is called a pseudo queue field identifier which indicates that an area in the document was purposely skipped and the read head reactivated.

Decision block 244 tests signals ADPDS 1-7+02 for the start of document (SOD) control character. If this control character is not an SOD character then it is a read head identification (HID) character and in block 222, a hexadecimal 81 is stored in the FCQ address location. If decision block 244 sense the SOD character, then firmware routine SIDQFIEXIT 206 is called.

If decision block 202 indicates that the character received is not a control character, that is, signal ADPDS0+02 is at logical ZERO, then the firmware selects the outputs of RAM table 38 which are applied to input terminal 1 of MUX 42 as signals XLTDT0-7+00.

Decision block 204 test signal ADPDS0+02, but this time the signal at logical ONE indicates a queue symbol, and at logical ZERO, indicates that an information character was read. If an information character was read, then firmware routine SIDQFIEXIT 206 is called. The field data and position (FDEP) count stored in scratch pad memory 300, Figure 6, is incremented in block 208. The FDEP stores a count of the number of character positions-the last character in the field is from the head character.

Decision block 210 checks if the character received is an illegal character. If it is not an illegal character, then the firmware subroutine SIDQFIEND 212 starts a sequence which results in the character being loaded into main memory 4 and RSA1 8 is ready to send the next character to MDC 6.

After a control character is identified and the appropriate code written in the FCQ address location, a firmware routine, SIDQF1200 224, is called which, in decision block 226, tests if a control character or a queue field identified character was received previously during the reading of the document. If not, then firmware routine SRSA1-QFlB 230 is called to initialize the basic fields.

Block 232 initializes a number of address locations in scratch pad memory. The FDEP address location is initialized to hexadecimal FF and the field data start position (FDSP) address location is initialized to hexadecimal 01. Also the read head that is operative is identified in the number of error characters in field (NECF) address location.

Firmware subroutine SRSAl-QFIA 234 in block 236 stores the contents of the FCQ address location hexadecimal 81, if the first character is the HID character, into the field opening queue (FOQ) address location and clears the FCQ address location to hexadecimal 00. Also cleared are the first, second and third error character positions (ECPs) address locations and the lower bit positions of the NECF address locations.

Block 238 sets an indication that the first control character of the document was received and the queue field is open.

Routine SIDQFIEXIT 206 now increments the FDEP address location to hexadecimal 00 in block 208.

Decision block 204 recognizes that a queue field identifier code from RAM table 38 was received, and in block 240 the character code is stored in the FCQ address location with the bit position 0 set at binary ZERO. Decision block 242 tests the queue field and if it is open, calls for routine SQFI-WRT 244. SQFl-WRT 244 is the subroutine which stores a completely assembled queue field identifier block of address locations FOQ, FCQ, FDSP and FDEP of scratch pad memory 300 into memory 4.

Decision block 252 tests if eight characters are stored in the above address locations. If there are 8 characters stored, then in block 254 the 8 characters are transferred to memory 4, and in block 258 the firmware returns to block 246.

If the result of decision block 252 test negative, then in block 256 a data truncated flag is set to indicate that a QFI field was not forwarded to main memory 4. In block 258, the firmware returns to block 246. Here, the contents of FDEP has hexadecimal 2 added to it and the result is stored in the field data start position (FDSP) address location of scratch pad memory 300. This defines the position of the first data character in the next OFI field of the document.

Firmware routine SRA1-QFlA 234 is called, and in block 236 the contents of address location FCQ is stored in address location FSQ and in block 208 the contents of address location FDEP is incremented. Decision block 210 again checks for an illegal character. The legal queue field identifier character is stored in main memory 4 in the firmware sequence started by routine SIDQFIEND 212.

Subsequent data characters are read, incrementing address location FDEP in block 208 as described supra so that address location FDEP stores a count of the position-the current character in the data field is from the head identifier character.

If decision block 202 senses a control character such as an end of document (EOD) character code, hexadecimal 84 is loaded into address location FCQ in block 216, and firmware routine SIDQF1200 244 is called. Decision block 226 calls firmware routine SQFl-WRT 244.

Previously, decision block 242 called firmware routine SOFl-WRT 244 which transferred the contents of address locations FCQ, FSO, FDEP, FDSP and the error count and error character positions to main memory 4, and returned to block 246. Here the EOD character initiates the calling of firmware routine SQF--WRTT 244 which transfers the contents of the above address locations FCQ, FSQ, FDEP, FDSP and the error count and error character positions to main memory 4. The routine 244 returns to call firmware routine SRSAl-QFlB 230.

Detection of EOD from the device indicates no further data character from the document is to be transferred, thus implying no further building of Efts.

If decision block 210 indicates an illegal charactsr, thsn firmware subroutine SIDQFI510 264 is called. In block 266 the number of error characters in field (NECF) is incremented. In decision block 268 the NECF is tested for greater than 8 errors. If there are more than 8 errors in the field, the routine is terminated and firmware routine SIDQFIEND 212 is called. If decision block 268 shows less than 8 errors, then decision block 270 tests for less than 4 errors. If NECF indicates less than 4 errors, then decision block 274 tests for 1 or 3 errors, and decision block 276 tests for 1 error.Block 278 stores an indication of the first error character position (FOP), block 280 stores an indication of the second error character position and block 282 stores an indication of the third error character position, and the end firmware routine SIDQFIEND 212 is called.

The contents of address locations FOQ and FCQ, when examined by the CPU 2, will indicate the status of the reading of the document by reader sorter 10.

The contents of the character decode lookup table 40 are shown in the following table, in hexadecimal form, and appear on the 8 signal lines DATDC0-7+00. The address locations are also shown in hexadecimal form. Signals XLTQD1-3+00 and RSDAT1~7, applied to the address input, select the address location. The 9th and 1 ooth bits indicate the operative read head and are the signals XLTDQ1 +00 and XLTDQ2+00.

Head 3 (OCR 3) SOH 102 82 Dash 120 10 Symbol 124-12F 20 Numeric 130-139 04 Symbol 1 3C-1 3E 20 Can't Read 13F 40 Alphabetic 141-15A 02 Symbol 156--15F 20 MICR Head 160 AO RA2 (MICR) 162 EO OMR Head 168 90 OCR 3 Head 170 88 RA2 (OCR 3) 172 C8 OCR 4 Head 178 84 RA2 (OCR 4) 17A C4 Field Format Error 1 7C 01 EOD 17F 81 Unused Location 00 Head 4 (OCR 4) SOH 102 182 Dash 120 1 AO Symbol 124--l2F 1 A4-1 AF Numeric 130--139 1 1B0-1B9 Symbol 13C-13E 1BC-1BE Can't Read 13F 1 BF Alphabetic 141-15A 1C1--1DA Symbol 156-15F 1 DC-1 DF MICR Head 160 1 EO RA2 (MICR) 162 1 E2 OMR Head 168 1E8 OCR 3 Head 170 1 FO RA2 (OCR 3) 172 1F2 OCR 4 Head 178 1F8 RA2 (OCR 4) 17A 1 FA Field Format Error 1 7C 1 FC EOD 17F 1 FF Unused Location 00 The following chart shows the interpretation of the bits of the contents of selected address locations:: Signal Weight Bit=O Bit= I MSB DATDCO+OO 8 0 1 DATDC1 +00 4 Can't Read Read Area 2 DATDC2+00 2 Symbol Head lID (MlCR) DATDC3+00 1 Dash or Space Head 21D (OMR) DATDC4+00 8 Transit Symbol Head 31D (OCR1) DATDC5+00 4 Numeric Head 41D (OCR2) DADTC6+00 2 Alpha SOD LSB DATDC7+00 1 Field Format Error EOD As an example, the contents of address location hexadecimal 1 7a is hexadecimal C4.

Hexadecimal 17A, expressed as a binary number, is 0001 01111010. The 1 itch and 12th bit positions contain binary 00 and are ignored. The 10th and 9th bit positions contain binary 01 respectively indicating that the character was read by read head 3. Hexadecimal C4 expressed as a binary number, binary 1100 0100, indicates a read area 2 character associated with head 4. This is an indication to the MDC 6 that head 3 has completed the reading of the OCR1 field, and the document will pass to the read head 4 read station for reading the OCR2 field.

Claims (10)

Claims

1. A document processing system comprising: a reader sorter device which reads a document and generates a sequence of character signals comprising information characters read from the documents and control characters generated by the reader sorter device; an adapter coupled to the reader sorter device and responsive to the character signal sequence to generate translated character signals identifying queue field identifier characters among the information characters and to generate character identifier signals identifying the control characters as pseudo queue field identifier characters; and a controller coupled to the adapter responsive to the translated character signals identifying queue field identifier characters and to the character identifier signals identifying pseudo queue field identifier characters to designate the boundaries of a field, for transfer to a main memory, and further responsive to the translated character signals to generate a start position character count and an end position character count in the queue field for transfer to the main memory.

2. The document processing system of Claim 1 , wherein the adapter comprises: a random access memory responsive to the character signals from the reader sorter device to select the translated character signals; a read only memory responsive to the character signals to select the character identifier signals; and a multiplexer responsive to the controller to select either the translated character signals or the character identifier signals for transfer to the controller.

3. The document processing system of Claim 2, wherein the controller comprises: control means coupled to the adapter to control the multiplexer; arithmetic logic unit means responsive to a translated character signal to generate a queue field identifier character, and to a character identification signal to generate a pseudo queue field identifier character; and a scratch pad memory, coupled to the arithmetic logic unit means, to store first signals representative of queue field identifier characters in a first address location representative of a field opening queue character, and in a second address location representative of a field closing character and to store second signals representative of pseudo queue field identifier characters in the first and second address locations.

4. The document processing system of Claim 3, wherein the arithmetic logic unit means is responsive to a succession of translated character signals to generate signals representative of the start position character count when the first of a succession of translated character signals is received, and to count the succession of translated character signals to generate signals representative of the end position character count.

5. The document processing system of Claim 4, wherein the scratch pad memory means further stores the start position count signals in a third address location, and the end position count signals in a fourth address location.

6. The document processing system of Claim 5, wherein the arithmetic logic means includes means for checking the translated character signals and the character identifier signals for generating signals indicative of the number of illegal characters in the field, said checking means generating signals indicative of whether the number of illegal characters is less than a predetermined value.

7. The document processing system of Claim 6, wherein the checking means further generates signals indicative of the character positions of the illegal characters in the field.

8. The document processing system of Claim 7, wherein the scratch pad memory further stores the signals indicative of the character position of illegal characters.

9. The document processing system of Claim 8, wherein the scratch pad memory means stores character position signals indicative of the character position of at least the first illegal character in the field.

10. The document processing system of Claim 9, wherein the arithmetic logic unit means is responsive to translated character signals and/or the character identifier signals representative of the queue field identifier character to transfer the controls of the scratch pad memory to the main memory for processing by a central processor unit.

1 1. A document processing system substantially as herein described and illustrated.