CA1155228A - Queue symbol field recovery flags for defining boundaries of one or more fields of a document read by a reader sorter - Google Patents

Abstract

Abstract of the Invention A Reader Sorter may have an MICR (Magnetic Link Character Recognition) read head, an OMR (Optical Mark Recognition) read head, and two OCR (Optical Character Recognition read heads or a combination thereof.
A Reader Sorter Adapter receives characters read by the Reader Sorter.
The characters include data and formatting symbol characters read from a document and control characters generated by the Reader Sorter. Certain characters may be identified as queue field identifiers (QFI) by the user via software. These are usually the formatting characters. The control characters are identified as pseudo queue field identifiers (PQFI). QFI and PQFI characters are received by a Multiple Device Controller and allow the firmware to identify the length of the data fields, the head from which the characters were received, and any special conditions associated with reading of a data field.

Description

~S~8 BACKGROUND OF T~E INVENTION
Field of Use This invention relates generally to the reading of documents by a reader sorker, for selecting a pocket into which the document is sorted; and more specifically, to the defining of OCR (Optical Character Recognition), MICR (Magnetic Ink Character Recognition~ and O~R (Optical Mark ~ecognition) data fields within the document.
Description of the Prior Art A reader sorter has a number of heads for reading fields of informakion on documents, such as checks having MICR and OCR fields. The information is read by the reader sorter, processed by the controller, and trans-ferred to a central processor unit which, under software control, selects a pocket for sorting the document. The information on the document is organized in fields. A
fleld may include a control character followed by a group of data characters, followed by another control character.
The prior art systems such as the Honeywell H200 Data Processing System having a reader sorter on a subsystem transmit all of the characters read from the document through a controller to a central processor unit. Time consuming software routines examined all of the characte~s received from~the reader sorter, differentiating control characters ~rom data characters and defining the fields.

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Objects of the Invention Accordingly, it is a primary object of the invention to provide a docu-ment sorting system with improved performance.
It is another object of the invention to provide a document sorting sys-tem with improved apparatus for defining the fields read ~rom the document by the reader sorter~
It is still another object of the invention to provide a document sort-ing system ~ith. improved apparatus for translating the queue sym~ols to the queue field identifier characters.
It is yet another ohject of the invention to provide a document sorting syætem with improved apparatus for identi~ying queue symbols and pseudo queue field identifieræ for defining fields- read from the documen-t.
Brief Summar~ of the Invention In accordance ~ith the present invention, there is provided a document procesæing syætem compriæ~ing: a reader sorter device for reading a document se-quentially and generating character signals indicative o~ a character read from said document~ ~nd a control c'haracter generated by said reader sorter device; an adapter coupled to s:aid reader s:orter device and responsive to sa:Ld charac~.er sig-nals for generating translated character signals, identi:fying sa:Lcl c'haracter as a 20, queue ~ield identifier t,haracter; said adapter being Eurther responsive to æaid character slgnals or generating character ldentlfier slgnals identi~ying said control character as a pseudo queue field identifier character; a controller coupled to sa-id adapter ~or recei,ving said translated character signals representa- .
ti,ve of said queue ~ield identifieY character and said character identifier sig-nals, representative of said pseudo queue field identifier character, for designa-ting the boundari~es oE a ~ield? for trans~er to a main memor~; and, said control-ler ~urther receiving said trans-lated character signals for generating a start position character count and an end position character co~mt in said fi,eld for trans.fer to said main memory~

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3RIEF DESC~IPTION OF ~HE DRAWINGS

The nov~l features which are characteristic of the invention are ~et ~orth with par~icularity in the ap-pended claim~. The inven~ion itself, however, both a~
5 ts organization and operation, may best be under~tood by reference to ~he following de~cription in conjunc-tion with the drawings in.which:
Figure 1 is an overall block diagr~m of the sy~t~m.
Figure 2 i8 a block diagram of the reader aorter adapter.
Figure 3 i5 a detailed logic diagram of the reader sorter adaPter.
Figur~ 4 is a timing diagram showing load data operation .
Figure 5 is a flow diagr~m of the firmware sPquen-ces in the microprogrammed device controller which identifies the fields.
Figure 6 is a block diagram of the microprogrammed device controller.
Figure 7 3hows the character se~uence received by the reader 90rt~r adap~er.
Figure 8 shows the contents of the programm~bl~
read only memory.

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SUMMARY OF THE INVENTION

~,~. A document processing syst2m includes a central proce~sor unit (CPU), a snain m~ry and a mi~oprograIrr~
device controller (MDC), all coupled in c~unon to a 5 system bu~. A reader sortex is coupled ~o a reader sorter adapter ~RSA) which, in ~urn, i~ coupled to he MDC .
Character codes are generated in the reader sor-ter and transerred to the RSA. The character codes 10 include informakion read from the document as well as indicating the active read head and the position of the document relative to the read head. Included are start o~ document, end of doc~ment, read area 2 (RA2) character codes as well as character codes identifying 15 the active head reading the document.
The character codes read from the documen~ are data characters and special symbol characters, and are translated in the RSA to conorm to the code~ used in ~he CPU.
The in~onmation on the document i~ organ~zed in fields. Certain character codes read rom the docu~.e, :
are translat2d in ~he RSA a~ queue ~ield ide~tifier (QFIl charaatcrs. The character aodes read from the '.
document are also txanslated into character identif ier codes which indicate typically, an alphabetic charac-ter, a numeric character, a dash or space, or a special symbol. The charac~er codes generated by the reader sorter are also translated in~o certain charac~er iden-~ifier codes designating pseudo queue field iden~ifier (PQFI) characters.
The QFI characters and PQFI charac~ers identify the boundaries of the field.
The MDC includes a control stor2 for storing firm ~Jare routines; an arithmetic logic uni~ (ALU) receiving

3~ the translated character codes and the character iden-, .
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2~1 3 L., , tifier codes for selecting the QFI characterc from thetran~lated character code~ and the PQFI characters from the character identiier codes, and a scratch pad memory for storing in address locations, the QFI or S PQFI c:haracter codes starti~g and closing ~he f ields .
Xn addition, the controller, undex finmware con-~rol, generata~ a count of the number of po i~ions the character recelved, following the QFI or PQFI starting character, i8 from the PQFI character identifying the 10 active head~
The Gontroll~r al~o ~enerate~ a count of the number of positions the character received, immedia~e-ly preceding the QFI or PQFI closing character, is from th~ PQFI charac~er identifying ~he active head.
lS These c9un~s are stored in address locations in scra~ch pad memory.
In addition, the controller checks all tran~lated charact~r codes and charactex identifier codes for illegal chaxactar codes and ~tore~, in addre~ loca-kions in ~cratch~ pad memoxy, a count of khe numbex oillegal character3 in the ~i~ld with the location in the ~iald of the illegal character8.

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Fi~ure 1 shows the Docume~t Processin~ System, which includes a central processor unit (CPU) 2, a main memory 4, a plurality o~ peripheral controllexs 12, and a plurality of microprogrammed device co~trol-lers (MD~) 6, all coupled in common ~o a syskem bu~ 16.
Coupled to the MDC 6 may b~ a Reader Sorter Adapter 1 (RSAl) 8 or a Reader Sorter Adapter 2 tRSA2) 18. A Reader Sorter Device-l (RSD-l) 10 r which may b~
a Honeywell Model DHU9840 device, is coupled to the RSAl 8; and, ~ Roaaer Sort~r Device-2 (RSD-2~ 20, which may be a Honeywell Model 234-0 or a 236, i~
coupled ~o ~he RSA2 18.
~he ~DC 6 is disclosed iA U. S. Patent 4,003,033 ~5 entitled, "~rchitec~ure for a Microprogrammed ~evice ControllerU ~ t~~hi~-r~renee-~-i*eoff~ e~ o The Document Proces~ing System reads documents in the Read~r Sorter Device-1 10 ~equentially from up to four read h~ad~. ~ firsk read head reads MICR (Magna~
tic Ink Charac~er Recognition) charac~er~, a second read h~a~ r0~d~ OMR words ~Optical Mark Recognik~on~
and a ~hlrd and ~ourth read heads read OCR (Optlcal Character Recogn~tion) characters. The infonmation Lrom the document is read through the ~SAl 8 and MDC 6 onto th~ sy~tem bus 16 to main memory 4, and is pro csssed by the CPU 2. Selected characters may be stoxed in main memory 4 for further processing.
The CPU 2 processes the information under program 30 c:ontrol and sends re~urn signals via the sys~em bus 16, tlle MDC 6, and the RSAl 8 to the. Reader Sorter Devic -1 101 there~y indicating the pocke~ nto which the docu-~nen~ is sorted.
The ~C 6 is a microprogrammed peripheral control-35 ler which performs general purpose con~rol functions . . . ~ . . .
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such as executing sy~tem bus sequenceQ, providing com-mand storage, tra~sferring and editing data~ and e~tab-lishing the general flow of command execution.
The RSAl 8 contains all the u~ique hardware nece~-sary to dialogue with the Reader Sorter Device-l 10.
This em~odiment describes the relationship between the MDC 6 and ~he RSAl 8. It i9 understoQd that RSA2 18 and Reader 5Orter Device-2 20 operat~ wi~h ~he MDC 6 in a qimilar manner aq RSAl 8.
Refer~ing to Figure 2, the RSAl 8 include~ a Translation and QuPue Marker Table Random Access Memory ~RAMj 38 for storing, in 512 addressable location~, chaxact~r code3 which are transferred to a multiplexer 42 as ~ignals XL~DT0-7+00, and, in turn, to the MDC 6 a~ signal~ ADPDS0-7~02.
Document character code ~iqnals are applied to a receiv~r/multiplexer 32 of RS~l 8 as signal~ RSDAT 1-7 (7 bit~), an~ ~re applie~ to the ad~ress select termin-al~ of RAM 38 to select the address locations ~koring the equivalent char~cter code for tran~er to MDC 6. A
cod~ identifying the particular head reading the docu-ment is stored in a Translation Table Quadrant Registe~
Counter 34. Signals X~TQD 2,3~00, applied to the addre~s select term~nal~ of R~M 3~, select the 128 addres~ loca-tionq in R~M 38 ~torin~ corre~pondin~ charackers assoc.ia-ted with a particular head.

Head Character XLTQD
Nl~ber Field 2 3 2 OMR ~ 0 1

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The RAM 38 is loaded initially with character codes that will be u~ed by the CPU 2~ These character code6 include fo~mat characters, font select characters and data characters, and may be ASCII, EBC~IC, binary

5 coded decimal, or ~ny other appropriate code as required ~,.
for the current sorting application.
A Load Data Register/Counter 30 applies output signal~ ~DDA~0-7-00 to receiver multipl~x~r 32. The Counter 30 is initially set to hexidecimal ZERO and incremented ~hrough 128 addre~s locations under firm-war~ control. Similarly, Counter 34 is reset to binary ZERO and incremented once every 128 character transfers for writing the 512 character codes into RAM 38.
The aharacter code is applied to a Statu~ Select Register Counter 36 from the MDC 6 via signals A~UOT
0-7+00 and applied to RAM 38 as signals RSSEL0-7+00.
RAM 38, therefore, is loaded initially with the character code~ required by the ~PU 2. -During the reading o~ the document, the characters are translated into the required code by RAM 38. Sig-nals LDDAT 0-7~00 are applied to the Reade~ So~ter lG
and indicate khe pocket in~o which ~he document i~ to be sorted.
The Reader Sorter Adapter-l 8 is controlled by logic signals ~DPPLS+00, ADPENB-00, ADPCD1~3~00, and LODASl-10, which are applied to control logic 44 from ~DC 6. Output signals PCDEC 1,3,5 and 6 initiate the required cycle3 of loadinq, clearing, writing and in-crementing as shown in the timinq diagram of ~igure 4.
Character code signals RSDAT 1-7+00 and transla-tion table quadrant signals XLTQD 1-3+00 are applied to the address sPlection terminals of a character decode lookup Table 40. Output signals DATDC0-7~00 are .
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~55i2~8 coded ~o indicate ~h~ type of charactex received by RSAl 8; that is r if it is a ~umeric, an alphabetic, a control, or a formatting character.
Signals UPlR04 and UPlR05 are generated by MDC 6 and applied to the selec~ terminals of MUX 42 to tra~-;~ f~r the ~elec~ed MUX 42 output~ signals to MDC 6. Sig-nals ATEST2~00 and ATEST2-00, aPPlied to RCVR~MPX 32~ are generated by control logi :: 44 to select either the load operation or the transla~e o~eration.
Referring to Figure 3, the ~ranslation and Queue Marke~ Table, RPM 38 includes random acoess memories RAM 106, 108, 110 and 112, which are 2101A memory cir-cuits described in the In~el Data Cataloq 1978, pages 3-26. The catalog is published by Intel Coxporation, 3015 Bower3 ~venue, San~a Clara, ~alifornia 95051.
During the document reading operation, character cbde signals are received from Reader Sorter 10 o~er signal lineq RSDATl-7~0R, and are applied ~o rec2iver/
multiple~er 32, which include~ receiver/multiplexer~
64, 68, 72, 78, 82, 86 and 90. Control signal A~ES~
2-00 is at logi~sl O~E for the document readlng ope:-akion. Ou~.put signal~ RSDATl-7~00 are applied to thP
address s~lect inputs of RAM~ 106, 108, 110 and 112.
Counter 102 o~ Translation Table Quadrant Register/
Coun~er 34 provldes 3ignal XLTQD2+00, which enables RAMs l.06 and 108 or RAMs 110 or 112. Siq~al XLTQD3+00 i5 appli~d to the addre~s seleck ~erminal 128. Address locations 000 through 1271~ of R~M8 106 and 108 store characters decoding the characters on th~ document r~ad by head l. Addres~ locations 128~o through 2551o of RA~ 106 and 108 store characters decoding the .

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character3 on ~he documen~ read by head 2. Similarly, . aâdre~s loca~ions 000 through 1271o of RAM~ 110 and 112 are associated wlth head 3, and addr¢ss locations 12~1o thrcugh 2551o with head 4.
The output of RAMs 106 and 108, signals XL~DT
0-7+0A, and RAMs 110 arld 112, signals XLTDT0-7~0B, are applied ~o wired O~ circuits 118 through 132. The out-put signal~ XLDT0-7~00 are applied to inpu~ ~erminal 1 of MUX 42.
Initially the ~AMs 106, 108, llO and 112 are load-ed with character codes c~mpatible with the data proc:ess-ing system of the Document Pxocessing System, namely, the CPU 2, main memory 4, an~ MDC 6. The character codes include data characters as well as control charac-ters.
The load operation is inLtiated by MDC 6 sending hexadecimal 05 o~er signal lines ~LUOTl-7+00 with con-trol signal~ ADPENB-00 and LODASl-10 at logical ZERO to Control Logic 44. This enable~ a decoder 54 and output signal ASIDC0-04, forced to logical ZE~0 a~ ~he rise of clock stobe ~ignal CLKSTB, enables the loadln~ o:E a re-gis~er S6. Since ~ignals ALUO~5~00 and A~UOT7+00 ar~ ~t logical ONE, output signal AT:E5ST2~00 is at logical 02~
Si~nal ATEST2-00, the output o~ an inverter 92, is at logical ZER0. This sel2cts the load ~ignals LDDATl-7-00, the output of inver~ers 62, 66, 70, 76, 80, 84 and 8B, through receiver/multiplexers 64, 68, 7~, 78, 82 t û6 and 90, a~ output signals RSDATl-7+00.: This is shown in clock cycl8 A of ~he timing chart of Fi~ure 4. On the next clo~k cycle ~cycle B , Figure 4), hexadecimal 00 is sent over signal lines AIluor~7+ûo along with signals ~PENB-00 a~d ADPPLS+00 at logical ZER0, thereby enabling a decoder 520 Signal ADPPhS-OO is at logical ONE as the outpu~ of an inverter 51. Output signal PCDEC6-01 at logical ZERO i~ applied ~o the LOAD terminals of ~ oad 35 data registers 58 and 60. Signal ADPCDl~00 i~; at logi-~, .

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cal ZERO and ~ignals ~DPCD2+û0 and ADPCD3~00 are at logical ONE. Hexadecimal 00 is set into registers 58 and 60 since s~gnals ALU0q~0-7+00 are at logical ZERO.
-` Signal~ UOT4-7~00 are at logical ZERO during 5 clock cycl~ C , Figure 4, and signal~ rom MDC 6 force the PCDECl-01 outpu~ signal of decoder 52 to loyical ZERO. This forces counter 1û2 ~o hexadecimal ZERO for decoding the address location~ of RAMs 106 and 108 with translated character codes read by head 1 of Reader Sorter 10.
During oycle D, Figure 4l control signal PCDEC5-01, the output of decoder 52 is forced to logical ZERO en-abling counters 94 and 96 to ~ore ~he first ~ranslated character code recaived over signal bus AhUOT0-7~00 from MDC 6.
On the next clock cycle (cycle El Figure 4~/ a D
~lop 104 is set on the ri52 of the CLOCK signal when signal PCDEC3-01 is at logical Z~ROI thereby ~orci~g the wxite pul~e ~ig~al WRTXL~-00 to logical ZE~O.
On the next clock cycle (cycle Fl Figure 4), the data stored in the status selec~ register~ 94 and 96 are wrltten into addre~s location Q00 o~ RAMs 106 ar~e 108 ~ia ~ignal lines RSSE~0-7+00.
On ~he ne~t cycle (cycle Gl Figure ~)l control 2~ signal ADPPhS~00 is at logical ONE I the~eby enabling a decoder 50l and signal PCDEC6-02 is forced ~o logi~al ZE~OI th~r~by incremen~ing load data register 60 to 001;
and, o~ ~he next cycle (cycle ~I Figure 4), the next data charact~r ic loaded into registe~s 94 and g6, and cycle~ D, E, F ana G are repeated untll ~he regi~ters 5 8 and 60 tore hexadecimal 7F, That i5, l3ignals 1,DDATl-7-00 are at logical ONE, indicating address location 1271o. on ~he next increment load data re-gister clock cycle (cycle G, Figure 4), ~he carry ~ig-nal LDDTCY-01 of register 60 is forced to logical ZERO~
which increment~ load da~a regis~er 58 on the next ri3e of ~he C~OCK signal. Thi~ forces the LDD~T0~00 siqnal l ~s to lo~ical ONE, and ~ignal~ LDDA~1-7+00 to logical ZE~O.
Al30, the carry signal LDDTCY~01, outpuk of an -~ inverter 99, is applied to a NAND gate 98. Since 8i~-nals LDDATl-3+00 are al90 at logical ONE during this cycle, the output signal LDDTCY-03, at logical ZERO is applied to the PT terminals of counter 102. Thi3 in-crements counter 102, and output signal XLT~D3~00 is forced to logical ON~. Thi~ enable~ the sslection o~address locationq .l281o through 2551o of RAMs 106 and 108. Thi~ hown in cycle I, Figure 4.
Signals I,DDAT0+00 at logical O~E and LDDATl+00 at logical ZERO indicate to MDC 6 that the head 1 charac-ter sequence i~ comple~ed and reqisters 58 an~ 60 store addre~s location 000. When the h~ad 2 character ~e-~uence i~ completed, counter 102 i9 incremented a~ de-scribed supra through NAND gate 98 and NOR gate 100, forcin~ signal XLTQD2+00 ~Q logical ONE and XLTQD3~00 to log-ical ZERO. On the next clock cycle, signals LDDAT0~00 And LDDAT11 00 are at loqical ZERO, indicat-ing to ~h~ MDC 6 that ~he head 2 character sequerlce is 20 completed~
Signal XLTQD2~00 at logical ONE ~elect~ RPMs 110 and 112, and the ~hove sequence i9 repeated for ~he heads 3 and 4 character sequence~. This kime, when ~ounter 102 i~ incremented, si~nal XLT(2Dlt 00 i~ forced to logical ONE. This indicates to MDC 6 that the load operation is completed and, as shown in cycle J, Figure 4, s.ignal ATEST2+00 is forced ~o loqical ZE~O in regis- i, t~r 56. Ii~ ~ignal XLT¢~D1~0û is a~ logical ZERO, then in cycle J, Figure 4, signal PCDEC3-01 i~ forced to 30 logical ZERO by MDC 6 and the memory write flop 104 is set and c~cle X is a write ~ata cycle as in cycle E.
PROM~ 114 and 1ï6, of character lecode lookup tabLe 40, receive character code signals RSDA~ 7~0r and translation table q~aadran~ si~nals XLTQD1-3+00, .~ and provide output signals D~TDC0-7~00, a~ described ~, J supra.

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I''' Figure 5 i~ a flow chart of the firmware routine~
`` in ~he MDC 6 tha~ processes character code~ received from the RSAl 8~ A firmware routin~ RSAl-QFl 200 analyzes the character code for a control character, a queue field identifier character or a data character~
Firmware routine 200 iden~ifies the s~art of document and th0 end of document charact~r3 as well as the queue 5ymbol~, thereby defining the data field. The start and end of field characte~q may be control char-10 ac~ers or queue ~ymbols, Queue symbols are tra~slated into queue field identifier characters as the output of ~s 106, 108, 110 and 112 of Figure 3.
The firmware initially selects the output of MUXs 114 and 116, signals DATDC0-7~00, which are applied to input terminal 3 of MUX 42. The output of MUX 42 sig-nals ADpDso-7+o2 are applied to MDC 6. Decision block 202 examines ~ignal ADPDS0~02 which, if at logical ONE, indicates a control character. ~he firmware then te~ts signal~ ADPDSl-7+02 in decision block 214 for ~he end of documen~ charac~er (EOD). If the control character is an EOD character, then in block 216, a hexadecimal ~.4 is stored in the iald closing queue ~FCQ) character addres~ loaation in scra~ch pad memory 300, Figurs 6.
Decision block 218 te~ts ~ignals ADPDS1-7 ~02 ~or 25 a xead a~ea 2 (~A2) control charaater. If the R~2 con-trol char~cter is sensed, then in block 220 a hexa-decimal 82 i9 stored in the FCQ addres~ location. RA2 is called a pseudo queue ield identi~ier which indi- 1, cate~ that a~ area in the document was purposely skipped and the read head reactivated.

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Decision block 244 tests signals ADPDSl-7~02 or the start of document ~SOD) control character. If this control character is not an SOD character then it is a read head identification (HID) character and in block 222, a hexadecimal 81 is stored in the FCQ address location.
If decision block 244 senses the SOD character then firmware routine $IDQFIEXIT 206 is called.
If decision block 202 indicates that the character received is not a control character, that is, signal ADPDS0~02 is at logical ZERO, then the firmware selects the outputs of RAMs 106, 108, 110 and 112 which are applied to input terminal 1 of MUX 42 as signals XLTDT0~7+00.
Decision block 204 tests signal ADPDS0+02, but this time the signal at logical ONE indicates a queue symbol, and at logical ZERO, indicates that an information char-acter was read. If an information character was read, then firmware routine $IDQFIEXIT 206 is called. The field data end position (FDEP) count stored in scratch pad memory 300, Figure 6, is incremented in block 208. The FDEP stores a count of the number of character positions - the last character in the fieId is from the head character.
Decision block 210 checks if the character received is an illegal characker. If it is not an illegal characterl then the firmware subroutine $IDQFIEND 212 starts a sequence whiah results in the character being loaded into main memory 4 and RSAl 8 is ready to send the next character to MDC 6.
After the control character is identified and the appropxiate code written in *he FCQ address loca*ion, a firmware routine, $IDQFI200 224, is called which, in decision block 226, tests if a control character or a queue field identifier character was received previously during the reading of the document. If not~ then ~:h ;,. . . .

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~'7 f irmware routine $RSAl-QFIB 230 is called to initial-ize the ba~ic ~ield~:
Block 232 lnitializes a number of address loca-tions in scra~ch pad memory. The FDEP address loca-tion is initialized to hexadecimal FF and the fielddata start position (FDSP) address location is initial-- ized ~o h~xadecimal 01. Also the read h~ad that is operative i8 identified in the number of error charac~
ters in field (NECF1 addres~ location.
Firmware ubroutine $RSAl-QFI~ 234 in block 236 stores the contents of the FCQ addres~ loca~ion hexa-decimal 81, if ~he first charac~er is the HID charac-ter, into ~he field opening queue (FOQ) addre~s loca-tion and clear~ the FCQ addre~ location to hexa-decimal 00. ~l~o claared are the first, second and third error character posi~ions (ECPs) addres~ loca-tions and the lover bit positions of ~he NECF address locatis:~n~ .
~loclc 238 set an indic:ation that the rirst con-trol charactE~r o~ the document was received and the queue f ield is open .
Routine $IDQFIEXIT 20~ now increments the FDEP
a.ddre~5 loaation to hexadeaimal 00 in block 208.
Decision block 20~ recognize9 that a queue field identi~ier code from RAMs 106, 10a, 110 and 112, Flgure 3, was received r and ln blsck 240 the charac~r code i~ tored in the FCQ address location with the bi~
position 0 :set at bi~ary ZERO~ Deci.sion block 242 1, tests ~he queue field and if it i open, calls for routine $~FI-WR~ 2~44. $QFI-WRT 244 is the subroutine which stores a complet~ly as~embled queue ~ield iden-tifier block of address loca~ions FOQ, FCQ, FDSP and FDEP of scratch pad memory 300 into memory 4.
Decision block 252 tes~s if eight characters are stored in ~he above address locations, If there are 8 characters stored, then in block 254 the 8 characters .
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are transfer~d to memory 4, and in block 258 the firmware returns ~o block 246.
I~ the re~ult o decision block 252 ta8t8 nega~ive, 'i~ then in block 256 a datatxuncated :Elaq is set to int1i-s cate that a QFI field was not forwarded to main memory 4 . In block 258, the f irmware return~ to block 246. Her~, the cont~nt~ of ~D13P has hexadecimal 2 add-ed to it and the an~wer stored in th~ f leld data start po~ition ~FDSP) address location of scratch pad memory o 3do. This dQfines the position of the first data char-acte r in the next QFI f ie ld o the doc~nellt .
Fismwa~ routine $RA1 QFIA 23 4 i~ called, and in block 236 the content~ of address lo~ation FCQ i~ stored in addre~ locatio~ FSQ and in block 208 the co~ten~s of 15 addre~s locakion FDEP i incremented. Decision block 210 again che::ks for an illegal character. The legal queue ~leld identifier charactex is sto~ed in main mem-ory 4 in ~he firmware s~quence started by routine $IDQFIEND 212~ Subsequent data characters are read, : 20 incrementing addre~s:location FDEP i~ block 208 a~
de~cribed upra so that address location FDEP s~ore~ a count o~ the po~ition - the current charact~r in the data field i9 ~rom the head idenkifier char~ater.
I~ d~cision block 202 5en9e~ a control character ~uch as an end o~ document (EOD) characker code, hexa-decimal B4 i~ loaded into addres~ location FCQ in block 216, and firmware routine $IDQFI200 244 is called.
Deci~ion bloc~c 226 calls ~ir~ware routine $~FI-WRT 244. 1!
Previou~ly, decision bloclc 24~ called f irmware : 30 routine ~$QFI-WRT 244 which ~rarlsf~rred the coTl~ents of addres~ :locations FCQ, FSQ, FDEP, E'DSP a~d the error count and ~rror character positions to maln memory 4, and returnad to block 246. Here the EOD character initiat~ alling of firmware routine $QFI-WR~ 244 35 which tsan~er~ ~he contents of the abo~e addres~ }oca~
~iorLs FCQ, FSQ, FD~5P, FDSP and the error cour~t and error .. ~ , , , ~.

I '"l ' character posi~iorls to main m~rnory 4. The routine 244 rekurns to call irmware routine $RSAl-QFIB 23 0 .
. Detection of EOD from the device indicates no further data chara::ter from the document is to be trans-5 ferred, thus implying no :Eurther building of ~FIs.
If decision block 210 indicates an illegal charac-ter, thsn ~inmware 3ubroutine $IDQFI510 264 is called.
In block 266 the number of error characters in field (NECF) i~ incremented. In decision block 268 the NECF
is te~ted for gre~ter than 8 errors. If there are more than 8 errors in the ield, the routine is terminated and firmware routine $IDQFIEND 212 is called. If deci-sion block 268 ~hows less than 8 errors, then decision block 270 test~ for less than 4 errors. If NECF indi-cates las~ than 4 errors, then decision block 274 testsor 1 or 3 errors, and decision block 276 tests ~or 1 error. Block 278 tores an indication of the first error character position (FECP), block 280 qtores ~l indication o the second error character po~ition and block 2~ stores an indication of the third error char-acter position, and the end ~irm~1are routine ~IDQFIE..lD
212 i~ called.
Flgu~e 6 i~ a block diagram of ~he mi~roproyramm,~
device controller 6.
Character signals ADPDS0-7~02 are recelved from tha RSAl 8 throuqh an ~rithme~ic lo~ic unit ~ ~TJ~ 04 and mul~lpl~xer (MUX) 302 and stored in a scratch pad memory 300. Inormation rom scratch pad memory 300 is transferxed to a register 306 via MUX 302 and an ~ 30 ALU 304. The informa~.ion stored in register 306 is : transferred out on system bus 16 via MUX 302 and a bus incerfa~e regis~er tBIR) 308.
Signals ALUOT0-7~00 are sent to the RSAl 8 ~rom the syst2m bus 16 via BIR 308, MUX 302 and ALU 304.
The control si~nals ArPPL~, ADPPENB, ADPCDl-3, LODASl, UPlRO4 and UPlRO5 are generated frGm microwords ~' ' . ~ ' . - :
,; '' ~

-read ~rom a microprogram c~ntrol store 310, stored via re~ister 312 and decod~d by an upcode .lec~oder ~14.
Clock generator 316 develops the CLOCK and CLKSTB sig-nals which are applied to RSAl 8.
Figure 7 shows a typical stream of characters from a document having an MICR field, an OMR ~ield, an OCRl f ield and an OCR2 f ield . The start OlC document (SOD), Rtart l~f head ~SOH), reac9 area 2 (P~23, and end of document (EOD) characters are the p~eudo queue field characters. Queue symbol (QS) charactexs are transla-ted to queue field identifier (QFI) characters in the translation and queue marker ~able 38, Figure ~.
The notation SOH QS indicat~s that the start o~
head is ~tored in address location F~Q and the queue symbol is stored in address loca~ion FCQ o~ scratch pad memory 300.
A. SOH-QS indicates the start of the first read area of thiS head.
. QS-SOH indicates the en~ o~ a read area of this ~0 head.
. QS-P~A2 indi~ates the end of the first read area o this head.
D. R~2-Q~ indica~es the s~art of read area 2~
E. Q8-EOD indica~e~ the last read area o the docu-ment.
F. SOH-SOH lndicates that no QS character~ an~ d~ka were detected for this head.
G. SOH-RA2 inflica~es that no da~a and no QS charac- i ters were detected in the first read area of this head.
H. RA2-~OH indicates that no data and no S~S charac-ters were detected in the second read area of thls head.
I. RA2-EOD indicates that no data and no QS charac-ters wera detected in ~he last read area of the . document.

!q J. SOH -EOD indicates tha~ either no QS characte~ s ~.. ~ i , . were detected in the document or in the last read head or read heads.
The contenti of addre~s locations FOQ and FCQ, S when examined ~y the CPU 2, will indicate the status of the reading of the document by reader sorter 10.
Figure 8 ~hows ~he conten~s of PROM8 114 and 116.
The addre~ locations are hown in hexadecimal form.
Signals XhTQDl-3+00 and RSDATl-7, applied to the ad-dxess terminals, select the 10 low order bits of the 12 bit hexad~cimal addre~s location shown in Figure 8.
The 11th and 12th bit position~ are at binary ZE~O.
The 9th and 10~h bit position~ i~dicate the operativ~
re.ad head and are a repre~en~ation of the ~tate of signals X~TQDl+00 and XLTQD2+00.
The con~ents of the ~elected addre~ location appear~ on the 8:signal lines ~ATDC0-7~00, and are shown i~ Fiyure 8 in hexadecimal form.
: The following chart ~hows the interpretation of the bits of the contents of selecked addre 8 locations:

: Si~nal W ~ 3it 0=0 Bit 0=1 MSB DATDco+oo 8 0 1 ~ :
DATDC1~00 4Can't Read Read Area 2 DATDC2+00 2 Synbol Head lID (MICR) ~A~rDC3~00 1 Dash or Spac~ Head 2ID tOMR!
DATDC4+00 8 T~ansit Symbol Head 3ID ~Rl ~ `
D~T~C5~00 4 ` Numeric Head 4ID (OC~2) ~ADTC6+00 2 ~lpha SOD
~SB DATDC7~00 1 Field Format E~ror EOD

Ai~ ~n ~xP~mnl~, th~ ~n~.~n~ ~f ~ r~.~.q 1- sat i.Qn lhexadecimal 17A is hexadecimal C4. Hexadecimal l~A, exp~esse~. as a bin~ry number, is ~001 01}1 1010. The :, ' .

11th and 12th bit positions contain binary 00 and are ignored. The 10th and 9th bit positions ~ontain binary 01 respectively indicatin~ ~hat the character wa~ rea~
by read head 3. Hexadecimal C4 expres~ed as a binary number, binary 1100 0100, in~icates a read area 2 charac~er associated with head 4. Th.is is an indica-~ion to ~he MDC 6 tha~ head 3 has complete~ the read-ing of the OCRl field, and the document will pa~s to the read head 4 read station for readin~ the OCR2 field.

,................................ , ~ .

,r,~ I

.. Following is a tabl0 identiying the lo~lcal elements of this embodiment:

The TTL Data sook for Design Engineer~, Second Edition, ~ublished by Texa Ins~ruments S Decoder~ 50, 52, 54 74L$138 Counter/Register 58, 60, 94 74L.s169 D Flop 104 74LS74 S~gnetics Bipolar & MOS Memory Data ~lanual PROM 114, 116 82S137 Signetic~ Logic - TTL Data Manual coPyright 1978, ~a~e 62 Regi3t~r 56 9334 Having shown and d~scrib2d a prefer~ed embodimer'r o~ the i~vention, those skilled in the axt wlll reali that many vasiatlons and modiications may be made to afect the described invention and still b~ within the ~cope of the claimed invention. ~hus, man~ o~ the ele-ments will provide the same resul~s and fall withtn the.
spirlt of the claimed inven~ion. It is the intention, therefore, ~o limit the invention only as indicated b~
the scope of the claims.
What i~ claimed is:

,- -. . ..

Claims (14)

1. A document processing system comprising:
a reader sorter device for reading a document sequentially and generating character signals indica-tive of a character read from said document, and a control character generated by said reader sorter device;
an adapter coupled to said reader sorter device and responsive to said character signal for generating translated character signals identifying said character as a queue field identifier character;
said adapter being further responsive to said character signals for generating character identifier signal identifying said control character as a pseudo queue field identifier character;
a controller coupled to said adapter for re-ceiving said translated character signals representa-tive of said queue field identifier character and said character identifier signals representative of said pseudo queue field identifier character, for designa-ting the boundaries of a field, for transfer to a main memory; and, said controller further receiving said trans lated character signals for generating a start posi-tion character count and an end position character count in said field for transfer to said main memory.

2. The document processing system of claim 1 wherein said adapter comprises:
receiving means coupled to said reader sorter device for receiving said character signals;
random access memory means coupled to said receiving means and responsive to said character sig-nals for selecting said translated character signals, said translated character signals, having a selected one of said translated character signals in a first state, being representative of said character, and said control character, and having said selected one of said translated character signals in a second state being representative of said character being said queue field identifier character;
read only memory means coupled to said receiv-ing means and responsive to said character signals for selecting said character identifier signals having a selected one of said character signals in a first state identifying said character, and having said selected one of said character signals in a second state iden-tifying said control character as said pseudo queue field identifier character; and, multiplexer means, coupled to said random access memory means, and said read only memory means and responsive to controller signals in a first state for selecting said translated character signals, and responsive to said controller signals in a second state for selecting said character identifier signals for transfer to said controller.

3, The document processing system of claim 2 wherein said controller comprises:
control means, coupled to said adapter for generating said controller signals in said first state for selecting said translated character signals, and said controller signals in said second state for selec-ting said character identifier signals;
arithmetic logic unit means coupled to said adapter, and responsive to said translated character signals, having said selected one of said translated character signals in said second state, for generating said queue field identifier character, and responsive to said character identification signals, having said selected one of said character identifier signals in said second state, for generating said pseudo queue field identifier character; and, scratch pad memory means coupled to said arithmetic logic unit means including first means for storing first signals representative of said queue field identifier character in a first address location representative of a field opening queue character;
second means for storing said first signals in a second address location representative of a field closing character; third means for storing second sig-nals representative of said pseudo queue field identi-fier character in said first address location; and fourth means for storing said second signals in said second address location of a scratch pad memory.

4. The document processing system of claim 3 wherein said arithmetic logic unit means is responsive to a succession of said translated character signals in said first state for providing means for generating signals representative of said start position charac-ter count when a first of said succession of said translated character signals having said selected one of said translated character signals in said first state is received, and providing counting means re-sponsive to said succession of said translated charac-ter signals in said first state for generating signals representative of said end position character count.

5. The document processing system of claim 4 wherein said scratch pad memory means further includes fifth means for storing said start position count sig-nals in a third address location, and sixth means for storing said end position count signals in a fourth address location of said scratch pad memory.

6. The document processing system of claim 5 wherein said arithmetic logic means includes means for checking said translated character signals and said character identifier signals for generating signals indicative of the number of illegal characters in said field, said checking means further providing means for generating signals indicative of the number of said illegal characters being less than a predetermined value.

7. The document processing system of claim 6 wherein said checking means further includes means for generating signals indicative of the character posi-tions of said illegal characters is said field.

8. The document processing system of claim 7 wherein said scratch pad memory means further includes seventh means for storing said signals indicative of the character position of said illegal characters in a fifth address location of said scratch pad memory.

9. The document processing system of claim 8 wherein said scratch pad memory means further includes the eighth means for storing said character position signals indicative of the character position of a first of said illegal characters in said field in a sixth address location of said scratch pad memory.

10. The document processing system of claim 9 wherein said scratch pad memory means further include ninth means for storing said character position sig-nals indicative of the character position of a second of said illegal characters in said field in a seventh address location of said scratch pad memory.

11. The document processing system of claim 10 wherein said scratch pad memory means further includes tenth means for storing said character position sig-nals indicative of the character position of a third of said illegal character in said field in an eighth address location of said scratch pad memory.

12. The document processing system of claim 11 wherein said arithmetic logic unit means provides eleventh means responsive to said translated character signals representative of said queue field identifier character for transfer of said first, second, third, fourth, fifth, sixth, seventh and eighth address loca-tion signals to said main memory for processing by a central processor unit.

13. The document processing system of claim 12 wherein said arithmetic logic unit means provides twelfth means responsive to said character identifier signals representative of said pseudo queue field identifier character for transfer of said first, second third, fourth, fifth, sixth, seventh and eighth address location signals to said main memory for processing by a central processor unit.

14. The document processing system of claim 13 wherein said predetermined value is four.